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Warm hints: The word in this article is about 4000 words and  reading time is about 20 minutes.SummaryThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of system clock and the delay of clock to ensure the stability of design. CoreClock in FPGA designPurposeDetermining the influencing factors of clock to ensure the stability of designEnglish nameField Programmable Gate ArrayCategoryDigital electronic circuitFunctionCreating digital circuitsFeatureTotally up to the designer to create a bit fileCatalogsCatalogsⅠ. What is Setup time and Hold timeⅢ. Analyzing with the help of timing diagram3. The composition of the state machine1. Synchronization between single bits and each pulse transmitted has at least 1 cycle width1. Setup timeⅣ. How to increase the clock working frequencyⅤ. An example showing a good method for state machine design2. The input pulse could be less than a synchronous circuit under a clock cycle width 2. Hold time1. Changing the line type for circuit wiringⅥ. The introduction of state machine Ⅱ. A basic model of synchronous design using a single clock2. Splitting the combinational logicⅦ. What we should pay attention when designing the clock in FPGA  IntroductionⅠ. What is Setup time and Hold timeThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of the system clock and the delay of the clock to ensure the stability of the design.Learn how a clock drives all sequential logic in FPGA, from Flip-Flops to Block RAMs; The clock tells you how fast you can run your FPGA;This video demonstrates how to properly deal with multiple clock domains inside your design.1. Setup timeSetup time(Tsu) is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.2. Hold timeHold time(Thd) is defined as the minimum amount of time after the clock's active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.Figure 1 Shows setup time and hold timeFigure 2 If data will change in tsu then it will cause setup violation and if data will change in thd then it will cause hold violation  DtailⅡ. A basic model of synchronous design using a single clockIn the same module of FPGA design, it often contains the combinational logic and the sequential logic. In order to guarantee the data in this logic interface can be processed steadily, then figuring out the concept of setup time and hold time is very important. Then we could be able to think about this following question:Figure 3 Shows a basic model of synchronous design using a single clockTco: Delay of the data output of the trigger;Tdelay: Delay of the combinational logic;Tsetup: The trigger's setup time;Tpd: Delay of the clock (negligible).T: clock cycleT3: D2 setup timeT4: D2 hold timeIf the first trigger D1 has a maximum setup time of T1max and a minimum of T1min, the combinational logic has a maximum delay of T2max and a minimum of T2min. The question is what conditions setup time T3 and hold time T4 of the second trigger D2 should be met, or what the maximum clock cycle given T3 and T4. This is the thing must be carefully considered in the process of design, because only by clarifying this issue can we ensure that the delay of the  combinational logic designed meets the requirements.Ⅲ. Analyzing with the help of timing diagramNow let us analyze this question with the help of timing diagram: let the input of the first flip-flop be D1, the output be Q1; the input of the second flip-flop be D2, the output be Q2;Given the clock is uniformly sampled on the rising edge, for ease of analysis we would discuss two cases, the first one: Assume that the delay of the clock Tpd is zero, which in fact, is often met in the FPGA design where the unified system clock it is generally adopted and the clock be input through the global clock pin, therefore the internal clock delay can be completely ignored. In this case, it is not necessary to consider the hold time, because each data maintains one clock tick while there is also delay line, that is, the delay based on CLOCK is much smaller than the delay based on data, so the hold time can meet the requirement. The setup time is what we should care about. If the setup time D2 meets the requirement, the timing diagram should be as shown as Figure 4.Figure 4 Shows the timing chart that meets the requirementsFrom the figure 4 we can see:T-Tco-Tdelay>T3That is Tdelay< T-Tco-T3During the setup time D2, the signal can reach D2 through the combinational logic D1, i.e. the data is already in Tsup before the second CLK arrive.Then it meets the requirement of setup time, where T as the clock period, the second flip-flop can pick up D2 on the rising edge of the second clock in this case. {D1 => setup time => hold time => trigger data output delay => combinational logic delay => D2 => ...}If the delay time of the combinational logic is too largeT-Tco-Tdelay < T3 (Tcox<D2 setup time)Then it will not meet the requirements. The second trigger will pick up an unstable state on the rising edge of the second clock, as shown in Figure 5, then the circuit will not work properly.Figure 5 The delay time of the combinational logic is too large to meet the requirementsSo you can deriveT - the Tco - T2max > = T3This is the setup time for D2.From the timing diagram above, it also can be seen that the setup time and hold time of D2 are not related to the setup and hold time of D1, except the combinational logic in front of D2 and the data transmission delay of D1. This is also a Very important conclusion, which shows that the delay has no additive effect.However, if there is a delay in the clock instead, the hold time must be considered in this case, together with the setup time. Most clocks with large delays are designed using asynchronous clocks, which is difficult to guarantee the data synchronization, so it is rarely used in actual designs. At this point, if the setup time and hold time all meet the requirements, you will see the output timing as shown in Figure 6.Figure 6. Clock has a delay but meets the timingIt can be easily seen from figure 5 that the Tpd is relaxed for the setup time, so the setup time of D2 must meet the requirements:Tpd+T-Tco-T2max>=T3 (T3 is the setup time of D2, T2max is the maximum delay of  combinatorial logic, Tpd is the clock delay)As shown in the FIG. 6, since the sum of setup time and hold time is a stable clock period (T), if the clock has a delay and the data delay is small, then the setup time will increase inevitably,  and the decrease of hold time goes with it. If it is reduced to not meet the requirement of hold time D2 , the correct data cannot be collected.That is T-(Tpd-Tco-T2min)T-(Tpd+T-Tco-T2min)>=T4 i.e. Tco+T2min-Tpd>=T4 (D2 hold time )From the formula above we could also figure out that if Tpd = 0, that is to say the delay of the clock is 0, then the same requirements goes with Tco + T2min> T4, however in practical applications the delay of T2 i.e. the delay of line is much larger than the trigger's hold time T4, it becomes not necessary to take the hold time into consideration.Figure 7 The clock has a delay and the hold time does not meet requirementsIn summary, if you do not consider the delay of the clock, the only thing you need to care about is the setup time, or the hold time instead. Then let us think about in FPGA design, how to increase the working clock in the synchronous system. AnalysisⅣ. How to increase the clock working frequencyFrom the above analysis, we can see that the requirements of setup time T3 for the D2 in the synchronization system is as follows:T-Tco-T2max>=T3So it is easy to derive:T>=T3+Tco+T2maxwhere T3 is the setup time Tset of D2, and T2 is the delay time of the combinational logic. In a design, T3 and Tco are both fixed values determined by the device, the only factor that we could control is the input delay of the combination logic T2. Therefore, by reducing T2 as much as possible, the clock working frequency can be increased. In order to achieve the reduction of T2 in the design, there are different comprehensive methods we can use.1. Changing the line type for circuit wiringAltera devices, for example, there are many bars in the quartus timing closure floorplan, so we can slice and dice them into rows and columns: Each bar represents 1 LAB, each LAB has 8 or 10 LEs in. The relationship of their routing delay is as follows: the same LAB (fastest) < the same row and column < different row and column. We could add appropriate constraints to the synthesizer (this should be given appropriate, generally 5% margin adding, for example, if the circuit works at 100Mhz, then adding constraints to 105Mhz is sufficient, because the excessive constraint could do a bad effect instead, and greatly increases the integration time) to make the relevant logic circuit wiring be placed as close as possible, thereby reducing the routing delay.2. Splitting the combinational logicSince the general synchronous circuits are more than a?single?stage latch (as shown in Figure 9), and to make the circuit stable, the clock period must meet the maximum delay requirement, and the maximum?delay of the longest path can be shortened before the operating frequency of the circuit be increased.As shown in Figure 8, we can decompose the larger combinatorial logic into smaller blocks and insert flip-flops in the middle, which can increase the operating frequency of the circuit. This is also the basic principle of the so-called "pipelining" technology.For the upper part of Figure 9, its clock frequency is subject to the delay of the second larger combinational logic. By appropriately distributing the combinational logic, excessive delay between the two flip-flops can be avoided and speed bottlenecks can be eliminated.Figure 8 Splitting combination logicFigure 9 Transferring Combination LogicHow to split the combinatorial logic in design, the better method should be accumulated in practice, but some good design ideas and methods also need to be mastered. We know that at present most of the FPGAs based on 4-input LUTs, if an output criteria corresponding is more than four inputs, then the multiple LUT cascade will be needed, thus introducing the delay of one-stage combinational logic. That is we want to reduce the number of combinational logic, the logic is nothing more than to make the input conditions as few as possible, so that less multiple LUT cascade need to be use, thereby reducing the time delay caused by combinational logic.The pipelining that we usually hear is a way to increase the operating frequency by splitting a large combinational logic (in the middle of which a singer or multiple stages of D flip-flops are inserted, thereby reducing the number of combinatorial logic between registers) to a smaller one. For example, a 32-bit counter, with a very long carry chain, will inevitably reduce the operating frequency, so we can split it into a 4-bit and a 8-bit one, whenever the 4-bit counter counts to 15 and triggers an 8-bit one, which enable the counter to be split and increases the operating frequency.Just as the same, large counters are generally moved out of the state machine, because if they, with usually more than 4 inputs, are used as state transition criteria with other conditions, they will increase the multiple LUT cascade, and then increasing the combination logic.Taking a 6-input counter as an example, we wanted to make a state transition after the counter counted to 111100, now because we put the counter out of the state machine, when it counts to 111011, a signal of "enable" is generated and then trigger the state transition, which obviously reduces the combinatorial logic.3. The composition of the state machineThe state machine generally contains three modules:An output moduleA module that determines what the next state isA module that saves the current stateThe logic used to form these three modules is also different. The output module usually contains both combinatorial logic and sequential logic; the module that determines the next state is usually composed of combinatorial logic; and the module that saves the current state is usually composed of sequential logic. The relationship between these three modules is shown in Figure 10.Figure 10 The composition of the state machineⅤ. An example showing a good method for state machine designThat is why when writing the state machine, the state machine is always divided into three parts according to these three modules. The following example shows a good method of state machine design: -----------------------------------------------------*/module arbiter2 (                    clock , // clock                    reset , // Active high, syn reset                    req_0 , // Request 0                    req_1 , // Request 1                    gnt_0 ,                    gnt_1                );//-------------Input Ports-----------------------------input    clock ;input    reset ;input    req_0 ;input    req_1 ;//-------------Output Ports----------------------------output    gnt_0 ;output    gnt_1 ;//-------------Input ports Data Type-------------------wire    clock ;wire    reset ;wire    req_0 ;wire    req_1 ;//-------------Output Ports Data Type------------------reg        gnt_0 ;reg        gnt_1 ;//-------------Internal Constants--------------------------parameter     SIZE = 3 ;parameter     IDLE = 3'b001 ,            GNT0 = 3'b010 ,            GNT1 = 3'b100 ;//-------------Internal Variables---------------------------reg        [SIZE-1:0] state ;        // Seq part of the FSMwire    [SIZE-1:0] next_state ;    // combo part of FSM //----------Code startes Here------------------------assign    next_state = fsm_function(req_0, req_1);//------------fsm_function--------------//function [SIZE-1:0] fsm_function;input     req_0;    //parameterinput     req_1;    //parameterbegin    case(state)        IDLE :                if (req_0 == 1'b1)                    fsm_function = GNT0;            else if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function = IDLE;        GNT0 :             if (req_0 == 1'b1)                fsm_function = GNT0;            else                fsm_function = IDLE;        GNT1 :            if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function =IDLE;        default : fsm_function = IDLE;        endcaseendendfunction always@(posedge clock)begin    if (reset == 1'b1)        state <= IDLE;    else        state <= next_state;end//----------Output Logic-----------------------------always @ (posedge clock)begin    if (reset == 1'b1)         begin        gnt_0 <= #1 1'b0;        gnt_1 <= #1 1'b0;        end    else         begin        case(state)            IDLE :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end            GNT0 :                 begin                gnt_0 <= #1 1'b1;                gnt_1 <= #1 1'b0;                end            GNT1 :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b1;                end            default :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end        endcase        endend // End Of Block OUTPUT_Endmodule Ⅵ. The introduction of state machineState machines are usually written in three segments to avoid excessive combinational logic.All we mentioned above shows how we could use the way of pipelining to split the combinational logic, but in some cases it is difficult for us to do that, and then what should we do?The state machine is such an example that we cannot add assembly line in the state decoding combinational logic. If there is a design of state machine with dozens of states, there is no doubt that its state decoding logic will be very large and this will be the critical path in the design. So what should we do?Just the same way, reducing the combinatorial logic. We can analyze the output of the state, reclassify and redefine them into a group of small state machines. By selecting the input (case statement) and triggering the corresponding small state machine, we can achieve a large state machine splitting into several small state machines. In the ATA6 specification (hard disk standard), there are about 20 kinds of input commands, and each piece of command corresponds to a variety of states. It is unthinkable to do it with a large state machine (nesting), however in the contrary, if you use the case statement to decode the command and trigger the corresponding state machine, in this way the module can run very fast.The key to increasing the operating frequency is to reduce the time delay from register to register, and the most effective method for reduction is to avoid large combinational logic, that is, to try to meet the four-input condition, reducing the number of LUT cascades, that’s mean that we could increase the working frequency by adding constraints, using a way of pipelining and splitting states.Ⅶ. What we should pay attention when designing the clock in FPGA1.Try to use only one clock in a module, and a module here means a module or an entity. In the design of multi-clock domain, it is better to have an extra special module for the isolation of clock domain. This allows the synthesizer to get a better results.2. Unless it is a low-power design, otherwise do not use the gated clock (gllobal Clock buffer such as IBUFG within FPGA) to control the input of clock edge of flip-flop, but use combinational logic and other timing logic (such as frequency divider) to generate signals used as the input of clock edge of flip-flop---all this is to reduce the instability of the design.3. Do not use the signals divided by counter as the clock of other modules, but  with the help of clock enable(CE). Otherwise, this clock-like manner is extremely unfavorable to the reliability of the design, and greatly increases the complexity of the static timing analysis .Ⅷ. Synchronization Between Different Clock DomainsIf two modules in a design using two respective operating clock, then at their interfaces there would emerge a phenomenon which called as Asynchronous Patterns. In order to ensure data correct processed, the two modules must be synchronized.There are usually two cases of different clock domains here (discrete clock source):1. the frequency of two clocks is different;2. the two clocks share a same frequency, but they are actually two separate clocks with no relation to the phase.Just as shown in the following two figures:Figure 11 The frequencies of two clocks are completely differentFigure 12 The frequencies of the two clocks are the same, but the phases are irrelevantThe data transmission between two clock domains usually adopts different synchronization methods according to different bit widths.1. Synchronization between single bits and each pulse transmitted has at least 1 cycle widthThis kind of synchronization is mainly used for the synchronization of some control signals. As shown in Figure 13 below:Figure 13 One bit synchronizer designThe following points are required to be explained for this synchronization:(1) synchronous circuit of figure 12 is actually called "one bit synchronizer", it can only be used for one bit asynchronous signal which must be wider than that of the Current stage’s clock, otherwise it may be unable to adopt this asynchronous signal.(2) why is the circuit in figure 13 can only be used in one bit asynchronous signals?When two or more asynchronous signals (control or address) simultaneously get into the current time domain and take control the circuit of current time domain, problems arise if these signals are all synchronized using the same circuit in FIG. 13. Skews has arisen between two or more asynchronous signals (control or address) due to connection delays or other delays, and then the skew is greatly enlarged via the synchronizer in Figure 13 when getting into the current time domain, or competition may caused and finally leading to an error in the time domain circuit.Figure 14 Problem-passing multiple control signals between clock domainsIf the asynchronous data bus is to enter the current time domain, the circuit in Figure 13 cannot be used either, because data change very randomly and the width of 0 or 1 has nothing to do with the clock pulse of the current time domain, so the circuit in Figure 13 may be unable to adopt the correct data.(3) Please note that the second trigger is not used for avoiding the occurrence of "metastable state", on the contrary, it can prevent the transmission of metastable state. In other words, once the first flip-flop becomes metastable (possibly), due to the second flip-flop, the metastability will not be transmitted to the circuit following.(4) The first-stage trigger has a metastable state, which means it will require a recovery time to stabilize again, or it is also called Withdrawal from metastable state. The recovery time plus the establishment time of the second-stage flip-flop (say more precisely, maybe also minus the clock skew) is less than or equal to the clock period, which can be easily satisfied. This is means thees two stages of flip-flop should be put together as close as possible, without any combinatorial logic between them or excessive skews to the clock, and then the second-stage flip-flop can adopt data stably and preventing the transmission of metastable state.(5) FF1 is the sampling output of FF2, so of course, what is output by FF1 is  what output by FF2, everything is the same except one cycle of delay. Note that “meta-stableit” means that once the data of FF1 enters, its electrical level would be indefinite and maybe incorrect. So although this method can prevent transmission of metastable state, it does not guarantee the data after the two-stage flip-flop is correct. Therefore, this kind of circuit always has a certain amount of fault-tolerance. This applies only to a some error-insensitive cases, but for other sensitive circuits, dual-port RAM or FIFO are better choices.2. The input pulse could be less than a synchronous circuit under a clock cycle width How is that possible? Has it not less than the original clock? For this case, the Feedback shown in Figure 15 below may usually be taken into consideration. The analysis of this circuit is as follows: Assume that the input data is high level, because the first flip-flop FF1 is high-level cleared, then all outputs should also be high and correctly adopted. On the other hand, if the input is low-level, data of FF1 would be forced to clear and the output level is zero, which ensures the correctness of the output.Figure 15 Synchronous circuit--input pulse may be less than one clock cycle width  Book SuggestionBuilding Embedded Systems: Programmable Hardware 1st ed. EditionThis is a book for embedded-system engineers and intermediate electronics enthusiasts who are seeking tighter integration between software and hardware. Those who favor the System on a Programmable Chip (SOPC) approach will in particular benefit from this book. Students in both Electrical Engineering and Computer Science can also benefit from this book and the real-life industry practice it provides.--Changyi GuDigital Integrated Circuit Design Using Verilog and Systemverilog 1st Edition, Kindle EditionFor those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. --Ronald W. MehlerPower Converters with Digital Filter Feedback Control 1st Edition, Kindle EditionThis book builds a bridge for moving a power converter with conventional analog feedback to one with modern digital filter control and enlists the state space averaging technique to identify the core control function in analytical, close form in s-domain (Laplace). It is a useful reference for all professionals and electrical engineers engaged in electrical power equipment/systems design, integration, and management.--Keng C. Wu Relevant information "Discussion on the influencing factors of clock in FPGA design"About the article "Discussion on the influencing factors of clock in FPGA design", If you have better ideas, don't hesitate to  write your thoughts in the following comment area. You also can find more articles about electronic semiconductor through Google search engine, or refer to the following related articles.To Solve the Problems of Cloud Skyrocket--Edge ProcessingFPGAs Power Facial Recognition Technology Was Issued by NECNew Software for C2000 MCUs Eliminates the FPGA in industrial designsCustomisable Ethernet switch designed for embedded applicationsMouser signs Intel FPGA board firm ReFLEX CES

Catalog Introduction Design Flow of Chip Design Specification Development Design Details of the Chip Draw a Blueprint for the Plane About Wafer What Is a Wafer How to Make Single Crystal Wafer Metallurgical Purification Pulling the Crystal Design Flow of Chip Manufacture What Is an IC Chip Metal Sputtering Coating Photoresistance Etching Technology Photoresist Removal Nano-Process What Is the Nano-Process How Tiny Is the Nanometer Purpose of Reducing the Process Physical Limitations of Downsizing About Encapsulation Two Common Packages DIP Package BGA Package Two Ways to Reduce Size SoC SiP Introduction A chip is a silicon chip that contains an integrated circuit, so the chip is also called an integrated circuit. It may be only 2.5 centimeters in square size, but it contains tens of millions of transistors. Simpler processors, on the other hand, may have thousands of transistors engraved on chips which are a few millimeters in size. Chip is the most important part of electronic equipment, which undertakes the function of operation and storage. Design Flow of Chip The birth of a chip can be divided into two parts: design and manufacture. First, let's take a look at the complex and tedious chip design process. Fig 1. The process of making a chip is like building a house with Lego. First, the wafer is used as the foundation and the necessary IC chips can be produced after layers are stacked on top of each other. However, there is no use in having no amount of manufacturing capacity without a design drawing. Therefore, the role of an architect is very important. But who is the architect in IC's design? The next step is to introduce the IC design. In the IC production process, IC is mostly planned and designed by professional IC design companies, such as MediaTek, Qualcomm, Intel and other well-known large factories, all of which design their own IC chips to provide different specifications and efficiency chips for downstream manufacturers to choose from. Because IC is designed by the factories themselves, so IC design depends very much on the technology of engineers and the quality of engineers affects the value of an enterprise. But what are the steps engineers take to design an IC chip? The design process can be simply divided into the following steps. Design Specification Development In IC design, the most important step is specification development. This step is like deciding how many rooms, bathrooms, what building codes to comply with, and designing after all the features have been identified so that no additional time is spent on subsequent modifications. The IC design needs to go through similar steps to ensure that the chip is designed without any errors. The first step in specification development is to determine the purpose and effectiveness of IC and to set the general direction. The next step is to see what protocols to comply with, such as the wireless card chip needs to comply with IEEE 802.11 and other specifications. Otherwise, the chip will not be compatible with the products on the market, so that it will not be able to connect to other devices. Finally, the implementation method of this IC is established, different functions are allocated into different units, and the method of connecting different units is established, so that the specification can be completed. Design Details of the Chip After designing the specifications, it is followed by the details of the design chip. This step is like making a preliminary note of the planning of the building and depicting the overall outline for subsequent drawing. In IC chip, the hardware description language (HDL) is used to describe the circuit. The commonly used HDLs are Verilog, VHDL, and so on, which can easily express the function of a IC by code. This is followed by checking the correctness of the program's functionality and continuously modifying it until it meets the desired functionality. Fig 2. Verilog Example of 32 Bits Adder Draw a Blueprint for the Plane With a complete plan, the next step is to draw a blueprint for the plane. In IC design, the step of logic synthesis is to put the unmistakable HDL code into the electronic design automation tool (EDA tool), to let the computer convert HDL code into logic circuit, resulting in the following circuit diagram. After that, it is repeatedly determined whether the logic gate design conforms to the specification and is modified until the function is correct. Fig 3. The Result of the Synthesis of the Control Unit Finally, the synthesized code is put into another set of EDA tool for circuit layout and winding (Place And Route). After continuous detection, the following circuit diagram will be formed. You can see blue, red, green, yellow and other different colors, each of which represents a mask. As for the use of the mask, how should it be used? Fig 4. The Commonly Used Calculus Chip-FFT Chip, Which Completes the Circuit Layout and the Winding Result ——The chip is stacked by layers of masks. First of all, it is now known that an IC will produce multiple masks. These masks have the difference between the upper and lower layers and each layer has its own task. The following figure is a simple mask example. Taking the most basic element CMOS in the integrated circuit as an example, the full name of CMOS is complementary metal oxide semiconductor. That is, the combination of NMOS and PMOS to form CMOS. As for what is a metal oxide semiconductor (MOS)? This kind of component which is widely used in the chip is more difficult to explain, and it is more difficult for the general reader to figure it out, so there is no more detailed study here. In the following figure, on the left is the circuit diagram formed after the circuit layout and winding, and you have already known that each color represents a mask. On the right is the way each mask is spread out. Production is to start from the bottom, in accordance with the method proposed in the manufacture of the IC chip, layer by layer, and finally the desired chip will be produced. Fig 5.  At this point, you should have a preliminary understanding of the IC design. The overall view is very clear that IC design is a very complex major, but also thanks to the maturity of computer-aided software, so that IC design can be accelerated. The IC design relies heavily on the wisdom of engineers, and each of the steps described here has its own expertise and can be separated into multiple professional courses. For example, writing a hardware description language does not simply require familiarity with the programming language. You also need to understand how logic circuits work, how to convert the required algorithms into programs, and how synthetic software converts programs into logic gates. What Is a Wafer? In semiconductor news, it is always mentioned in the size of the wafer, such as 8-inch or 12-inch wafer. But what is the so-called wafer? What part of it is 8 inches? What is the difficulty of producing large wafers? Here is a step-by-step introduction to the most important foundation of semiconductors-what is a "wafer". Wafer is the basis for making all kinds of computer chips. We can compare chip manufacturing to building a house with Lego blocks and building the shape we want (that is, all kinds of chips) by stacking one layer after another. However, if there is no good foundation, the built house will be tilted back and forth, contrary to our wishes. In order to make the perfect house, we need a smooth substrate. For chip manufacturing, this substrate is the wafer that will be described next. First of all, think back to when you were a child playing with Lego blocks, there would be a small round bulge on the surface of the building blocks. With this structure, we can stack the two blocks firmly together without using glue. Chip manufacturing, also in a way like this, binds subsequent atoms to the substrate. Therefore, we need to find a substrate with a neat surface in order to meet the conditions needed for subsequent manufacturing. Fig 6. In solid materials, there is a special crystal structure. That is, single crystal (Monocrystalline). It has the characteristics of atoms one after another closely arranged together, which can form a flat atomic surface. Therefore, using single crystal to make wafer can meet the above needs. However, how to produce such a material? There are two main steps, respectively, purification and crystal pulling. After this, such a material can be completed. How to Make Single Crystal Wafer? Metallurgical Purification The purification is divided into two stages. The first step is metallurgical purification. During this process, we add carbon and convert silicon oxide into silicon with a purity of more than 98% in a redox manner. Most metals, such as iron or copper, are refined in this way to obtain sufficient purity of metal. However, 98% is still not enough for chip manufacturing and still needs to be further improved. Therefore, Siemens process will be used for purification, so that the high purity polysilicon needed for semiconductor process will be obtained. Fig 7. Silicon Column Manufacturing Process Pulling the Crystal Then there is the step of pulling the crystal. First, the high purity polysilicon obtained earlier is melted to form liquid silicon. After that, the single crystal silicon seed is in contact with the liquid surface and slowly pulls up as it rotates. As for why single crystal silicon is needed, that is because silicon atoms are arranged in the same way as people queue up. They will need to arrange the head so that later people can arrange it correctly. And silicon seed is an important row head, so that the later atoms know how to queue up. Finally, after the silicon atoms leaving the liquid surface solidify, the neatly arranged single crystal silicon columns are completed. Fig 8. Single Crystal Silicon Column But what do 8 inches and 12 inches stand for? It refers to the diameter of thin wafers being treated and sliced into，which is from the surface of the part of a crystal column that looks like a pencil rod. What is the difficulty of making large wafers? As mentioned earlier, the crystal column is made as if it were making marshmallows, rotating and forming at the same time. If you have made marshmallows, you should know that it is very difficult to make large and solid marshmallows, and the same is true of the crystal pulling process. The speed of rotation and the control of temperature will affect the quality of the crystal column. As a result, the larger the size, the higher the speed and temperature requirements are, so it is more difficult to make high-quality 12-inch wafers than 8-inch wafers. However, a whole silicon column cannot be made into a chip-making substrate. In order to produce a silicon wafer, the silicon column needs to be cut transversely into a wafer with a diamond knife, and the wafer can be polished to form the silicon wafer needed for chip manufacturing. After so many steps, the fabrication of the chip substrate is complete, and the next step is to stack the house, that is, chip manufacturing. So, how to make a chip? Manufacture ——Stacked chips After introducing what silicon wafers are, you also know that making IC chips is like building a house with Lego blocks, creating the shape you want by stacking layer after layer. However, there are quite a few steps to build a house, and so is IC manufacturing. What are the steps to make IC? Next, the process of IC chip manufacturing will be introduced. What Is an IC Chip? Before we begin, we need to know what an IC chip is. IC, which means integrated circuit (Integrated Circuit), is the design of the circuit that is in the form of stacking together. In this way, we can reduce the area required to connect the circuit. The following figure is a 3D diagram of the IC circuit, from which you can see that its structure is like the beams and columns of a house. It is done layer by layer and this is the reason why IC manufacturing is compared to building a house. Fig 9. 3D Profile of IC Chip From the 3D profile of the IC chip in the image above, the dark blue part at the bottom is the wafer introduced in the previous step. From this picture, we can see more clearly how important the wafer substrate plays in the chip. As for the red and khaki parts, they are the places to be completed when IC is made. First of all, the red part can be compared to the hall on the first floor of the building. The hall on the first floor is the door of a house because everyone and everything come in and out of here. It has more functionality under the control of traffic. Therefore, compared with other floors, the construction will be more complex and requires more steps. In IC circuit, this hall is the logic gate layer; it is the most important part of the whole IC by combining a variety of logic gates together and completes the fully functional IC chip. The yellow part is like a normal floor. Compared with the first floor, there will not be much complex structure, and each floor will not change much when it is built. The purpose of this layer is to connect the logic gates of the red part. The reason why so many layers are needed is that there are so many lines to be connected that a single layer cannot hold all the lines. So it is necessary to stack a few more layers to achieve this goal. Among them, the lines of different layers will be connected up and down to meet the needs of the wiring. ——Layered construction, layer by layer architecture Once you know the construction of IC, let's show you how to make it. Imagine that if we want to make a fine drawing with a paint spray tank, we need to cut out the cover plate of the figure and cover it on paper. Then spray the paint evenly on the paper and remove the mask when the paint is dry. After repeating this step over and over again, you can complete neat and complex graphics. IC is made in a similar way, by covering up a layer of stacking. Fig 10.  When making IC, you can simply divide into the above four steps. Although the actual manufacturing steps will be different and the materials used will be different, but generally using a similar principle. This process is slightly different from painting: IC manufacturing is to paint first and then cover while painting is to cover and then paint. And the processes are described below. Metal sputtering:  Sprinkle the metal material which is to be used evenly on the wafer to form a thin film. Coating photoresistance:  First put the photoresist material on the wafer, and then hit the beam on the desired part through the mask to destroy the structure of the photoresist material. Next, use chemicals to wash away the damaged material. Etching technology:  The silicon wafer without photoresistance protection will be etched by ion beam. Photoresist removal:  Use the photoresist solution to dissolve the remaining photoresist, so that a process can be completed. Finally, a lot of IC chips will be completed on a whole wafer, and then as long as the completed square IC chips are cut off, they can be sent to the packaging factory for packaging. What is the packaging factory? We'll have to explain it later. Nano-Process What is the nano-process? Samsung and TSMC compete fiercely in advanced semiconductor processes because both of them want to take the lead in wafer contract manufacturing to win orders, which has almost become a battle between 14 nanometers and 16 nanometers. But what is the meaning of 14 nm and 16 nm, and where do they refer? What are the benefits and problems that will be brought about by the reduction of the process? Next we will give a brief description of the nano-process. How tiny is the nanometer? Before you start, you need to understand what nanometer really means. Mathematically, nanometers are 0.000000001 meters, but this is a pretty bad example. After all, we can only see a lot of zeros after the decimal point, but we don't actually feel it. If you compare it with the thickness of nail, it may be more obvious. If you actually measure it with a ruler, you can tell that the thickness of the nail is about 0.0001 meters (0.1mm), that is to say, try to cut the side of a nail into 100000 lines, each of which is about one nanometer. From this, we can slightly imagine how tiny a nanometer is. Purpose of Reducing the Process After knowing how small the nanometer is, it is necessary to understand the purpose of reducing the process. The main purpose of reducing the transistor is to insert more transistors into smaller chips so that the chip will not become larger as a result of technological advances; second, it can increase the computational efficiency of the processor; moreover, reducing the volume can also reduce the power consumption. Finally, after the chip size is reduced, it is easier to plug into the mobile device to meet the needs of thinness and lightness in the future. Come back to explore what the nano-process is and we will take 14 nm as an example. The process refers to the minimum size of 14 nm in the chip. The following figure shows the appearance of a traditional transistor, as an example. The main purpose of reducing transistor is to reduce power consumption, but which part needs to be reduced to achieve this goal? The L in the figure on the left is what we expect to shrink. By reducing the gate length, the current can be routed from the Drain side to the Source end in a shorter path (if you are interested, you can use Google to search for MOSFET, which will be explained in more detail). Fig 11. In addition, computers operate on 0 and 1. How can we use transistors to meet this purpose? The way to do this is to determine whether the transistor has current flow. When a voltage supply is made at the Gate (green square), the current will flow from the Drain to the Source, and if there is no supply voltage, the current will not flow, so that it can represent 1 and 0. (As to why 0 and 1 are used to judge, if you are interested, you can go to the Brin algebra. That is the way we use this method to make a computer.) Physical Limitations of Downsizing However, the process cannot be reduced indefinitely. When we narrow the transistor to about 20 nanometers, we will encounter problems in quantum physics, so that the transistor has a leakage phenomenon, offsetting the benefits of L. As a way to improve, the concept of FinFET (Tri-Gate) was imported, as shown in the figure above. The leakage caused by physical phenomena can be reduced by importing this technology. Fig 12. More importantly, this method can increase the contact area between the Gate end and the lower layer. In traditional practice (top left), the contact surface has only one plane, but with FinFET (Tri-Gate), the contact surface will become three-dimensional, and the contact area can be easily increased. This allows the Source-Drain side to be smaller while maintaining the same contact area, which is of considerable help in reducing the size. Finally, why would anyone say that it would be a pretty serious challenge for factories to enter the 10-nanometer process? It is mainly because the size of an atom is about 0.1 nanometers, and in the case of 10 nanometers, there are fewer than 100 atoms in a line. It is very difficult to make, and as long as there is an atomic defect, such as atoms falling out or impurities in the production process, there will be unknown phenomena, affecting the yield of the product. If you can't imagine the difficulty, you can do a small experiment. Line up a 10 × 10 square with 100 small beads on the table, cut a piece of paper to cover the beads, then brush off the beads next to it with a small brush, and finally make it form a 10 × 5 rectangle. In this way, we can know the difficulties faced by the major factories and how difficult it is to achieve this goal. Encapsulation After a long process, from design to manufacture, finally we got an IC chip. However, a chip is so small and thin that it can be easily scratched and damaged if it is not protected from the outside. In addition, because of the small size of the chip, if you do not use a larger size of the shell, it will not be easy to manually place on the circuit board. Therefore, the next step is to describe the encapsulation: Two Common Packages At present, there are two common packages; one is the DIP package, which is common in electric toys and looks like a centipede, the other is the BGA package, which is common when buying boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array) used in the early CPU or an improved version of QFP (plastic square flat package) of DIP. Because there are so many packaging methods, only DIP and BGA encapsulation are described below: ——Enduring Traditional Packaging DIP Package The first thing to introduce is the Dual Inline Package (DIP), we can see from the following figure that the IC chip with this package will look like a black centipede at the foot of the dual inline connection and this is the earliest IC packaging technology. It has the advantage of low cost and is suitable for small chips without too many wires. However, because most of them are plastic, the heat dissipation effect is poor, which cannot meet the requirements of the current high-speed chips. Therefore, most of the chips using this package are durable chips, such as OP741 shown in the following figure or smaller IC chips with less speed requirements and fewer holes. Fig 13.  The IC chip shown on the left is a common voltage amplifier named OP741. On the right is its section. The package connects the chip to the leadframe with a gold wire. BGA Package As for spherical array (Ball Grid Array,BGA) packaging, compared with DIP, it is smaller and can be easily placed in smaller devices. In addition, because the pin is located under the chip, it can hold more metal pins than the DIP so it is Ideal for chips that require more contacts. However, the cost of this packaging method is high and the connection method is more complex, so it is mostly used in high unit price products. Fig 14.  On the left is a chip encapsulated in BGA. On the right is a schematic diagram of BGA using a cladding packaging. ——The rise of mobile devices and the emergence of new technologies on the stage Two Ways to Reduce Size However, the use of these packaging methods will cost a considerable amount of volume. For example, today's mobile devices, wearing devices, and so on, require quite a variety of components. If each component is packaged independently, it will cost a lot of space. Therefore, there are two ways to meet the requirements of reducing size. They are SoC (System On Chip) and SiP (System In Packet). SoC At the beginning of the rise of smart phones, the term SoC can be found in major financial magazines, but what is SoC? To put it simply, ICs with different functions are integrated into one chip. By this method, not only the volume can be reduced, but also the distance between different IC can be reduced, and the calculation speed of the chip can be improved. As for the manufacturing method, during the IC design phase, different ICs are put together and then a mask is made through the design process described earlier. However, SoC is not the only advantage; to design a SoC requires considerable technical cooperation. When IC chips are encapsulated, they have their own external protection, and the distance between IC and IC is long, so there is no interactive interference. But when all the ICs are wrapped together, it is the beginning of a nightmare. The IC design factory has to change from the original simple design IC, to the IC which requires them to understand and integrate the various functions. Therefore, it increase the workload of engineers. In addition, there will also be a lot of situations, such as the high-frequency signal of the communication chip may affect the IC of other functions and so on. In addition, SoC also needs to obtain IP (intellectual property) authorization from other vendors in order to put components designed by others into SoC. Because making SoC needs to obtain the design details of the whole IC in order to make a complete mask, which also increases the design cost of SoC. Some people may question why not just design one by yourself. That is because designing all kinds of IC requires a lot of knowledge related to the IC, only a rich enterprise like Apple can have a budget to poach top engineers from well-known enterprises. It's still a lot cheaper to design a whole new IC through collaborative licensing than to develop it by yourself. SiP As an alternative, SiP has leapt onto the stage of integrating chips. Unlike SoC, it buys IC from different enterprises and finishes the last step, which is to encapsulate the IC. In this way, the IP licensing step is eliminated and the design cost is significantly reduced. In addition, because they are independent ICs, the degree of interference with each other is greatly reduced. Fig 15. Apple Watch uses SiP technology to package the entire computer architecture into a chip, not only to meet the desired performance but also to reduce the size, so that the watch has more space for battery release. The most famous product using SiP technology is Apple Watch. Because the internal space of Watch is too small, it cannot use the traditional technology, the design cost of SoC is too high, SiP has become the first choice. With SiP technology, not only the volume can be reduced, but also the distance between each IC can be shortened, so SiP can be a feasible compromise. The following figure shows the structure of the Apple Watch chip, and you can see that quite a few IC are included in it. Fig 16. Internal configuration Diagram of S1 Chip encapsulated by SiP in Apple Watch After the packaging is completed, we will enter the testing stage. At this stage, it is necessary to confirm whether the encapsulated IC is functioning properly and that it can be shipped to the assembly plant after it is correct, so that the electronic products we can see can be made. So far, the semiconductor industry has completed the task of the whole production.