mosfet Related Articles
Stay Ahead with Expert Electronics Insights,
Industry Trends, and Innovative Tips
- Electronic Components
- News Room
- General electronic semiconductor
- Components Guide
- Sort by
- Robots
- Transmitters
- Capacitors
- IC Chips
- PCBs
- Connectors
- Amplifiers
- Memory
- LED
- Diodes
- Transistors
- Battery
- Oscillators
- Resistors
- Transceiver
- RFID
- FPGA
- Mosfets
- Sensor
- Motors, Solenoids, Driver Boards/Modules
- Relays
- Optoelectronics
- Power
- Transformer
- Fuse
- Thyristor
- potentiometer
- Development Boards
- RF/IF
- Semiconductor Information
- Sensors
- PCB
- transistor
Toshiba America Electronic Components, Inc. (TAEC) has expanded its U-MOS IX-H Series of low-voltage N-channel power MOSFETs with the addition of new 40V and 45V products. Delivering high-speed performance and industry-leading1 low on-resistance, the new MOSFETs are designed for industrial and consumer applications, including high-efficiency DC-DC converters, high-efficiency AC-DC converters, power supplies, and motor drives. The new MOSFETs utilize Toshiba’s latest generation low-voltage trench structure U-MOS IX-H process to lower the performance index for “RDS(ON) Qsw”2 figure of merit, improving switching applications to a level that surpasses other offerings3. Output loss is improved by the reduction of output charge, which can contribute to higher set efficiency. Additionally, the cell structures used in the new MOSFETs are optimized to suppress spike voltage and ringing during switching, which can contribute to lowering set EMI. Toshiba’s U-MOS IX-H Series is specifically designed for synchronous rectification applications, including the secondary side of isolated switching power supplies. It provides an improved Qoss4 performance, which is one of the main causes of power loss of synchronous rectification. The U-MOS IX-H Series also provides a low Ron•Qoss, the trade-off characteristics between on-resistance and Qoss. Since Ron has a significant impact on Qoss, Toshiba will extend the U-MOS IX-H portfolio to include MOSFETs having ultra-low Ron in order to supplement its U-MOS VIII-H Series of MOSFETs. Features·Low on-resistance·Low output charge·High-speed performance·Low switching noise·Supports 4.5V logic level drive *About TAECThrough proven commitment, lasting relationships and advanced, reliable electronic components, Toshiba enables its customers to create market-leading designs. Toshiba is the heartbeat within product breakthroughs from OEMs, ODMs, CMs, VARs, distributors and fabless chip companies worldwide. A committed electronic components leader, Toshiba designs and manufactures high-quality flash memory-based storage solutions, solid state drives (SSDs), hard disk drives (HDDs), solid state hybrid drives (SSHDs), discrete devices, custom SoCs/ASICs, imaging products, microcontrollers, wireless components, mobile peripheral devices, and advanced materials that make possible today’s leading smartphones, tablets, cameras, medical devices, automotive electronics, industrial applications, enterprise solutions and more. Ref.KY68-VS75B-24KY68-DS1200D
kynix On 2017-06-29
Isolation comes from ADI’s ADuM4135 isolated gate driver (see diag below), with IXYS IXDN630YI booster providing silicon carbide gate drive voltages. “The design provides customers with an isolated dual-gate driver switch for evaluating SiC mosfets in a number of topologies, said Microsemi. This includes modes optimised for half-bridge switching with synchronous dead time protection and asynchronous signal transfer with no protection.” It can also be configured for concurrent drive to study un-clamped inductive switching (UIS) or double pulse testing, and the board supports changing gate resistor values to accommodate different mosfet characteristics. According to Microsemi, when comparing the drives of Si devices to those of SiC devices, there are two important differences to consider: Slew rate at the output of a SiC half bridge can be much higher than with silicon – easily 35kV/μS. This affects the design of the gate drive signal isolation and EMI mitigation. It creates potential issues with the method of implementation of parts of the system, such as the gate power dc-dc function. The intention of this board is to provide an off-the-shelf test solution which addresses these issues. Compared to silicon mosfets, SiC mosfets are normally driven at wider gate voltages – typically from -5 to 20V. Lower positive voltages can be used if the resulting higher Ron is acceptable. Lower negative drive voltages can be used, possibly down to zero. The reference design is intended for markets including: aerospace (actuation, air conditioning and power distribution), automotive (power-trains, battery chargers, dc-dc converters and energy recovery), defence (power supply and high power motor drive), industrial (photovoltaic inverters, motor drives, welding, un-interruptible power supply, switched-mode power supply and induction heating) and medical (MRI and x-ray power supply). Analog Devices’ iCoupler technology, used here, has better than 50ns propagation delay with 5ns matching, and common-mode transient immunity of better than 100kV/us. Lifetime working voltages are available up to 1.5kV in a single package. Ref: KY32-TC4429CAT KY32-IXDD414CI KY32-TPS2819QDBVRQ1
kynix On 2017-06-07
Texas Instruments (TI) (NASDAQ:TXN) today introduced two new device families that help reduce size and weight in motor drive applications. When used together, DRV832x brushless DC (BLDC) gate drivers and CSD88584/99 NexFET™ Power Blocks require as little as 511 mm2, half the board space of competing solutions.The DRV832x BLDC gate drivers feature a smart gate-drive architecture that eliminates up to 24 components traditionally used to set the gate drive current while enabling designers to easily adjust field-effect transistor (FET) switching to optimize power loss and electromagnetic compliance. The CSD88584Q5DC and CSD88599Q5DC power blocks leverage two FETs in a unique stacked-die configuration, which doubles power density and minimizes the FET resistance and parasitic inductances typically found in side-by-side FET configurations.An 18-volt compact BLDC motor reference design demonstrates how the DRV8323 gate driver and CSD88584Q5DC power block can drive 11 W/cm3 power and enable engineers to jump-start their designs for smaller, lighter-weight power tools, integrated motor modules, drones and more. Benefits of using a CSD88584/99 and DRV832x device togetherMaximum power density: The combined solution delivers 700 W of motor power without a heat sink, providing 50 percent higher current than conventional solutions without increasing the footprint.High peak current: As demonstrated by the 18-volt BLDC reference design, the smart gate driver and power block are capable of driving a peak current of up to 160 A for more than 1 second.Optimal system protection: The combination enables shorter trace lengths and actively prevents unintended FET turn-on, while also providing undervoltage, overcurrent and thermal protection.Superior thermal performance: The CSD88584Q5DC and CSD88599Q5DC power blocks come in TI's DualCool™ thermally enhanced package, which enables designers to apply a heat sink to the top of the device to decrease thermal impedance and increase the amount of power dissipated to maintain safe operating temperatures for the board and end application.Clean switching: The power blocks' switch-node clip helps eliminate parasitic inductance between high- and low-side FETs. Additionally, the DRV832x gate driver's passive component integration minimizes board traces.Tools and support to jump-start designIn addition to the 18-volt BLDC motor reference design, engineers can search for other motor reference designs that use the power blocks and gate drivers to help solve their system design challenges. The three-phase smart gate-driver evaluation module (EVM) allows designers to drive a 15-A, three-phase BLDC motor using the DRV8323R gate driver, CSD88599Q5DC power block and MSP430F5529microcontroller LaunchPad™ development kit. The EVM is available from the TI store for US$99.00.Package, availability and pricingThe new DRV832x BLDC smart gate drivers offer peripheral and interface options for engineers to select the best device for their design: with or without an integrated buck regulator or three integrated current-shunt amplifiers. Each device option is available in a hardware or serial interface and comes in quad flat no-lead (QFN) packaging. The CSD88584/99 power blocks come in DualCool small outline no-lead (SON) packaging, with 40- or 60-V breakdown voltage (BVDSS) choices. Ref:KY32-MSP430F5529IPNKY362-DRV8301-69M-KITKY32-DRV8301DCAR
kynix On 2017-05-31
A MOSFET is a four-terminal device having source(S), gate (G), drain (D), and body (B) terminals. In general, the body of the MOSFET is in connection with the source terminal thus forming a three-terminal device such as a field-effect transistor. MOSFET is generally considered as a transistor and employed in both analog and digital circuits. This is the basic introduction to MOSFET. Let’s step into the world of MOSFET and find out its secret. Catalog I. What is MOSFET? 1.1 Brief Introduction 1.2 MOSFET Structure 1.3 Electrical Symbol and Types 1.4 MOSFET Operating Principle II. MOSFET Selection III. MOSFET Gate Material IV. MOSFET Advantage V. MOSFET Technology VI. Common MOSFET Failures VII. MOSFET Well-known Brands FAQ I. What is MOSFET? 1.1 Brief Introduction MOSFET(metal-oxide-semiconductor field-effect transistor) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This video will cover the basics of what you need to use it in your circuit, including calculating if you need a heat sink or not. MOSFET (metal-oxide semiconductor field-effect transistor) is a kind of field effect transistors (FET), that is, the gate of metal layer (M) is separated by oxide layer (O) to control the semiconductors (S) by the field effect transistor. 1.2 MOSFET Structure Fig. 1 mosfet body structure Fig. 1 is a cross-sectional view of a typical N-channel enhanced NMOSFET diagram. a P-type silicon semiconductor material is used as a substrate, two N-type regions are diffused on the surface of the substrate, a layer of silicon dioxide (SiO2) insulating layer is covered on the substrate, and finally, two holes are formed by using an etching method over the N region. The metallization method is used to make three electrodes: G (gate), S (source), and D (drain) in the insulating layer and the two holes, respectively. From Fig. 1, we can see that the gate G is insulated from drain D and source S, and there are two PN junctions between D and S. In general, the substrate and the source S are connected internally, in other words, there is a PN junction between D and S. Fig. 1 is a basic block diagram of a common n-channel enhancement MOSFET. To improve the performance of some parameters, such as improving the working current, increasing the working voltage, reducing the on-resistance, improving the switching characteristic, and so on. With different structures and processes, there are VMOS, DMOS, TMOS, etc. Although their structures are different, the working principle is the same. 1.3 Electrical Symbol and Types Fig. 2 mosfet symbols There are many variations in circuit symbols commonly used in MOSFET. The most common design is to represent the channel in a straight line, two lines perpendicular to the channel to represent the source and drain, and the left and the channel parallel and shorter lines to represent the grid. Sometimes a straight line representing the channel is replaced by a broken line to distinguish between an enhancement mode MOSFET or a depletion mode MOSFET and each mode divided into two types respectively, NMOSFET and PMOSFET. Fig. 3 NMOSFET and PMOSFET Depletion Mode: the Gate-Source voltage of a transistor switches the device “OFF”. The depletion-mode MOSFET is equivalent to a “Normally Closed” switch. Fig. 4 structure and electrical symbol (depletion mode mosfet) Enhancement Mode: the Gate-Source voltage of a transistor switches the device “ON”. The enhancement-mode MOSFET is equivalent to a “Normally Open” switch. Fig. 5 enhancement type MOSFET(channel structure) Since the MOSFET on the integrated circuit chip is a four-terminal component, there is a bulk or body except for the gate, source and drain. The arrow extending from the channel to the right can indicate that the component is an NMOSFET or PMOSFET. In addition, the arrow direction is always pointed from the P end to the N end, so the arrow points from the channel to the base is the P-type MOSFET, abbreviated PMOS. On the contrary, if the arrow points from the base to the channel, the base is P-type, and the channel is N-type, which is the N-type MOSFET. In a typical discrete device, that base and source are typically connected together so that the distributed MOSFET is typically a three-terminal element. Whereas a MOSFET in an integrated circuit, the polarity of the base is not indicated because of the use of the same base, and a circle is added to the gate terminal of the PMOS to distinguish. P-Channel MOSFET: It has a P-Channel region between source and drain. It is a four-terminal device such as gate, drain, source, body. The drain and source are heavily doped p+ region and the body or substrate is n-type. The flow of current is positively charged holes. When we apply the negative gate voltage, the electrons present under the oxide layer are pushed downward into the substrate with a repulsive force. The depletion region populated by the bound positive charges which are associated with the donor atoms. The negative gate voltage also attracts holes from the p+ source and drain region into the channel region. N- Channel MOSFET: It has an N-channel region between source and drain. It is a four-terminal device such as gate, drain, source, body. In this type of MOSFET, the drain and source are heavily doped n+ region and the substrate or body is P-type. The current flows due to the negatively charged electrons. When we apply the positive gate voltage the holes present under the oxide layer pushed downward into the substrate with a repulsive force. The depletion region is populated by the bound negative charges which are associated with the acceptor atoms. The electron's reach channel is formed. The positive voltage also attracts electrons from the n+ source and drains regions into the channel. Now, if a voltage is applied between the drain and source the current flows freely between the source and drain and the gate voltage controls the electrons in the channel. Instead of positive voltage if we apply negative voltage a hole channel will be formed under the oxide layer. Therefore, the MOSFET has 4 modes: P-channel enhancement mode, P-channel depletion mode, N-channel enhancement mode, N-channel depletion mode. Their circuit symbols and application characteristic curves are shown in the following figure. Fig. 6 circuit symbols and application characteristic curves of MOSFET 1.4 MOSFET Operating Principle The internal structure and electrical symbols of power MOSFET can be divided into NPN type and PNP type. That is, the source and drain poles of the N-channel FET are connected to the N-type semiconductor, and the source and drain of the P-channel FET are connected to the P-type semiconductor. We know that the output current of the general transistor is controlled by the input current. But for field-effect transistors, the output current is controlled by the input voltage (or field voltage), which can be considered to be minimal or no input current, causing the device to have a high input impedance, and it is the reason why we call it a FET. The working principle of power MOSFET is as follows: adding positive power supply between drain and source, and no voltage between gate and sources. The PN junction J1 formed between drain and source is anti-biased, and there is no current flow between drain-source. Conductive: adding the positive voltage UGS, the gate is insulated between the gate and source, so there will be no gate current flowing through. However, the positive voltage of the gate pushes the hole in the P region below it and attracts the minority electron in the P region to the surface of the P region below the gate when the UGS is greater than the UT (on voltage or threshold voltage). The electron concentration on the surface of the P region under the gate will exceed the hole concentration, making the P-type semiconductor invert into the N-type. For the inversion layer, the N-channel is formed and the PN junction J1 is disappeared, and meanwhile, the drain electrode and the source electrode are conductive. Basic static characteristics of power MOSFET: Its transfer and output characteristics are shown in Fig. 7. Fig. 7 transfer and output characteristics of mosfet The relationship between drain current ID and voltage UGS between gate and source is called the transfer characteristic of MOSFET. When ID is large, the relationship between ID and UGS is approximately linear, and the slope of the curve is defined as grid-anode transconductance Gfs. The voltage-current characteristic (output characteristics) of drain include the cut-off region (corresponding to the cut-off region of GTR), the saturated region (corresponding to the magnification region of GTR), and the unsaturated region (corresponding to the saturation region of GTR). The MOSFET operates in the on-off state, that is, switching back and forth between the cut-off zone and the unsaturated zone. There are parasitic diodes between the drain and source, and the devices are on when a reverse voltage is added between the drain and source. The on-state resistance of the power MOSFET has a positive temperature coefficient, which is beneficial to the current sharing of the devices in parallel. 1. Cut-off Region: with the transistor acting as an open switch, the gate-source voltage is much lower than the transistor's threshold voltage so the MOSFET transistor is switched off fully. 2. Linear (Ohmic) Region: the transistor is in its constant resistance region behaving as a voltage-controlled resistance whose resistive value is determined by the gate voltage. 3. Saturation Region: the transistor is in its constant current region and is therefore switched on fully. The Drain current is equal to the maximum with the transistor acting as a closed switch. Dynamic Properties On-delay time (Td): it is the time experienced when the gate-source voltage rises to 10% of the gate drive voltage to the specified current rises to 10%. Rise time (Tr): it is the time taken to increase the drain current from 10% to 90%. The ID steady-state value is determined by the drain-source voltage UE and the drain load resistance. The UGSP is related to the steady-state value of the ID, and when the UGS reaches the UGSP, it continued to increase until it reached the steady-state, but the ID did not change. Turn-on time: the sum of turn-on delay time and rise time. Turn-off delay time (Td): it refers to the time from when the voltage between gate and source drops to 90% of the gate drive voltage to the leakage current of 90% of the specified current. This shows the delay before the current is transferred to the load. Drop time: it is the time experienced by the drain current drops from 90% to 10%. Turn-off time: the sum of the turn-off delay time and drop time. Understand several commonly used parameters of MOSFET. VDS is the drain-source voltage, which is an absolute parameter rating of MOSFET, which indicates the maximum voltage value that MOSFET can bear between drain and source. It is important to note that this parameter is related to junction temperature, and the higher the junction temperature is, the greater the value is. RDS (on), refers to the leakage source on-resistance, which represents the on-resistance between drain and source when MOSFET is on under certain conditions. This parameter is related to MOSFET junction temperature and driving voltage Vgs. In a certain range, the higher the junction temperature, the greater the Rds, the higher the driving voltage, the smaller the Rds. Qg is the gate charge, gate charge is the charge required to increase the gate voltage from 0V to the termination voltage (such as 15V) under the action of the driving signal. That is the charge required by the driving circuit from the cut-off state to the full-on state, which is the main parameter used to evaluate the driving ability of the driving circuit of the MOSFET. Id (drain current), is usually described in several different ways. According to the form of the working current, it divided into the continuous drain current and the pulse drain current. In addition, it is also an absolute parameter rating of MOSFET, but this maximum current value does not mean that the drain current can reach this value during operation. It means that when the shell temperature is at a certain point if the operating current of MOSFET is the maximum drain current mentioned above, the junction temperature will reach the maximum value. Thus this parameter is also related to device packaging and ambient temperature. Eoss (output volume energy), representing the output capacitance Coss stored in the MOSFET. Because the output capacitance Coss of MOSFET has very obvious nonlinear characteristics, it varies with the change of Vds voltage. If the datasheet identifies this parameter, it will be helpful to evaluate the switching loss of the MOSFET. The current rate of the body diode di/dt reflects the MOSFET reverse recovery characteristics. Because the diode is a bipolar device, it is affected by the charge storage, when the diode reverses bias, the charge stored in the PN junction must be removed, which is precisely the reaction of the above-mentioned parameters characteristic. The maximum gate-source driving voltage Vgs, which is also an absolute parameter rating of the MOSFET, represents the maximum driving voltage that the MOSFET can withstand. Once the driving voltage exceeds this limit, permanent damage to the gate oxide can occur even in a very short period of time. Generally speaking, as long as the driving voltage does not exceed the limit, there will be no problem. However, due to the existence of parasitic parameters in some special cases, the Vgs will be affected unpredictably, which needs to be paid more attention to. SOA (safe work area), each MOSFET will give its safe working area. For example, different bipolar transistors, power MOSFET does not show a second breakdown, so the safe operation area is simply defined from the dissipative power that causes the junction temperature to reach the maximum allowable value. II. MOSFET Selection After understanding the principle of MOSFET selection, You can select the correct MOSFET with the following four steps. 1) channel selection The first step in choosing the right device for design is to decide whether to use N-channel or P-channel MOSFET. In typical power applications, when a MOSFET is grounded and the load is connected to the trunk voltage, the MOSFET forms a low-voltage side switch. N-channel MOSFET should be used in the low-voltage side switch, which is due to the voltage required by switching on or switching off the device. When the MOSFET is connected to the bus and the load is grounded, the high-voltage side switch is used. P-channel MOSFET is usually used in this case, which is also due to the consideration of driving voltage. 2) selection of voltage and current The higher the rated voltage, the higher the cost of the device. According to practical experience, the rated voltage should be greater than trunk voltage or bus voltage. This will provide sufficient protection so that the MOSFET can work well. As far as MOSFET is concerned, it is necessary to determine the maximum possible voltage between the drain and the source. Other safety factors that design engineers need to consider include voltage transients induced by switchgear, such as motors or transformers. And rated voltages vary from application to application, typically, portable devices are 20V, FPGA power supplies are 20V~30V, and so on. In the continuous conduction state, the MOSFET is stable and the current passes through the device continuously. A pulse spike refers to a large number of surge current (or peak current) flowing through the device. Once the maximum current is determined under these conditions, simply select the device that can withstand the maximum current. 3) calculating on-loss The power loss of MOSFET devices can be calculated by Iload2×RDS (on). Because the on-resistance varies with temperature, the power loss also varies proportionally. For portable designs, lower voltages are more common, and for industrial designs, higher voltages can be used. Note that the RDS (on) resistance increases slightly with the current. Variations in the electrical parameters of the RDS (on) resistance can be found in the technical datasheet provided by the manufacturer. 4) heat dissipation requirements for a computing system The designer must consider two different situations, the worst case, and the real situation. It is recommended that the worst-case results be used because the results provide a greater security margin to ensure that the system does not fail. There are also some measurements on the MOSFET table that need to be noticed, such as the thermal resistance between the semiconductor junction and the environment of the packaged device, and the maximum junction temperature. Switching loss is also a very important indicator. The voltage-current product of the on-off moment is quite large, which determines the switching performance of the device to a certain extent. However, if the system requires high switching performance, you can choose a power MOSFET with a lower gate charge. III. MOSFET Gate Material Theoretically, the gate of MOSFET should be chosen as well as possible, and the conductivity of polysilicon doped by heavy can be used on the gate of MOSFET. The reasons for using polysilicon in MOSFETs are as follows: 1) The threshold voltage of the MOSFET is mainly determined by the difference between the work function of the gate and the channel material, and because the polysilicon is essentially a semiconductor, it is possible to change its work function by doping impurities of different polarities. More importantly, since the gap between the polysilicon and the silicon as the channel is the same, it is possible to achieve the demand by directly adjusting the work function of the polysilicon when the threshold voltage of the PMOS or NMOS is reduced. Conversely, the work function of the metallic material is not like the semiconductor is then easily changed so that it becomes difficult to reduce the critical voltage of the MOSFET. And if the threshold voltage of the PMOS and the NMOS is to be reduced at the same time, two different metals are required to do their gate material, respectively, and a large variable for the producing process. 2) After years of research on the silicon-silica interface, it has been proved that the defect between the two materials is relatively small. On the contrary, there are many defects in the metal-insulator interface, so it is easy to form a lot of surface energy levels between the two, which greatly affects the characteristics of the elements. 3) The melting point of the polycrystalline silicon is higher than most of the metal, while in the modern semiconductor process, the gate material is used to deposit the gate material at high temperatures to improve the efficiency of the element. The low melting point of the metal will affect the upper-temperature limit that can be used by the process. However, although polysilicon has been the standard material for the manufacture of MOSFET gates, there are also a number of shortcomings of it, which makes it possible for some MOSFET to use metal gates in the future. These shortcomings are as follows: (1) Polysilicon is less conductive than metal, limiting the speed of signal transmission. Although doping can be used to improve its conductivity, the effectiveness is still limited. Some metal materials with a high melting point, such as tungsten, titanium, cobalt, or nickel, are used to make alloys with polysilicon. This type of mixture is commonly referred to as metal silicide. The polysilicon gate with metal silicide has good electrical conductivity and can withstand a high-temperature process. In addition, because the position of the metal silicide is on the surface of the grid, therefore, the critical voltage of MOSFET will not be affected much. The process of plating a metal silicide on the gate, source, and drain is referred to as self-aligned metal, commonly referred to as salicide process. (2) When the size of the MOSFET is small and the gate oxide layer also becomes very thin, for example, the new process can reduce the oxide layer to a thickness of about one nanometer, and a phenomenon is also generated unprecedentedly, and that is "polysilicon depletion". When the inversion layer of the MOSFET is formed, the MOSFET gate polysilicon depletion phenomenon is occurring close to the oxide layer, and a depletion layer is present to influence the conduction characteristics of the MOSFET. To address this problem, one way is the metal gate. Reasonable materials include tantalum, tungsten, tantalum nitride, or titanlium nitride. The gates made by these metals usually form MOS capacitors along with oxide formed by high permittivity substances. Another solution is the polysilicon alloying, also called FUSI (FUlly-SIlicide polysilicon gate). IV. MOSFET Advantage MOSFET was first made successfully in 1960 by D. Kahng and Martin Atalla in Bell Labs, and the operating principle of this element was very different from that of the bipolar junction transistor (BJT) invented by William Shockley in 1947. And because of the low cost and small size, it plays a very important role in large-scale integrated circuits (LSI) and very large-scale integrated circuits (VLSI) than BJT. 1) Field-effect transistor (FET) is a voltage control element, and bipolar junction transistor (BJT) is a current control element. The FET should be selected when only less current is allowed, and the BJT should be chosen when the signal voltage is low and more current is allowed to flow through from the source of the signal. 2) The source and drain poles of some FET can be used interchangeably, the gate voltage can also be positive and negative, and the flexibility is better than the bipolar transistor. 3) FET is called a monopole device because it makes use of majority carriers to conduct electricity, while BJT is conducting by majority carrier or minority carrier, therefore, it is called bipolar device. 4) FET can work under the conditions of very low current and low voltage, and its manufacturing process can easily integrate many FETs on a silicon wafer. Therefore, FET has been widely used in large-scale integrated circuits (LSI). With the improvement of the performance of MOSFET components, except the traditional applications in digital signal processing such as microprocessors and microcontrollers, more and more integrated circuits for analog signal processing can be implemented by MOSFET. V. MOSFET Technology 1) Dual-gate MOSFET Dual-gate MOSFET is usually used in radio frequency (RF) integrated circuits. The two gates of the MOSFET can control the current. In RF circuits, the second gate of the dual-gate MOSFET is mostly used for gain, mixer, or frequency conversion control. 2) Depletion Type MOSFET In general, a depletion-mode MOSFET is less common than the enhancement mode MOSFET. The depletion-mode MOSFET changes the impurity concentration of the channel in the doping process so that the channel still exists even if the gate of the MOSFET is not applied voltage. If you want to close the channel, you must apply a negative voltage to the gate. Thus the most application of the depleted MOSFETs is in the "normally-off" switch, while the enhancement-mode MOSFET is usually used in the " normally-on" switch. 3) NMOS Logic The NMOS of the same driving capability is generally smaller than the area occupied by the PMOS, and therefore, if an NMOS is used only on the design of the logic gate, the chip area itself can be reduced. However, although the area of the NMOS logic is small, the static power will be consumed unlike the CMOS logic, so it has gradually exited the market after the mid-1980s. 4) Power MOSFET There is a significant structural difference between the power MOSFET and the above-mentioned MOSFET elements. In general, MOSFET in integrated circuits are planar structures, and the endpoints of transistors are only a few microns away from the surface of the chip. But all the power components are vertical structures, which allows the components to withstand both high voltage and high current working environments. A power MOSFET withstand voltage is a function of the doping concentration and the thickness of the N-type epitaxial layer, and the width of the channel is related to how much the current can pass through, that is, the wider channel can accommodate more current. For a planar MOSFET, the current and the breakdown voltage are dependent on the length and width of the channel. For a vertical MOSFET, the area of the element is approximately proportional to the current it can hold, and the thickness of the epitaxial layer is proportional to its breakdown voltage. Working principle Due to the positive power supply between the source and the drain, the voltage between them is zero. The PN junction J1 formed between the P base region and the N drift region is anti-biased, and no current flows between the source and the drain. Conduction: the positive voltage UGS, the gate is insulated between the gate and the source, so there will be no gate current flowing through. However, when the positive voltage of the gate pushes the hole in the P region below it and attracts the minority electron in the P region to the surface of the P region below the gate and the UGS is greater than the UT (on voltage or threshold voltage), the electron concentration on the surface of the P region under the gate will exceed the hole concentration, which causes the P-type semiconductor inversion to become N-type and becomes the inversion layer. The inversion layer forms N-channel and makes the PN junction J1 disappear, and the drain and the source turn to conductive. It is worth mentioning that power MOSFET with planar structure is not non-existent, and this kind of element is mainly used in advanced sound amplifiers. The characteristics of planar power MOSFET in the saturation region are better than that of vertical structure MOSFET. Vertical power MOSFET takes the advantage of very small turn-on resistance and is mostly used for switches. 5) DMOS DMOS is an abbreviation for a double-diffused MOSFET, which is mainly used for high voltage and belongs to the category of high-voltage MOSFET. The MOSFET is used to realize the analog switch. The channel resistance of the MOSFET is low when the MOSFET is turned on, and the resistance is almost infinite when the MOSFET is turned off so that the switch which is suitable as a switch of the analog signal (the energy of the signal is not lost due to the resistance of the switch). When the MOSFET is a switch, its source and drain are different from each other, respectively, because the signal can be accessed from any end of the MOSFET. For an NMOS switch, the negative voltage is in the source, it opposite to the PMOS, the positive voltage is in the source. The signal that the MOSFET switch can transmit is subject to its voltage between gate and source, gate and drain, drain and source. If the upper limit of the voltage is exceeded, the MOSFET may burn out. MOSFET switches have a wide range of applications, such as the need for sampling holding circuit (sample-and-hold circuits) or truncated circuit (chopper circuits) design, For example, MOSFET switch can be seen on the analog-digital converter (A / D converter) or switched capacitor filter (switch-capacitor filter). 6) Single MOSFET Switch When the NMOS is used as a switch, the base is grounded and the gate is the controlling end of the switch. The state of the switch is on when the gate voltage subtracts the source voltage exceeding the critical voltage. If the gate voltage continues to rise, the current through which the NMOS can pass more. NMOs operate in the linear region when the switch is turned on because the voltage of the source and drain tends to be consistent when the switch is on. When the PMOS is used as a switch, its base is connected to the highest potential in the circuit, usually a power supply. The voltage of the gate is very low than the source. And when the gate exceeds the critical voltage, the PMOS switch will be turned on. And a single MOSFET switch may reduce the amplitude of the signal and distort the signal. 7) Double MOSFET (CMOS) Switch In order to improve the signal distortion caused by the single MOSFET switch mentioned above, the use of a PMOS plus and an NMOS of CMOS switch has become the most common practice at present. The PMOS switch connects the source and drain of the NMOS separately. The basic joining rule is the same as the traditional connecting method of NMOS and PMOS. When the input voltage is at (VDD-Vthn) and (VSS+Vthp), the PMOS and NMOS are on, but when the input is less than (VSS+Vthp), only NMOS is on and the input is greater than (VDD-Vthn), and only the PMOS turns on. The advantage of this is that under most of the input voltage, both the PMOS and the NMOS are turned on at the same time, and if the on-resistance of either side is increased, the on-resistance on the other side is reduced, so that the resistance of the switch can be kept almost constant, thus the signal distortion is reduced. Fig. 8 switching process of power MOSFET VI. Common MOSFET Failures Overvoltage damage, including gate overvoltage and drain overvoltage, often accompanied by overcurrent. If protection happened in a very short period of time, it may be overvoltage damage. If there is no overvoltage protection and the state turns into overcurrent damage, the chip in the source non-line region will burn out. A large current, such as severe over-current short-circuit damage, will cause a large amount of heat to burn out the chip. Overheat damage, if the MOS tube isn’t appearing overcurrent and overvoltage, just because the junction temperature is too high, if the chip is protected, the surface will not see obvious burns, if not, there will be a large amount of burning area. In general, the mechanism of MOS tube damage is usually thermal damage, local overheating, or overall heating, such as overvoltage, is a crystal package that can’t stand high voltage breakdown causing heating damage. The fault analysis of the MOS tube should be based on the combination of specific circuit and burning phenomenon to be more accurate. Fig. 9 basic structure of an n-channel mosfet VII. MOSFET's Well-Known Brands MOSFETs are mainly divided into several series: American, Japanese, Korean, Taiwan, and so on. The brand's representatives of each system are as follows: American: IR ST TI PI Fairchild Infineon ON Semiconductor Japanese: TOSHIBA RENESAS SHINDENGEN Taiwan: APEC CET Korean: KEC AUK MagnaChip KIA Truesemi Wisdom FAQ 1. What is Mosfet and how it works? In general, the MOSFET works as a switch, the MOSFET controls the voltage and current flow between the source and drain. The working of the MOSFET depends on the MOS capacitor, which is the semiconductor surface below the oxide layers between the source and drain terminal. 2. What is Mosfet and its characteristics? MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form an integral part of vast variety of electronic circuits. ... In this region, MOSFET behaves like an open switch and is thus used when they are required to function as electronic switches. 3. How many types of Mosfet are there? Four types. There are two classes of MOSFETs. There is depletion mode and there is enhancement mode. Each class is available as n- or a p-channel, giving a total of four types of MOSFETs. 4. What is an ideal Mosfet? In an ideal MOSFET, setting the gate-source voltage to a value VGS < VTn places the transistor into cutoff with ID = O. Increasing the gate-source voltage to a value VGS > VTn allows the transistor to conduct current ID; this defines the active mode of operation. 5. How do I know if my MosFet is bad? A good MOSFET should have a reading of 0.4V to 0.9V (depends on the MOSFET type). If the reading is zero, the MOSFET is defective and when the reading is “open” or no reading, the MOSFET is also defective. When you reverse the DMM probe connections, the reading should be “open” or no reading for a good MOSFET. 6. What is a Mosfet used for? What is a MOSFET and How does it work? MOSFET, in short, is a metal oxide semiconductor field-effect transistor used to switch or amplify voltages in circuits. Being part of the field-effect transistor family, it is a current-controlled device that is constructed with 3 terminals. 7. Is Mosfet still used? The MOSFET is by far the most widely used transistor in both digital circuits and analog circuits, and it is the backbone of modern electronics. It is the basis for numerous modern technologies, and is commonly used for a wide range of applications. 8. Why is it called Mosfet? The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel. 9. What causes a Mosfet to fail? If the maximum operating voltage of a MOSFET is exceeded, it goes into Avalanche breakdown. ... If the energy contained in the transient over-voltage is above the rated Avalanche energy level, then the MOSFET will fail. The device fails short circuit, initially, with no externally visible signs. 10. Why N channel is better than P channel Mosfet? N-Channel MOSFETs are more efficient than P-Channel MOSFETs.It comes down to physics. N-Channel MOSFETs use electron flow as the charge carrier. P-Channel MOSFETs use hole flow as the charge carrier, which has less mobility than electron flow. And therefore, they have higher resistance and are less efficient. You May Also Like Selection of Drive Resistor: MOSFET | Gate Drive Reference Component KY56-SQ7415AEN-T1_GE3 KY56-STP160N3LL
kynix On 2017-05-10
One of the greatest challenges in the evolution of electronics has been to reduce power consumption during transistor switching operation. In a study recently reported in Nature, engineers at University of California, Santa Barbara, in collaboration with Rice University, have demonstrated a new transistor that switches at only 0.1 volts and reduces power dissipation by over 90% compared to state-of-the-art silicon transistors (MOSFETs). MOSFETs have been the building blocks of everyday electronic products since the 1970s. However, to sustain the ever-growing need for increased transistor densities, miniaturization of MOSFETs has given rise to a power dissipation challenge due to the fundamental limitations of their turn-on characteristics. "The steepness of a transistor's turn-on is characterized by a parameter known as the subthreshold swing, which cannot be lowered below a certain level in MOSFETs," explained Kaustav Banerjee, Professor of Electrical and Computer Engineering at UC Santa Barbara. A minimum gate voltage change of 60 millivolts at room temperature is required to change the current by a factor of ten in MOSFETs. In essence, the existing state of transistor technology limits the energy efficiency potential of digital circuits in general. The research group of Professor Kaustav Banerjee at UC Santa Barbara took a new approach to subverting this fundamental limitation. They employed the quantum mechanical phenomenon of band-to-band tunneling to design a tunnel field effect transistor (TFET) with sub-60mV per decade of subthreshold swing. "We restructured the transistor's source to channel junction to filter out high energy electrons that can diffuse over the source/channel barrier even in the off state, thereby making the off state current negligibly small," explained Banerjee. At UCSB, Banerjee's Nanoelectronics Research Lab includes Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, and Stephan Kraemer, as well as Yongji Gong and Pulickel Ajayan of Rice University. Banerjee and his colleagues are motivated by a global electronics industry that loses billions of dollars each year to the impact of power dissipation on chip cost and reliability. "This translates into lower battery lifetime in personal devices like cell phones and laptops, and massive power consumption of servers in large data centers," adds Banerjee, pointing out the global scale of this energy demand. An industry that relies on conventional semiconductors such as silicon or III-V compound semiconductors as the channel material for TFETs, Banerjee explains, "faces limitations because these materials have high density of surface states, which increase leakage current and degrade the subthreshold swing." The TFET designed by the UCSB team overcame this challenge in a few ways, most significant being the use of a layered two-dimensional (2D) material called molybdenum disulphide (MoS¬2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3nm. The resulting vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS¬2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area. "The crux of our idea is to combine 3D and 2D materials in a unique heterostructure, to achieve the best of both worlds. The matured doping technology of 3D structures is married to the ultra-thin nature and pristine interfaces of 2D layers to obtain an efficient quantum-mechanical tunneling barrier, which can be easily tuned by the gate," commented Deblina Sarkar, lead author of the paper and PhD student in Banerjee's lab. "We have engineered what is, at present, the thinnest-channel subthermionic transistor ever made," said Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve subthermionic subthreshold swing (~30 millivolts/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1V. Ajayan, co-author and professor of chemical and biomolecular engineering at Rice University, commented, "This is a remarkable example showing the uniqueness of 2D atomic layered materials that enables device performance which conventional materials will not be able to achieve. This is perhaps the first breakthrough in a series of novel devices that people will now aspire to build using 2D materials." "The work is a significant step forward in the search for a low voltage logic transistor. The demonstration of sub-thermal operation over four orders of magnitude is impressive, and the on-current also advances the state-of-the-art. There is still a long ways to go, but this work demonstrates the potential of 2D materials to realize the long-sought, low-voltage device," commented Mark Lundstrom, professor of electrical and computer engineering at Purdue University. "We have demonstrated how to achieve the most important metric of steep subthreshold swing that meets ITRS requirements. Our transistor can be utilized for a number of low-power applications including arenas where the steep subthreshold swing is the main requirement, such as biosensors or gas sensors. With improved performance, the range of applications of this transistor can be further expanded," explained Wei Cao, a PhD student in Banerjee's group and a co-author of the article. "This work represents an important step of bringing 2D materials closer to real applications in electronics. The use of 2D materials in tunneling transistors started only recently, and this paper gives the whole field yet another strong boost in improving the characteristics of such devices even further," commented Dr. Konstantin Novoselov, a professor of physics at University of Manchester. Novoselov was co-recipient of the 2010 Nobel Prize in Physics, awarded for the discovery of graphene. "When I first heard Banerjee's idea of using 2D materials for designing inter-band tunneling transistors in 2012, I recognized its merit and immense potential for ultra-low power electronics. I am pleased to see that his vision has been realized," commented James Hwang, professor of electrical engineering at Lehigh University, who was then the AFOSR program manager responsible for funding this research.
kynix On 2016-09-29
Catalog Overview Structure and Working Principle of Power MOSFET Structure of Power MOSFET WorkingPrinciple of Power MOSFET Basic Characteristics of Power MOSFET Static Properties Dynamic Characteristics Switching Speed of MOSFET Improvement of Dynamic Performance Principle and Performance Analysis of High Voltage MOSFET Principle and Method of Reducing on Resistance of High Voltage MOSFET On-Resistance Distribution of MOSFET with Different Voltage Resistance The Idea of Reducing the On-Resistance of High Voltage MOSFET Main Characteristics of Built-In Transverse Electric Field MOSFET The Decrease of On-Resistance The Reduction of Package and the Reduction of Thermal Resistance Improvement of Switching Characteristics Anti-Avalanche Breakdown Ability and SCSOA Development Status of Built-in Transverse Electric Field High Voltage MOSFET Comparison Between COOLMOS and IGBT Power MOSFET Drive Circuit Introduction and Analysis of Several MOSFET Drive Circuits An Unisolated Complementary Drive Circuit Isolated Drive Circuit 1. Overview The original meaning of MOSFET is Metal-Oxide-Semiconductor Field-Effect-Transistor. MOS means that the gate of the metal layer (M) is separated by the oxide layer (O) to control the field effect transistor of the semiconductor (S) by the effect of electric field. Power field effect transistors are divided into junction type and insulated gate type, but it usually refers to the MOS type(Metal Oxide Semiconductor FET) in the insulation grid type, which is referred to as power MOSFET. Junction power field effect transistors are generally referred to as Static Induction Transistor (SIT). It is characterized in that the gate voltage is used to control the drain current, the drive circuit is simple, the drive power is small, the switching speed is fast, the working frequency is high, and the thermal stability is better than that of GTR. However, its current capacity is small and it can just withstand low voltage. Generally speaking, it is only suitable for power electronic devices whose power does not exceed 10kW. 2. Structure and working principle of Power MOSFET Types of Power MOSFET: According to the conductive channel, it can be divided into P channel and N channel. According to the amplitude of gate voltage, it can be divided into: depletion type and enhancement type. Power MOSFET is mainly N-channel enhancement type. 2.1 Structure of Power MOSFET The internal structure and electrical symbols of the power MOSFET are shown in figure 1. When a monopole transistor is turned on, only one polar carrier (multiple carriers) is involved in the conduction. The conductive mechanism is the same as that of the low power MOSFET, but the structure is quite different. The low power MOSFET is a transverse conductive device. The power MOSFET mostly adopts the vertical conductive structure, also known as VMOSFET (Vertical MOSFET), which greatly improves the voltage and current resistance of MOSFET devices. Fig 1. According to the difference of vertical conductive structure, it can be divided into two types. One is VVMOSFET, which use V-shaped slot to achieve vertical conduction. Another is VDMOSFET (Vertical Double-diffused MOSFET), which has vertical conductive double diffusion MOS structure. In this article, VDMOS devices are discussed as an example. The power MOSFET is a multivariate integrated structure, such as the hexagonal unit adopted by the HEXFET of International Rectifier, the square unit adopted by the SIPMOSFET of Siemens and rectangular unit adopted by TMOS of Motorola. 2.2 Working principle of Power MOSFET Cut-off: Positive power supply is added between drain and source, and the voltage between gate and source is zero. The J1 of the PN junction formed between the P base region P and the drift region N is inversely biased, and there is no current flow between the drain and source. Conduction: By adding a positive voltage UGS between the gate sources, the gate is insulated, so no gate current flows through it. However, the positive voltage of the gate pushes away the holes in the region P below it, and attracts the electrons, minority carrier in the region P to the surface of the region P below the gate. When the UGS is greater than the UT (turn-on voltage or threshold voltage), the electron concentration on the surface of the region P under the gate will exceed the hole concentration, making the P-type semiconductor inverse into the N-type and become the inversion layer. The inversion layer forms the N channel and makes the PN junction J1 disappear. The drain and source conduct electricity. 2.3 Basic characteristics of Power MOSFET 2.3.1 Static properties: the transfer and output properties are shown in figure 2. Fig 2. The relationship between drain current ID and gate source voltage UGS is called the transfer characteristic of MOSFET. When the ID is large, the relationship between ID and UGS is approximately linear, and the slope of the curve is defined as transconductance Gfs. The drain volt-ampere characteristics (output characteristics) of MOSFET are as follows: Cutoff region (corresponding to the cutoff region of GTR) Saturation region (corresponding to the magnification region of GTR) Unsaturated region (corresponding to the saturation region of GTR) The power MOSFET works in the switching state, which means that it switches back and forth between the cut-off zone and the unsaturated zone. There is a parasitic diode between the drain and source of power MOSFET, and the device is turned on when the reverse voltage is applied between the drain and source. The on-state resistance of power MOSFET has a positive temperature coefficient, which is beneficial to the current sharing of the devices connected in parallel. 2.3.2 Dynamic characteristics; the test circuit and switching process waveforms are shown in figure 3 Fig 3. 2.3.3 Switching Speed of MOSFET The switching speed of MOSFET has a lot to do with the charge and discharge of Cin. The user can not reduce the Cin, but can reduce the internal resistance of the drive circuit Rs, reduce the time constant and speeds up the switching speed. MOSFET only depends on multiple carriers to conduct electricity, and there is no minority carrier storage effect, so the turn-off process is very fast. The switching time is between 10-100ns, and the working frequency can reach more than 100kHz, which is the highest among the main power electronic devices. When the field control device is static, there is little need for input current. However, during the process of switching, the input capacitor needs to be charged and discharged, and a certain amount of drive power is still needed. The higher the switching frequency, the greater the drive power required. 2.4 Improvement of dynamic performance In the application of the device, in addition to considering the voltage, current and frequency of the device, we must also grasp how to protect the device in the application so as not to damage the device in the transient change. Of course, the thyristor is a combination of two bipolar transistors, coupled with the large capacitance brought by large area, so its dv/dt capability is relatively fragile. For di/dt, it also has a conduction zone extension problem, so it also brings quite strict restrictions. The case of power MOSFET is very different. Its dv/dt and di/dt capabilities are often measured by its ability per nanosecond rather than per microsecond. But in spite of this, it also has the limitation of dynamic performance. These can be understood from the basic structure of power MOSFET. Fig. 4 is the structure of the power MOSFET and its corresponding equivalent circuit. In addition to the fact that almost every part of the device has a capacitance, it must also be considered that the MOSFET is connected in parallel with a diode. At the same time, from a certain point of view, it also has a parasitic transistor, just as IGBT is parasitic on a thyristor. These aspects are very important factors to study the dynamic characteristics of MOSFET. Fig 4. First of all, the intrinsic diode attached to the MOSFET structure has certain avalanche ability. It is usually expressed as the ability of a single avalanche and the ability of repeated avalanche. When the reverse di/dt is very large, the diode will withstand a very fast pulse spike. It may enter the avalanche area, once its avalanche capacity is exceeded, the device may be damaged. As any kind of PN junction diode, it is very complex to study its dynamic characteristics carefully. They are very different from the simple concept that we generally understand that the PN junction is conducted when it is forward and blocked when it is backward. When the current drops rapidly, the diode loses its reverse blocking ability and this is the so-called backward recovery time. When the PN junction requires rapid conduction, there will be a period of time when the resistance is not very low. Once the diode has a positive injection in the power MOSFET, the injected minority carriers will also increase the complexity of the MOSFET as a multi-subdevice. During the design process of power MOSFET, measures are taken to make the parasitic transistors as ineffective as possible. The measures are different in different generation of power MOSFET, but the general principle is to make the transverse resistance RB under the drain as small as possible. Because only when the transverse resistance under the region N of drain flows through enough current to establish the positive deviation condition for the region N, the parasitic bipolar thyristor begins to cause difficulties. However, under severe dynamic conditions, the transverse current caused by dv/dt through the corresponding capacitance may be large enough. At this point, the parasitic bipolar transistor will start, possibly causing damage to the MOSFET. Therefore, when considering the transient performance, attention must be paid to the internal capacitance of the power MOSFET device, which is the channel of the dv/dt. The transient situation is closely related to the line condition, which should be paid enough attention in the application. In order to understand and analyze the corresponding problems, it is necessary to have an in-depth understanding of the device. 3. Principle and Performance Analysis of High Voltage MOSFET In power semiconductor devices, MOSFET plays an important role in all kinds of power conversion, especially in high frequency power conversion with high speed, low switching loss and low drive loss. In the low voltage field, MOSFET has no competitors, but with the increase of the voltage resistance of MOS, the on-resistance increases to the power of 2.4 to 2.6. The growth rate makes MOSFET manufacturers and users have to reduce the rated current by tens of times in order to compromise the contradiction between rated current, on resistance and cost. Even so, the on-voltage drop caused by the on-resistance of the high-voltage MOSFET at the rated junction temperature is still high. The rated junction temperature and current of the MOSFET withstanding voltage above 500V are very high, and the on-voltage above 800V is astonishingly high. The conduction loss accounts for two-thirds to four-fifths of the total loss of MOSFET, which greatly limits the application. 3.1 Principle and Method of Reducing on Resistance of High Voltage MOSFET 3.1.1 On-resistance distribution of MOSFET with different voltage resistance: The resistance proportional distribution of each part of the on-resistance of MOSFET with different voltage resistance is also different. For example, the epitaxial layer resistance of 30V MOSFET is only 29% of the total on resistance, and the epitaxial layer resistance of 600V MOSFET is 96.5% of the total on resistance. From this, it can be inferred that the on-resistance of 800V MOSFET will be almost occupied by the epitaxial layer resistance. In order to obtain high blocking voltage, the epitaxial layer with high resistivity must be used and thickened. This is the fundamental reason for the high on resistance caused by the conventional high voltage MOSFET structure. 3.1.2 The Idea of Reducing the On-Resistance of High Voltage MOSFET Increasing the core area can reduce the on-resistance, but the cost is not allowed by commercial products. Although the introduction of minority carrier for conducting electricity can reduce the conduction voltage drop, but the price is the decrease of switching speed and the appearance of trailing current, the increase of switching loss and the loss of the high speed advantage of MOSFET. The above two methods can not reduce the on-resistance of high voltage MOSFET, the remaining idea is how to separately solve the low doping of high voltage, high resistivity region and the high doping, low resistivity of conductive channel. For example, it has no other use except that the high voltage epitaxial layer low doping can only increase the on resistance. In this way, whether we can realize the conductive channel with high doping and low resistivity, and try to clamp the channel in some way when the MOSFET is turned off, so that the voltage withstand of the whole device depends only on the low doping N-epitaxial layer. Based on this idea, INFINEON introduced a built-in transverse electric field voltage of 600V COOLMOS in 1988 to realize this idea. The profile structure of the high voltage MOSFET with built-in transverse electric field and the schematic diagram of high blocking voltage and low on resistance are shown in figure 5. Different from the conventional MOSFET structure, the MOSFET with the built-in transverse electric field embeds the vertical region P and clamps the region N of the vertical conductive region in the middle, so that when the MOSFET is turned off, the transverse electric field is established between the vertical P and N. The N doping concentration in the vertical conductive region is higher than that in the epitaxial region. When VGS is less than VTH, the N-type conductive channel caused by the inversion of electric field cannot be formed, and the positive voltage between D and S makes the PN junction inside MOSFET backward bias to form a depletion layer and the vertically conductive region N is exhausted. This depletion layer has a longitudinal high blocking voltage, as shown in figure 5 (b), where the voltage resistance of the device depends on the voltage resistance of P and N-. Therefore, low doping and high resistivity of N-are necessary. Fig 5. When CGS is greater than VTH, the N-type conductive channel is formed by the inversion of electric field. The electrons in the source region enter the exhausted vertical region N to neutralize positive charge through the conductive channel, thereby restoring the exhausted N-type characteristics, so the conductive channel is formed. Because of the low resistivity in the vertical region N, the on-resistance will be significantly lower than that of the conventional MOSFET. Through the above analysis, we can see that the blocking voltage and on-resistance are in different functional areas. The contradiction between the blocking voltage and the on-resistance is solved by separating the blocking voltage from the on-resistance function. At the same time, the surface PN junction is transformed into a buried PN junction, and the blocking voltage can be further increased at the same N-doping concentration. 3.2 Main Characteristics of Built-in Transverse Electric Field MOSFET 3.2.1 The decrease of on-resistance The MOSFET of the built-in transverse electric field of the INFINEON withstands 600V and 800V respectively. Compared with conventional MOSFET devices, the on-resistance with the same core area decreases to one fifth and one tenth of conventional MOSFET, and the on-resistance decreases to one second and one third respectively at the same rated current. Under the conditions of rated junction temperature and rated current, the conduction voltage is reduced from 12.6V, 19.1V to 6.07V, 7.5V, and the conduction loss is reduced to one second and one third of conventional MOSFET, respectively. Because of the decrease of conduction loss, the decrease of heat and the relative coolness of the device, it is called COOLMOS. 3.2.2 The reduction of package and the reduction of thermal resistance Compared with the conventional MOSFET, the core of the COOLMOS with the same rated current is reduced to one third and one fourth, which reduces the package by two shell specifications. Because the thickness of COOLMOS core is only one third of that of conventional MOSFET, the RTHJC of TO-220 package is reduced from 1 ℃ / W to 0.6 ℃ / W, and the rated power is increased from 125W to 208W, which improves the heat dissipation capacity of the core. 3.2.3 Improvement of switching characteristics The gate charge and switching parameters of COOLMOS are obviously better than those of conventional MOSFET. Due to the decrease of QG, especially QGD, the switching time of COOLMOS is about one second of that of conventional MOSFET, and the switching loss is reduced by about 50%. The decrease of turn-off time is also related to the low gate resistance in COOLMOS. 3.2.4 Anti-avalanche breakdown ability and SCSOA At present, the new MOSFET has the ability to resist avalanche breakdown without exception. COOLMOS also has the ability to resist avalanche. At the same rated current, the IAS of COOLMOS is the same as ID25 ℃. However, because of the decrease of the core area, when the IAS is smaller than the conventional MOSFET, and has the same core area, the IAS and EAS are larger than the conventional MOSFET. One of the biggest features of COOLMOS is that it has a short circuit safe operation area (SCSOA), but the conventional MOS does not have this feature. The SCSOA of COOLMOS is mainly due to the change of transfer characteristics and the decrease of core thermal resistance. The transfer characteristics of COOLMOS are shown in figure 6. As we can see from figure 6, when VGS is greater than 8V, the drain current of COOLMOS no longer increases, showing a constant current state. Especially when the junction temperature increases, the constant current value decreases, and at the highest junction temperature, it is about twice as much as ID25 ℃, that is, 3 to 3.5 times of the normal working current. In the short circuit state, the drain current will not rise to an intolerable ID25 ℃ due to the 15V drive voltage of the gate, so that the power dissipated by the COOLMOS in the short circuit is limited to 350V × 2ID25 ℃, so as to reduce the core heat during the short circuit as much as possible. The decrease of the thermal resistance of the core can make the heat generated by the core radiate quickly to the shell and restrain the rising rate of the core temperature. Therefore, COOLMOS can be driven by normal gate voltage, withstand 10 MS short circuit shock under 0.6VDSS power supply voltage for 1000 times without damage and the time interval is greater than 1s. Therefore, COOLMOS can be protected effectively in short circuit like IGBT. Fig 6. 3.3 Development Status of Built-in Transverse Electric Field High Voltage MOSFET Following the introduction of COOLMOS in 1988, ST introduced 500V internal structure similar to COOLMOS in early 2000, so that 500V, 12A MOSFET can be packaged in TO-220 shell, the on-resistance is 0.35 Ω, which is lower than that of IRFP450, and the current rating is similar to that of IRFP450. IXYS also has MOSFET that uses COOLMOS technology. IR also introduced the super MOSFET, rated current of 35A and 59A in SUPPER220, SUPPER247 package, and the on-voltage drop of about 4.7V when the on-resistance is 0.082 Ω, 0.045 Ω and 150C, respectively. From the comprehensive index, these MOSFET are superior to the conventional MOSFET. The proportional decrease of on resistance is not due to the increase of core area. Therefore, it can be considered that the above MOSFET must have a special structure similar to the transverse electric field. It can be seen that trying to reduce the conduction pressure drop of high pressure MOSFET has become a reality, and will promote the application of high voltage MOSFET. 3.4 Comparison between COOLMOS and IGBT The high temperature conduction voltage drop of 600V and 800V COOLMOS is about 6V and 7.5V respectively, the turn-off loss is reduced by one second, and the total loss is reduced by more than one second, so that the total loss is 40% to 50% of that of conventional MOSFET. The conduction loss of the conventional 600V MOSFET accounts for about 75% of the total loss, and the equilibrium point corresponding to the same total loss and ultra-high speed IGBT is 160KHZ, of which the switching loss accounts for about 75%. Because the total loss of COOLMOS is reduced to 40% to 50% of that of conventional MOSFET, the corresponding IGBT loss balance frequency will be reduced from 160KHZ to about 40KHZ, which increases the application of MOSFET in high voltage. From the above discussion, it can be seen that the new high voltage MOSFET solves the problem of high conduction voltage drop, and can simplify the design of the whole machine, such as the volume of heat dissipation device can be reduced to about 40%, drive circuit and buffer circuit are simplified. It has the ability to resist avalanche breakdown and short circuit, simplify the protection circuit and improve the reliability of the whole machine. 4. Power MOSFET drive circuit Power MOSFET is a voltage type driver. Because there is no minority carrier storage effect, the input impedance is high, the switching speed can be very high, the drive power is small, and the circuit is simple. However, the interpolar capacitance of the power MOSFET is large, and the relationship between the input capacitance CISS, the output capacitance COSS, the feedback capacitance CRSS and the interpolar capacitance can be expressed as follows: The gate input of the power MOSFET is equivalent to a capacitive network, and its working speed is related to the internal impedance of the drive source. Due to the existence of CISS, the gate drive current is almost zero in static state, but a certain drive current is still needed in the dynamic process of turning on and off. It is assumed that the gate voltage required for saturation conduction of the switch tube is VGS, the turn-on time TON of the switch includes two parts: the turn-on delay time TD and the rise time TR. During the turn-off process of the switch tube, CISS is discharged through ROFF, COSS is charged by RL, COSS is larger, VDS(T) rises slowly. With the increase of VDS(T), COSS decreases rapidly to close to zero, and VDS(T) increases rapidly. According to the above analysis of the characteristics of the power MOSFET, the drive requirements are as follows: The trigger pulse should have a fast enough rise and fall speed; Charging with low resistance gate capacitance when turned on, and providing low resistance discharge circuit for gate when turned off in order to improve the switching speed of power MOSFET; In order to enable the power MOSFET to turn on by trigger, the trigger pulse voltage should be higher than the opening voltage of the tube. In order to prevent misconduction, a negative gate source voltage should be provided at its cut-off time; When the power switch switches, the drive current is the charge and discharge current of the gate capacitance. The larger the interelectrode capacitance of the power tube is, the greater the required current is, that is, the greater the load capacity is. 4.1 Introduction and Analysis of Several MOSFET Drive Circuits 4.1.1 An unisolated complementary drive circuit Figure 7 (a) is a commonly used low power drive circuit, which is simple, reliable and low cost. It is suitable for low power switchgear that does not require isolation. The drive circuit shown in figure 7 (b) has fast switching speed and strong drive capability. In order to prevent the two MOSFET tubes from going straight through, a 0.5 × 1 Ω low resistance is usually connected in series for current limiting. The circuit is suitable for medium power switchgear that does not require isolation. These two kinds of circuits are characterized by simple structure. Fig 7. Power MOSFET is a voltage type control device. As long as the voltage applied between the gate and the source exceeds its threshold voltage, it will be turned on. Because of the junction capacitance of MOSFET, the sudden rise of the voltage at both ends of the drain source will produce interference voltage at both ends of the gate source through the junction capacitance when it is turned off. The turn-off circuit of the commonly used complementary drive circuit has small impedance and fast turn-off speed, but it cannot provide negative pressure, so its anti-interference is poor. In order to improve the anti-interference of the circuit, a circuit composed of V1, V2 and R can be added to the drive circuit to produce a negative pressure. The circuit schematic diagram is shown in Fig. 8. Fig 8. When V1 is turned on, V 2 is turned off, the gate and source of the upper tube in the two MOSFET are discharged, and the gate and source of the lower tube are charged, that is, the upper tube is turned off and the lower tube is turned on, which is turned off by the driven power tube. On the contrary, when V1 is turned off, V 2 is turned on, the upper tube is turned on, and the lower tube is turned off thus to turn on the driven pipe. Because the gate and source of the upper and lower tubes are charged and discharged through different circuits, including the circuit of V 2 and because V2 will continue to exit saturation until it is turned off, it is slower for S1 to turn on than to turn off, and faster to turn on than to turn off for S2. Therefore, the degree of fever of the two tubes is not exactly the same; S1 is more serious than S2. The disadvantage of the drive circuit is that it needs double power supply, and because the value of R cannot be too large, otherwise it will make V1 deeply saturated and affect the turn-off speed. So, there will be a certain loss on R. 4.1.2 Isolated drive circuit Forward drive circuit The circuit principle is shown in figure 9 (a). N3 is demagnetizing winding and S2 is the driven power tube. R2 is a damping resistance to prevent voltage oscillation at the gate and source end of the power tube. Because the leakage sense is not required to be small, and in terms of speed, R2 is generally small, so it is ignored in the analysis. Fig 9. Its equivalent circuit diagram, as shown in figure 9 (b), is a secondary side parallel resistor R1, which is not required for pulse and used as a false load of the forward converter to eliminate the misconduction caused by output voltage oscillations during the turn-off period. At the same time, it can also be used as an energy release circuit when the power MOSFET is turned off. The conduction speed of the drive circuit is mainly related to the driven S2 gate, the equivalent input capacitance of the source, the speed of the drive signal of S1 and the current provided by S1. From the simulation and analysis, we know that the smaller the duty ratio D, the larger R1, the larger L, the smaller the magnetization current, the smaller the U1 value, the slower the turn-off speed. The circuit has the following advantages: The structure of the circuit is simple and reliable, and the isolated drive is realized; Only a single power supply can provide positive pressure when on and negative pressure when off; When the duty ratio is fixed, the drive circuit can have a fast switching speed through the reasonable parameter design. The disadvantages of the circuit are as follows: First, because the secondary side of the isolation transformer needs a false load to prevent oscillation, so the circuit loss is large; second, when the duty ratio changes, the turn-off speed changes greatly. When the pulse width is narrow, the turn-off speed of MOSFET gate becomes slower due to the decrease of stored energy. A complementary drive circuit with an isolation transformer As shown in figure 10, V1 and V2 are complementary, capacitance C acts as an isolated DC, and T1 is a magnetic ring or tank with high frequency and high magnetic flux. Fig 10. The voltage on the isolation transformer is (1 / D) Ui when it is on and D Ui when it is turned off. If the voltage of the main power tube S by conduction is 12 V and the original side-to-turn ratio N1/N2 of the isolation transformer is 12 / [(1 / (1) Ui], the C value can be slightly larger in order to ensure the voltage stability of GS during the conduction period. The circuit has the following advantages: The circuit structure is simple and reliable, and has the function of electrical isolation. The turn-off ability of the drive does not change when the pulse width changes; The circuit only needs one power supply, that is, it works as a single power supply. The function of isolated capacitance C can provide a negative pressure when the driven tube is turned off, which accelerates the turn-off of the power tube and has high anti-interference ability; However, one of the major disadvantages of the circuit is that the amplitude of the output voltage will change with the change of duty ratio. When D is small, the negative voltage is small, the anti-interference of the circuit becomes worse, and the positive voltage is higher, so we should pay attention to make its amplitude not exceed the allowable voltage of MOSFET gate. When D is greater than 0.5, the positive voltage of drive voltage is less than its negative voltage, so it should be noted that the negative voltage does not exceed the allowable voltage of MOAFET gate. Therefore, the circuit is more suitable for situations where the duty ratio is fixed or the duty ratio variation range is small or the duty ratio is less than 0.5. Drive Circuit composed of Integrated Chip UC3724/3725 The circuit composition is shown in fig. 11. UC3724 is used to generate high frequency carrier signal, and the carrier frequency is determined by capacitance CT and resistance RT. In general, the carrier frequency is less than 600kHz, and high frequency modulation waves are generated at both ends of feet 4 and 6. After being isolated by high frequency small magnetic ring transformer, it is sent to feet 7 and 8 of UC3725 chip and modulated by UC3725 and the Drive signal is obtained. A Schottky rectifier bridge in UC3725 simultaneously rectifies the high frequency modulation waves of feet 7 and 8 into a DC voltage for drive power.Generally speaking, the higher the carrier frequency is, the shorter the drive delay time will be, but the anti-interference will become worse if it is too high. The larger the magnetization inductance of the isolation transformer is, the smaller the magnetization current, the less the UC3724 heat will be. However, with the increase of the number of turns, the influence of parasitic parameters becomes greater, and the anti-interference ability will also be weakened.According to the experimental data, it is concluded that for the signal whose switching frequency is less than 100kHz, it is better to choose (400 to 500) kHz carrier frequency, the transformer uses high magnetic conductivity such as 5K, 7K and other high frequency ring magnetic core, the original magnetization inductance is less than about 1 milligram. This kind of drive circuit is only suitable for the situation where the signal frequency is less than 100kHz. If the signal frequency relative carrier frequency is too high, the relative delay is too much, and the drive power is increased, and the heating temperature of UC3724 and UC3725 chips is higher. Therefore, the switching frequency above 100kHz can only be applied to the MOSFET with smaller pole capacitance. When switching frequency of 1kVA is less than 100kHz, it is a good drive circuit. The circuit has the following characteristics: single power supply, the control signal is isolated from the drive, and the structure is simple and small, especially suitable for the situation where the duty ratio is uncertain or the signal frequency is also changed. Fig 11.
kynix On 2016-09-01
Join our mailing list!
Be the first to know about new products, special offers, and more.
Feature Posts
How Resistors Work: From Basic Principles to Advanced Applications2025-07-30
DC Switching Regulators: Principles, Selection, and Applications2025-05-30
FPGA vs CPLD: In-depth Analysis of Architecture, Performance and Application2025-05-07
MOSFET Technology: Essential Guide to Working Principles & Applications2025-05-04
SMD Resistor: Types, Applications, and Selection Guide2025-04-30