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Introduction & Technical Background:Investigating the intriguing domains of FPGA (Field-Programmable Gate Array) and microcontrollers demonstrates the critical roles these two technologies play in embedded systems and digital design. By programming FPGAs at the hardware level, users can design unique digital circuits using these incredibly adaptable integrated circuits. Because of their great flexibility, they are perfect for complicated applications that need to be reconfigurable and prototyped quickly. Microcontrollers, on the other hand, are small integrated circuits that house a CPU core, memory, and several peripherals on a single chip. They offer an affordable option for simple to moderately complicated applications and are built for specialized needs. A microcontroller is a small integrated circuit that is used in embedded systems to control particular functions. Integrated circuits known as Field Programmable Gate Arrays (FPGAs) are frequently offered off-the-shelf. The reason they are called "field-programmable" is because they enable users to modify the hardware after it has been manufactured to satisfy certain use case specifications. FPGAs are "field-programmable," meaning that users can program the hardware after it is manufactured, whereas microcontrollers can only be more loosely customized. Microcontrollers:"Microcontrollers (MCU) are used in embedded systems to perform a certain task, handle communication, and control other hardware components." ( Pervasive Cardiovascular and Respiratory Monitoring Devices, 2023). To manage a single function in a device, a microcontroller is integrated into a system. It accomplishes this by using its core CPU to evaluate data that it gets from its I/O peripherals. In the home and workplace, building automation, manufacturing, robotics, automotive, lighting, smart energy, industrial automation, communications, and Internet of Things (IoT) deployments are just a few of the industries and applications that use microcontrollers. FPGAs"An FPGA is, as the name implies, a component comprising a large number of logic gates and other functional parts connected by a network, the connectivity of which can be determined by “programming” the device." (High-Performance Computing, 2018). The majority of FPGAs are programmed using an SRAM-based methodology. These FPGAs require external boot devices, but they can be programmed and reprogrammed in-system. Digital signal processing, biomedical instrumentation, device controllers, software-defined radio, random logic, medical imaging, computer hardware emulation, voice recognition, cryptography, filtering and communication encoding, and more are some of the specific applications that make use of an FPGA. Comparison between Microcontrollers and FPGAs:Power Consumption:In comparison and contrast, FPGAs are less efficient than parts like ASICs (Application Specific Integrated Circuits). When logic utilization drops due to reprogramming an FPGA, inefficiency also results. Similarly, more power is consumed when transistors are not in use. Microcontrollers are slower than FPGAs, though. The degree of customization and complexity that separates an FPGA from a microcontroller is the primary distinction. Their cost and level of usability also differ. In essence, an FPGA enables more intricate operations, higher levels of customization, and hardware modifications that can be made in the past. Because of their massive number of programmable parts and parallel architecture, FPGAs typically use more power than microcontrollers. An FPGA's power consumption is influenced by several variables, including the quantity of active logic parts, the interconnect switching frequency, and the I/O activity. Processing Speed:A microcontroller's typical processing speed falls between MHz to 50 MHz. While on the other hand, clock rates for FPGAs typically range from 100 MHz to 200 MHz. Compared to a CPU, which can readily operate at 3 GHz or higher, these rates are far lower. Flexibility & Programmability:When deciding between FPGAs and microcontrollers, the desired application's needs for customization and flexibility must be taken into account. An FPGA might be a preferable option if the application calls for a high level of hardware customization and flexibility. A microcontroller, however, would be more appropriate if the application could profit from the software-based customization and integrated peripherals that microcontrollers provide. It is crucial to take the target application's complexity and development time into account while deciding between FPGAs and microcontrollers. An FPGA can be a preferable option if the application calls for a high level of hardware customization and the development team has the required FPGA development experience. A microcontroller might be a better option, though, if the application can take advantage of the simpler and quicker development process that microcontrollers provide and the development team has more software development experience. The decision between FPGAs and microcontrollers can also be influenced by development time and complexity. A microcontroller can be a better option because of its easier and quicker development process if the development team has more experience with software development and high-level programming languages. On the other hand, an FPGA can be a preferable option if the team has experience with FPGA development and the application requires a high level of hardware customization. Through meticulous examination of the specifications and comparative analysis of various technologies, designers can make well-informed choices that optimize performance, power efficiency, flexibility, and development time, all while meeting the demands of their intended application. It is crucial to assess the unique needs of the intended application and balance the benefits and drawbacks of each technology when evaluating cost-related issues. An FPGA might be a preferable option if the application requires high-performance parallel processing and can afford the higher initial price of FPGAs. A microcontroller might be more appropriate, though, if the application can profit from the cheaper initial costs and easier development process that microcontrollers provide. Application FieldsMicrocontrollers are utilized in automatically operated items and gadgets, including power tools, toys, office equipment, appliances, implanted medical devices, remote controls, car engine control systems, and other embedded systems. Small, inexpensive, programmable microcontrollers are used to regulate the operation and behavior of a wide range of consumer electronics devices. They can communicate with sensors, buttons, LEDs, displays, motors, and other parts since they are integrated into circuits. Numerous characteristics of microcontrollers make them suited for use in embedded systems, including: Because every required peripheral is housed on a single integrated circuit chip, they are self-contained. They are intended to execute one specific application.FPGAs are perfect for applications like data analytics, machine learning, and scientific simulations because they can be programmed to create specialized hardware circuits that can execute certain algorithms far quicker than CPUs and GPUs. Because of their ability to make use of both temporal and spatial parallelism, FPGAs are frequently employed as implementation platforms for real-time image processing applications. FPGAs are advantageous in excellent-performance Computing applications because of their excellent energy efficiency, low latency, and parallel processing capabilities. They have been applied to several High-Performance Computing use cases, including data compression, cryptography, and machine learning. ConclusionIn conclusion, diverse applications can benefit from the distinct benefits and challenges that FPGAs and microcontrollers offer. Microcontrollers have a simpler development process and use less power than FPGAs, but FPGAs are better at parallel processing workloads and allow a great degree of hardware customization. It is crucial to take into account aspects like cost, development time, performance, power consumption, adaptability, and the particular needs of the intended application while deciding between various technologies. Through meticulous assessment of these variables and comprehensive consideration of the benefits and drawbacks of each technology, designers are better equipped to make options that best suit their projects' requirements, maximizing flexibility, power efficiency, performance, and development time.

Introduction FPGA is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It appears as a semi-custom circuit in the field of application specific integrated circuits (ASIC), which not only solves the shortcomings of the custom circuit, but also overcomes the limited number of gate circuits of the original programmable device. FPGA is often used in communication, network and other fields to process a large number of network data packets. It is also widely used in aerospace, military defense and other fields. As a hardware test platform before other chips are taped out, it plays an important role in cloud computing, artificial intelligence (AI) and other fields. FPGA Applications, Features and Selection Catalog Introduction Ⅰ FPGA Basic Architecture Ⅱ FPGA Basic Features Ⅲ FPGA Applications 3.1 Circuit Design 3.2 Product Design 3.3 System Application Ⅳ Vacuum Cleaner Based on FPGA 4.1 A Short Brief 4.2 The Composition of the Platform 4.3 Main Hardware Design 4.4 Program Design Points Ⅴ FAQ Ⅰ FPGA Basic Architecture FPGA consists of 6 parts, namely programmable input/output (I/O) unit, basic programmable logic unit, embedded RAM, abundant wiring resources, bottom embedded functional unit and embedded dedicated hard core. Figure 1. FPGA Basic Architecture Each unit is described as follows:🔺Programmable I/O UnitAt present, most FPGA I/O units are designed in programmable mode, that is, through the flexible configuration of software, they can adapt to different electrical standards and I/O physical characteristics; the matching impedance characteristics, the pull-up and pull-down resistors can be adjusted; the output drive current can be adjusted, etc.🔺Basic Programmable Logic UnitThe basic programmable logic unit of FPGA is composed of a look-up table (LUT) and a register. The look-up table completes the pure combinational logic function. FPGA internal registers can be configured as flip-flops with synchronous/asynchronous reset and set, clock enabled, or as latches. FPGA generally relies on registers to complete synchronous sequential logic design. Generally speaking, the configuration of a classic basic programmable unit is a register plus a LUT. However, the internal structures of registers and look-up tables of different manufacturers are different, so the combination modes are also different.An important aspect of learning the LUT and Register ratios of the underlying hive is device selection and sizing. In addition to the basic programmable logic units inside the FPGA, there are embedded RAM, PLL or DLL, dedicated Hard IP Core, etc. These modules can also be equivalent to a certain scale of system gates, so the simple and scientific method is use the number of Registers or LUTs of the device to measure.🔺Embedded RAMNow most FPGAs have embedded RAM, which can be configured as single-port RAM, dual-port RAM, pseudo-dual-port RAM, CAM, FIFO and other storage structures.CAM is the content address memory. The data written to the CAM is compared with every data stored in it and returns the addresses of all internal data that are the same as the port data. Simply put, RAM is a storage unit for writing addresses and reading data, while CAM is just the opposite of RAM. In addition to block RAM, Xilinx and Lattice FPGAs can flexibly configure LUTs into storage structures such as RAM, ROM, and FIFO.🔺Rich Wiring ResourcesThe routing resources connect all the units in the FPGA, and the length and process of the connection determine the driving ability and transmission speed of the signal on the connection. Here the division of wiring resources:1) Full dedicated routing resources: Complete the routing of the global clock and global reset/set within the device.2) Long-term resources: Used to complete the wiring of some high-speed signals and some second global clock signals between device banks.3) Short-circuit resources: Used to complete the logic interconnection and wiring between basic logic units.4) Others: There are various wiring resources and control signal lines such as dedicated clock and reset in the logic unit.In the design process, the place and router often automatically selects the available routing resources to connect the underlying unit modules used according to the topology and constraints of the input logic netlist, so routing resources are often ignored. In fact, the optimization of routing resources is directly related to the use and implementation results.🔺The bottom layer is embedded with functional units, and the resources embedded by different manufacturers will be different.🔺Embedded dedicated hard coreDifferent from the "low-level embedded unit", the hard cores here are mainly those with relatively weak generality, and not all FPGA devices contain hard cores.   Ⅱ FPGA Basic Features 1) Using FPGA to design ASIC circuit (application-specific integrated circuit), users can get suitable chips without film production.2) FPGA can be used as a mid-scale sample for other full-custom or semi-custom ASIC circuits.3) There are abundant triggers and I/O pins inside the FPGA.4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk in the ASIC circuit.5) FPGA adopts high-speed CMOS technology with low power consumption and is compatible with CMOS and TTL levels. Figure  2. FPGA Chip Ⅲ FPGA Applications 3.1 Circuit Design Connection logic and control logic are the areas where FPGA played a relatively important role in the early days and are also the cornerstone of FPGA applications. In fact, it is still quite difficult to apply FPGA in circuit design, which requires developers to have corresponding hardware knowledge (circuit knowledge) and software application capabilities (development tools). So talents in this area are always in short supply, and they are often engaged in new technologies. The successful product development of new products will become the mainstream basic products in the market for designers to apply. In the near future, the design of general-purpose and special-purpose IP will become popular. 3.2 Product Design Apply relatively mature technology to some specific fields such as communication, video, information processing, etc. to develop products that meet the needs of the industry and can be accepted by industry customers. This aspect is mainly a combination of FPGA and professional technology. In addition, there are product design for interface issues with professional customers also includes professional tool products and civilian products. The former focuses on performance, while the latter focuses on price-sensitive product design to achieve product functions as the main purpose.FPGA is a means of realization. In this field, it has the characteristics of interface, control, functional IP, embedded CPU, etc. to realize a system product design with simple structure, high degree of curing, and comprehensive functions for FPGA market. 3.3 System Application The system-level application is the combination of FPGA and traditional computer technology to realize an FPGA version of the computer system. For example, Xilinx V-4, V-5 series FPGA is used to realize the embedded POWER PC CPU, and then cooperate with various peripheral functions. To achieve a basic environment, running LINUX and other systems on this platform also supports various standard peripherals and functional interfaces, which is very helpful for quickly forming large-scale FPGA systems.In system-level applications, if the developers do not have the ability to expand the system, it is meaningless to just engage in programming. Of course, the development of device drivers is another case. The system-level application seems to have a high starting point, but it does not have deep development ability, it is likely to become a hobbyist, just like many people can make web pages but cannot be called programming.   Ⅳ Vacuum Cleaner Based on FPGA 4.1 A Short Brief Design of indoor intelligent vacuuming platform based on FPGA.Intelligent environmental cleaners have increasingly become the focus of research because they can replace people in environmental cleaning. Although they achieve intelligence, most of them have complex structures and high integration, which are not conducive to developers to expand their functions. On the basis of researching and summarizing the relatively mature products on the market, this paper designs and implements an indoor intelligent vacuuming platform based on a highly programmable FPGA. The platform has self-navigation, can clean most of the space, and is compact in shape, stable in operation and low in noise. More importantly, it has a simple structure and a user-friendly interface, which is convenient for further development of operation and functions. Figure  3. Body Frame 4.2 The Composition of the Platform The overall frame design of the platform proposed in this paper is shown in Figure 3, and a car with four wheels is used as the carrier of the entire platform. The FPGA controller is used as the main controller of the entire platform, and is connected to the photoelectric sensors jk1, jk2, jk3, jk4 and the collision switch jk5 through I/O to realize the detection of platform obstacles. Then output PWM waveform through I/O to drive speakers and high-low, and the change of the level drives the on and off of the LED to form an acousto-optic circuit. Finally the stepper motor dj1, dj2 and the DC dust collection motor dj3 are driven by controlling the signal control line of the motor driver to realize the movement and dust collection of the platform. 4.3 Main Hardware Design The system is mainly composed of FPGA main control chip, photoelectric sensor, collision switch, wireless remote control transmitter module controlled by two STC89C52 microcontrollers, two mode selection chips, acousto-optic circuit, drive motor, vacuum cleaner motor and the power supply circuit of the whole system, such as as shown in the Figure 4. Figure  4. Main Control System 🔺FPGA Chip SelectionAccording to the overall design of the platform, the basic requirements for the chip can be drawn:(1) At least 6 PWM waveform outputs are required.(2) One serial communication interface is required.(3) A real-time chip that requires a higher 12 V to be converted to 3.3 V.(4) Higher processing speed.(5) There are more I/O interfaces.Taking these conditions into consideration, the EP2C35F672C6 model in the CycloneII series FPGA produced by Altera can basically meet the requirements. It has excellent operation speed, low cost and DSP module, large internal memory, multi-channel PWM output, flexible design and comprehensive use of multiple languages, and the cost performance is relatively high.🔺Configuration Circuit Design Points(1) Power supply circuit: The power supply system uses 12V power supply as the input power supply, uses L7805CV to step down it to 5V, and then converts 5V to 3.3V and 1.2V by TPS37HD301. The power supply point of the I/O port of the FPGA is 3.3V, the core supply voltage is 1.2V. Because the motor drive system uses the 5V signal of the controller, and the port voltage of the FPGA is 3.3V, the I/O voltage must be boosted to 5V, and the 74HCT245 boost chip is used here.(2) Clock and reset circuit: ZPB-26-16 M is an active crystal oscillator in the clock circuit, and the frequency is 16MHz, which makes the serial port baud rate more accurate. At the same time, it can support the PPL function and ISP download function inside the chip. The reset circuit takes hardware reset and software reset.(3) Debug JTAG and download circuit: Because the soft core ISP and JTAG can be built directly inside the FPGA, the hardware circuit is connected to a JTAG interface of IDC-10.(4) Configuration storage circuit: EPCS16 is selected as the ROM of the FPGA, which can be repeatedly programmed by the download cable or other equipment, and can also be programmed online through the AS interface. Use the 4MHz On-Chip memory inside the FPGA chip as the RAM of the FPGA.(5) Sensor and collision switch: E3F-DS5C4.P1R photoelectric switch, used to detect obstacles and stairs, which is a cylindrical diffusion type with a maximum distance of 5cm, or an adjustable NPN type normally open photoelectric switch. The collision switch mainly cooperates with the front sensor to protect the front of the platform. When the platform hits the obstacle ahead, trigger the switch to make the platform avoid the obstacle.(6) Wireless sending and receiving module: XL02-232AP1 wireless module is a half-duplex wireless transmission module with UART interface, which can work in the 433MHz public frequency band and meet the wireless regulatory requirements.(7) Drive and vacuum motor: The platform adopts the front wheel dual drive, the motor selects the two-phase hybrid stepping type, and the vacuum cleaner motor adopts the DC motor. The main electrical parameters of the stepping motor are: ① Step angle: 1.8°② Phase current: 0.87 A③ Holding torque: 0.24 nm④ Phase resistance: 3.3 Ω⑤ Phase inductance: 5.0 mH⑥ Weight: 0.2 kg(8) Sound and light circuit and automatic cleaning time input display circuit: The sound and light circuit is mainly composed of light-emitting diodes and buzzers, which are directly connected to the FPGA to remind the working state of the platform. Use 4 buttons (OK, Initial, Up, Down) to input the cleaning time, and then three digital tubes display the set time. The cleaning time is counted by the timer inside the FPGA. When the timer is completed, the platform stops working. 4.4 Program Design Points Divide the program into two parts: hardware programming and software programming. For hardware programming, timing simulation of hardware circuits is required to determine the effect of debugging.🔺Hardware Programming and SimulationThe platform mainly generates input signals through sensors and collision switches, and processes the signals through FPGA. Finally, the FPGA transmits the processed signals to the motor, and the motor completes a series of actions, as shown in Table 1. So its logic design is the key to realize intelligence. After the hardware selection is completed, use Quartus II to build the hardware schematic diagram. After compiling, perform timing simulation on jk1, jk2, jk3, and jk4, analyze the timing relationship, estimate the performance of the design, and check and eliminate competition risks.Table 1: Relationship between Motor Status and Platform Working Status. dj1 dj2 dj3 Cleaner Status Turn Forward Turn Forward ON Vacuuming Forward Turn Back Turn Forward ON Vacuuming Left Turn Forward Turn Back ON Vacuuming Right Turn Back Turn Back ON Vacuuming Back The realization of platform work in automatic cleaning mode depends on the cooperative work of sensors (jk1, jk2, jk3, jk4) and motors (dj1, dj2, dj3), and the logical relationship is designed according to their functions.Table 2: Relationship between Sensor Status and Platform Working Status. jk1 jk2 jk3 jk4 Cleaner Status 1 1 1 1 Vacuuming Forward 1 1 0 1 Vacuuming Left 1 0 1 1 Vacuuming Right 1 0 0 1 Vacuuming Forward 0 1 0 1 Vacuuming Forward (Turn 90° Left)  0 0 1 1 Vacuuming Forward (Turn 90° Right)  0 0 0 1 Vacuuming Back When the hardware selection is completed, use Quartus II to build the hardware schematic diagram. After compiling, perform timing simulation on jk1, jk2, jk3, and jk4 to analyze the timing relationship.🔺Software ProgrammingAfter the hardware design and debugging is completed, the software system design is also carried out. Write a C program in a C language file to program the SoPC. The overall algorithm flow of the platform work is shown in Figure 5. When the platform is powered on, firstly enter the automatic cleaning and manual remote cleaning mode. After the automatic cleaning mode is selected, input the working time of the platform's automatic cleaning through the keyboard, and use the sensor to judge whether it encounters obstacles or stairs during the cleaning process. Through the interrupt, check whether the set time is reached at all times. If not, the program will return to running. However, if the set time is up, the program will end and the platform will stop working. When remote cleaning is selected, platform movement is controlled by the operator. Figure 5. Algorithm Flowchart Through hardware selection, construction and debugging, and software language writing and debugging, a simple platform has been successfully made, and various predetermined functions have been realized. Compared with similar products on the market, its structure is simpler, the cost is lower, the flexibility and scalability are stronger, and it provides a hardware-supported platform for researchers to develop more functions, which has practical value. As microprocessors continue to advance and sensing technology evolves, their performance can continue to improve and costs can continue to decline. However, in the process of simulation and implementation, it is found that its specific process algorithm is not rigorous enough, and it is necessary to continue to improve it in the future.   Ⅴ FAQ 1. What is FPGA architecture?The field-programmable gate array (FPGA) is an integrated circuit that consists of internal hardware blocks with user-programmable interconnects to customize operation for a specific application. 2. What are the parts of an FPGA?Structure of an FPGAConfigurable Logic Block (CLB)Digital Signal Processing (DSP) Slice.Transceivers.Block Random Access Memory (BRAM)Input/Output (IO) Blocks. 3. What is a basic unit of an FPGA?The configurable logic blocks (CLBs) are the basic logic unit of an FPGA. Sometimes referred to as slices or logic cells, CLBs are made up of two basic components: flip-flops and lookup tables (LUTs). 4. What is FPGA and its types?FPGA stands for Field Programmable Gate Array which is an IC that can be programmed to perform a customized operation for a specific application. They have thousands of gates. In the field of VLSI FPGAs have been very popular. 5. What is the function of FPGA?FPGAs are mainly used to design application-specific integrated circuits (ASICs). First, you design the architecture of such a circuit. Then, you use an FPGA to build and check its prototype. Errors can be corrected. 6. What is FPGA and its application?The FPGA is Field Programmable Gate Array. It is a type of device that is widely used in electronic circuits. FPGAs are semiconductor devices which contain programmable logic blocks and interconnection circuits. It can be programmed or reprogrammed to the required functionality after manufacturing. 7. What are the advantages of FPGA?FPGA advantagesLong-term availability.Updating and adaptation at the customer.Very short time-to-market.Fast and efficient systems.Acceleration of software.Real-time applications.Massively parallel data processing. 8. What is inside CLB in FPGA?A configurable logic block (CLB) is the basic repeating logic resource on an FPGA. When linked together by routing resources, the components in CLBs execute complex logic functions, implement memory functions, and synchronize code on the FPGA. 9. What are the main applications of FPGAs?Main FPGA applications are: Medical, video & image processing, telecom & datacom, server & cloud and defense and space. FPGA chips are used in both wired and wireless communications. 10. What are the industrial applications of FPGA boards?Such applications include multiple sensor dome cameras, HD (High Definition) cameras, night-vision cameras, etc. FPGAs provide the differentiation factor and the processing power to implement such complex solutions. 11. What are the applications of CPLDs and FPGAs?Applications of CPLDCPLDs can be used as bootloaders for FPGAs and other programmable systems. CPLDs are often used as address decoders and custom state machines in digital systems. Due to their small size and low power consumption, CPLDs are ideal for use in portable and handheld digital devices. 12. What programmable technology is used in a FPGA devices?FPGA emerged from relatively simpler technologies such as programmable read-only memory (PROM) and programmable logic devices (PLDs) like PAL, PLA, or Complex PLD (CPLD). It consists of three main parts: Configurable Logic Blocks — which implement logic functions. Programmable Interconnects — which implement routing. 13. What are the features of FPGA?The basic features of FPGA are: 1) FPGA design ASIC circuit, the user does not need to chip production, you can get a combination of chips. - 2) FPGA can do all other custom or semi-custom ASIC circuit of the sample sample. 3) FPGA has a rich internal trigger and I / O pin. 14. Is a FPGA a computer?An FPGA is a chip consisting of a series of logic blocks which can be modified and configured by the user. ... FPGA are programmable chips and their functionality can be updated multiple times. FPGAs come in array of size and prices and are most likely used in low-mid size volume products.

Introduction Everyone has heard of FPGA more or less, such as Bitcoin mining, or Microsoft said before that it will use FPGA instead of CPU in the data center. So what exactly is it? Why use it? Compared with CPU, GPU, and ASIC, what are the characteristics of FPGA? FPGA is a chip that can reconfigure circuits and is a hardware reconfigurable architecture. Through programming, users can change its application scenarios at any time, and it can simulate various parallel operations of hardware such as CPU and GPU. By interconnecting with the high-speed interface of the target hardware, the FPGA can complete the low-efficiency part of the target hardware, thereby achieving acceleration at the system level. What Is an FPGA? Catalog Introduction Ⅰ FPGA vs CPU vs GPU vs ASIC Ⅱ Five Advantages of FPGA 2.1 Performance 2.2 Time-to-Market 2.3 Cost 2.4 Stability 2.5 Long-Term Maintenance Ⅲ New Applications of FPGA Ⅳ Development Trend of FPGA Ⅴ FAQ Ⅰ FPGA vs CPU vs GPU vs ASIC The core difference between FPGA and CPU, GPU, ASIC chips, etc. is that the connection and logic layout of the underlying operation unit are not solidified. Users can program the logic unit and switch array through EDA software to configure the function, so as to realize the integration of specific functions.FPGA appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also improves the limited number of original programmable device gate circuits. Compared with ASIC chips, an important feature of FPGA is its programmable characteristics, that is, the user can specify the FPGA to realize a specific digital circuit through the program. Furthermore, FPGA chips are one of the best choices for small batch systems to improve system integration and reliability. Figure 1. FPGA Basic Structure So why is FPGA so fast? This is all because the computer's CPU(central processing unit) and GPU(graphics processing unit) belong to the von Neumann structure, with instruction decoding and execution, and shared memory. FPGAs, on the other hand, are instruction-free and memory-free architectures that make FPGA chips much more energy-efficient than CPUs or even GPUs. Figure 2. Von Neumann Structure In the von Neumann architecture, since the execution unit (such as the CPU core) may execute any instruction, so an instruction memory, a decoder, an operator of various instructions, and branch and jump processing logic are required. Due to the complex control logic of the instruction stream, it is impossible to have too many independent instruction streams. Therefore, the GPU uses SIMD (single instruction, multiple data) to allow multiple execution units to process different data at the same pace, and the CPU also supports SIMD instruction. The function of each logic unit of the FPGA has been determined during reprogramming, and no instructions are required. Figure 3. Computer CPU If the GPU is used for acceleration, in order to fully utilize the GPU computing, the batch size cannot be too small, and the delay will be on the order of milliseconds. Using FPGA to accelerate, only microsecond-level PCle delay is required. Why is FPGA so much lower latency than GPU? This is basically an architectural difference. FPGAs have both pipeline parallelism and data parallelism, while GPUs have almost only data parallelism (with limited pipeline depth).For example, FPGA chips can change the running hardware design on the chip every few seconds, while chips such as CPU and ASIC are already solidified when they leave the factory and cannot be changed. If ASIC, CPU, GPU, etc. are built buildings, and the routes of rooms, corridors, and stairs in the building have been fixed, while the interior of FPGA is similar to the magic staircase in Hogwarts, which can change the route of room to room at any time. In addition, FPGA does not need to compile the instruction system at the software application level like CPU and GPU. To program FPGA, use hardware description language, and directly compile and burn it into a combination of transistor circuits, that is, directly use transistor circuits to implement user algorithms.The biggest feature of FPGA is its flexibility. It can realize any digital circuit you want and can customize various circuits. Reduce the shackles of special chips, truly tailor-made for your own products, you can flexibly change the design during the design process, and have field programmability, so it is especially suitable for applications that require continuous changes in physical operation logic, such as AI algorithm optimization, data center applications, etc. Architecture Throughput（int ops） Delay Flexibility CPU ~1T N/A Very High GPU ~10T ~1ms High FPGA(Stratix V) ~1T ~1us High FPGA(Stratix 10) ~10T ~1us High ASIC ~10T ~1us Low The FPGA is set up by the RAM stored on the chip to reset its working state, so the on-chip RAM needs to be programmed when working. Users can use different programming methods according to different configuration modes, which can be said to be very flexible and convenient. The FPGA has the following configuration modes:🔺Parallel Mode: Parallel PROM, Flash configures FPGA.🔺Master-Slave Mode: One PROM configures multiple FPGAs.🔺Serial Mode: Serial PROM configures FPGA.🔺Peripheral Mode: The FPGA is used as a peripheral of the microprocessor and programmed by the microprocessor. Computational performance compared with CPU: For example, Stratix series FPGAs perform integer multiplication operations, and their performance is equivalent to that of a 20-core CPU, and for floating-point multiplication operations, their performance is equivalent to an 8-core CPU.Computational performance compared with GPU: FPGA performs integer multiplication and floating-point multiplication operations. There is an order of magnitude difference in performance compared to GPU. The computing performance of GPU can be approached by configuring multipliers and floating-point operation components. Figure 4. CPU and GPU Architecture Diagram The core advantage of FPGA for performing computation-intensive tasks: tasks such as search engine sorting and image processing have strict requirements on the return time limit of results, and it is necessary to reduce the delay of computing steps. Under the traditional GPU acceleration scheme, the data packet size is large, and the delay can reach the millisecond level. Under the FPGA acceleration scheme, the PCIe latency can be reduced to the microsecond level. Driven by long-term technology, the data transmission delay between CPU and FPGA can be reduced to less than 100 nanoseconds.The FPGA can build the same number of pipelines (pipeline parallel structure) for the number of data packet steps, and the data packets can be output immediately after being processed by multiple pipelines. The GPU data parallel mode relies on different data units to process different data packets, and the data units need to be input and output consistently. For stream computing tasks, the FPGA pipeline parallel structure has a natural advantage in latency. FPGA is used to process communication-intensive tasks and is not limited by network cards. It outperforms CPU solutions in terms of packet throughput and delay, and has strong delay stability. Therefore, FPGAs have obvious advantages over CPUs when performing large data processing tasks with high repetition rates.By programming the FPGA, the user can change the internal connection structure of the chip at any time to realize any logic function. Especially in industries with immature technical standards or rapid development and change, FPGA can effectively help enterprises reduce investment risks and sunk costs, and is a functional and economical choice. Figure 5. Computer GPU With the evolution of intelligent market demand, highly customized chips (ASIC SoC) have led to a sharp increase in market risks due to the large scale of non-repetitive investment and long R&D cycle. Relatively speaking, FPGA has advantages in the field of parallel computing tasks, and can replace some ASICs in the field of high performance and multi-channel. The demand for multi-channel computing tasks in the field of artificial intelligence (AI) drives the evolution of FPGA technology to the mainstream. Figure 6. ASIC SoC Ⅱ Five Advantages of FPGA 2.1 Performance Taking advantage of hardware parallelism, FPGAs break the sequential execution model and complete more processing tasks per clock cycle, surpassing the computing power of digital signal processors (DSPs). BDTI(Big Data Test Infrastructure), a well-known analysis and benchmarking company, has published benchmarks that show that in some applications, FPGAs can handle many times more processing power per dollar than DSP solutions. Controlling input and output (I/O) at the hardware level provides faster response times and specialized functionality to meet application needs. 2.2 Time-to-Market Despite increasing time-to-market constraints, FPGA technology offers flexibility and the ability to rapidly prototype. Users can test an idea or concept and complete verification in hardware without going through the lengthy manufacturing process of custom ASIC design. This allows users to make incremental modifications and iterate FPGA designs in hours, saving weeks. Commercial off-the-shelf (COTS) hardware provides different types of I/O connected to user-programmable FPGA chips. The increasing popularity of high-level software tools reduces the learning curve and abstraction layers, and often provides useful IP cores (pre-built functions) for advanced control and signal processing. 2.3 Cost The non-recurring engineering (NRE) cost of custom ASIC design far exceeds the cost of FPGA-based hardware solutions. The huge initial investment in ASIC design shows that OEMs need to ship thousands of chips each year, but more end users need custom hardware capabilities that enable the development of tens to hundreds of systems. The nature of programmable chips means that users can save on manufacturing costs as well as long lead times for assembly. System requirements change from time to time, but the cost of changing the FPGA design is negligible compared to ASCI's huge expense. 2.4 Stability Software tools provide the programming environment, and FPGA circuits are the real "hard" implementation of programming. Processor-based systems often contain multiple layers of abstraction that can schedule tasks and share resources among multiple processes. The driver layer controls hardware resources, while the operating system manages memory and processor bandwidth. For any given processor core, only one instruction can be executed at a time, and processor-based systems face the risk of tightly time-bound tasks taking over each other at all times. FPGAs, on the other hand, do not use an operating system, and have true parallel execution and deterministic hardware that focuses on each task, reducing the chance of stability issues. 2.5 Long-Term Maintenance As mentioned above, FPGA chips are field-upgradable without the time and expense involved in redesigning ASICs. For example, digital communication protocols contain specifications that can change over time, and ASIC-based interfaces can create maintenance and forward compatibility difficulties. Reconfigurable FPGA chips can accommodate future modifications. As a product or system matures, users can enhance functionality without spending time redesigning hardware or modifying board layouts.   Ⅲ New Applications of FPGA At present, the FPGAs mainly produced by Xilinx and Altera with the highest market share, which are all based on SRAM technology, and need to be connected to an external memory to save the program when in use. When powered on, the FPGA reads the data in the external memory into the on-chip RAM, and after completing the configuration, it enters the working state. When power off, the FPGA returns to a white chip, and the internal logic disappears. In this way, the FPGA can not only be used repeatedly, but also does not require a special programmer, but only a general EPROM and PROM programmer. So Actel, QuickLogic and other companies also provide FPGAs with anti-fuse technology, which can only be downloaded once. They have the advantages of anti-radiation, high & low temperature resistance, low power consumption and fast speed. They are widely used in military and aerospace fields. FPGA cannot be erased and written repeatedly, which is troublesome and expensive in the early stage of development. Lattice is the inventor of ISP technology, which has certain characteristics in small-scale PLD applications. Early Xilinx products generally did not involve military and aerospace markets, but now a number of products such as Q Pro-R have entered such fields.In the industrial field, FPGA chips are widely used in the industrial field, and are widely used in video processing, image processing, CNC machine tools and other fields to realize signal control and operation acceleration functions. With the development of intelligence and automation technology, the industrial field is gradually shifting from human resources as the core element to intelligent unmanned factories with automation as the core element.Smart electric vehicles will be the mainstream development direction of the automotive industry in the future. At present, the application of FPGA in automotive cameras and sensors is relatively mature. In the artificial intelligence system of automatic/intelligent driving vehicles, the applicability of FPGA will be the most suitable for processing sophisticated ADAS and autonomous driving. Figure 7. FPGA for Auto In the field of automotive electronic system interface and control, FPGA chips are used to control and drive electric vehicle motor control systems, connect various in-vehicle equipment such as driving systems, instrument panels, radar, ultrasonic sensors, etc. control. In the field of video bridging and fusion, FPGA chips can be used to realize functions such as signal bridging of multiple image sensors, 3D surround view video fusion, reversing auxiliary video, and assisted driving video.In the field of communication, the number of 5G base stations has increased, and the FPGA usage of a single base station has increased, driving the increase in FPGA demand. According to estimates, the FPGA consumption of a 5G single base station is expected to increase from 1-3 blocks in the 4G period to 4-5 blocks in the 5G period. Figure 8. RFSoC FPGA Board Target 5G eFPGA technology is superior to traditional FPGA solutions in terms of performance, cost, power consumption, profitability, etc., and can provide flexible solutions for different application scenarios and different market segments. The economic trend of increasing design complexity and falling equipment costs has stimulated the market demand for eFPGA technology.   Ⅳ Development Trend of FPGA First of all, with the commercialization of the new generation of communication technology, the demand for products such as communication base stations, servers, and intelligent terminals will further expand, thereby driving the increase in the market demand for FPGA chips. At the same time, smart cities, smart factories, and consumer electronics pay more attention to the functionality of various smart IoT devices, which will drive the wide application of FPGA chips in smart IoT devices. With the development of the Internet of Vehicles technology, the scale of the use of FPGA chips in the automotive industry will increase day by day to build a more complete Internet of Vehicles and realize smarter autonomous driving functions. Therefore, with the rapid penetration of 5G, the vigorous development of AI and the increasing trend of automotive intelligence, it is expected that the demand for FPGAs in the three fields of communication, AI and automotive electronics will continue to increase in the future, which will also promote The FPGA industry continues to grow.   Ⅴ FAQ 1. What is FPGA and why it is used?The acronym FPGA stands for Field Programmable Gate Array. It is an integrated circuit that can be programmed by a user for a specific use after it has been manufactured. ... These blocks create a physical array of logic gates that can be customized to perform specific computing tasks. 2. Is FPGA faster than GPU?The difference between GPU and FPGA performance is not a static factor, but it does depend on the size of the data set. A study by Sanaullah and Herbordt [7] revealed that FPGA can compute small samples of 3D FFT tens of times faster than GPU. The difference is less clear when the data set gets bigger. 3. Is FPGA faster than CPU?A FPGA can hit the data cell faster and more often than a CPU can do it meaning the FPGA causes more results to occur during an attack. It all goes faster when an FPGA is used. And as a side benefit, no trace of all this is left on the CPU because it's never touched when an FPGA is used. 4. Are FPGAs efficient?Efficiency and Power: FPGAs are well-known for their power efficiency. A research project done by Microsoft on an image classification project showed that Arria 10 FPGA performs almost 10 times better in power consumption. 5. Is FPGA programming hard?FPGA vendors have touted their wares as ideal replacements for DSPs, CPUs, and GPUs – even for all of them in a single device – but they are notoriously difficult for software engineers to program as they are not anything like a conventional processor. 6. What can you do with FPGAs?Uses for FPGAs cover a wide range of areas—from equipment for video and imaging, to circuitry for computer, auto, aerospace, and military applications, in addition to electronics for specialized processing and more. 7. What is the difference between processor and FPGA?Microprocessor vs FPGA: A microprocessor is a simplified CPU or Central Processing Unit. ... An FPGA doesn't have any hardwired logic blocks because that would defeat the field programmable aspect of it. An FPGA is laid out like a net with each junction containing a switch that the user can make or break. 8. What language is used to program FPGA?VerilogTraditionally, FPGAs are programmed using pro-level hardware-description languages such as Verilog or VHDL. 9. How many times can you program an FPGA?There is effectively no limit to the number of times a device can be reconfigured; the configuration is stored in SRAM, which has no write limit. most Fpgas can be passively loaded from a processor, one word at a time. That processor can get the FPGA image from anywhere. 10. What are the advantages of FPGA?FPGA advantagesLong-term availabilityUpdating and adaptation at the customerVery short time-to-marketFast and efficient systemsAcceleration of softwareReal-time applicationsMassively parallel data processing 11. How do you make an FPGA?FPGA design checklistMake sure you have plenty of time to spare.Find a decent computer.If you can afford it, add a big display.Decide which operating system to use.Consider using a virtual machine (VM).Select an FPGA vendor.Pick out a suitable development board.Select an embedded processor to use. 12. What is FPGA for beginners?FPGA stands for Field Programmable Gate Array. As you may already know, FPGA essentially is a huge array of gates that can be programmed and reconfigured any time anywhere. Huge array of gates is an oversimplified description of FPGA. FPGA is indeed much more complex than a simple array of gates. 13. What is FPGA in Verilog?FPGAs are nothing, but reconfigurable logic blocks and interconnects can be programmed by Hardware Description Language like Verilog/ VHDL to perform a specific functionality. 14. Do we need to program the FPGA once powered off?If you have a SRAM-based FPGA, like the Spartan 3, then you have to program it each time it is powered up. The reason for this is that the SRAM which stores the configuration is volatile and loses the programmed configuration after power is switched off. 15. How is FPGA different from microcontroller?One of the main differences between a microcontroller and an FPGA is that an FPGA doesn't have a fixed hardware structure, while a microcontroller does. While FPGAs include fixed logic cells, these, along with the interconnects, can be programmed in parallel by using HDL coding language.

IntroductionMany embedded designs use single board computer based on micro-processor and micro-controller(SBC) and modular system (SoM). However, people with more embedded applications can't bear the delay caused by the response time associated with software. Only the custom hardware can achieve the higher performance that these applications required, and the quickest way to develop custom hardware is to use FPGA. This article will introduce the advantages of using SoM to develop embedded systems that require higher processing power from FPGA, and will also cover the various FPGA SoM, and also discuss how they work when embedded in design and development.What is an FPGA? Intro for BeginnersCatalogs CatalogsFPGA: The Role of Modular SystemNew SoM based on SoC with processor and FPGAFunctions of SoM and SBCConclusion FPGA: The Role of Modular SystemThe modular system (SoM) can help designers to develop special shape size embedded systems with custom interfaces without having to develop kernel processing systems from scratch. Designers can insert SoM which has pre-designed and tested into pre-designed or customized cards to create embedded designs with the same functions as fully customized designs, but take much less time to develop hardware.Using SoM has several advantages over developing hardware from scratch as follows:1) Saving cost( in the process of developing and debugging the circuit board based on SoC, the non-recurrent engineering cost will be very high.)2) Multiple choices(benefiting the insertion ability of SoM)3) Developing hardware and software at the same time4) Reducing design risks5) Small packagesThe market, once dominated by microprocessors and micro-controllers, is now replaced by SoM, with through holes and socket components losing their leading role. Pin compatibility allows designers to select from a range of compatible processors that have the correct clock speed and appropriate on-chip memory capacity. However, with the increase of the number of pins and the adoption of surface mount packaging technology, this design method has become obsolete. And SoM has emerged as the times require, its shape size and substrate surface have the same function as the previous series of pin compatible micro-controllers.If SoM is used as the computing platform of the project, the design engineer can concentrate his energy and resources to develop the final application without being lost in the details of designing computing platform. For example, at the clock speed of hundreds of megahertz (MHz), the layout of the SDRAM circuit board connected to the application processor becomes increasingly difficult due to differential wire delay, noise, crosstalk and many other challenges. However, SoM vendors have done a lot of design work before the start of the project, which can solve these problems and cut the time of product launch.To select the appropriate SoM series for embedded development projects, we must carefully analyze various factors, including the expected requirements of embedded resources, as well as the design extendibility, future adaptability and ease of use. This helps to select the appropriate shape and substrate size of SoM, providing alternative options to meet known challenges and unexpected future challenges. If the selected SoM family includes multiple product members and has compatible appearance dimensions and connector base surfaces, the selection of the designers can be expanded to make the product better able to withstand the test of the future. New SoM based on SoC with processor and FPGASoM usually uses SoC which includes multiple application processors, but a new embedded processor, SoC, integrating FPGA, applies to the SoM design either, like the Zynq®-7000 SoC, Xilinx’s fully programmable processor. Xilinx Zynq-7000 SoC integrates the software programmability of Arm Cortex-A9 application processors with the hardware programmability of FPGA. Arm microprocessor, built in Zynq SoC,  combines enhanced peripherals with SDRAM memory controllers (called Zynq SoC's "processing systems" or "PS"), and performs all the software-based tasks typically handled by embedded microprocessors or microcontrollers, while integrated FPGA (known as Zynq SoC's PL: Programmable Logic) provides hardware I / O response time and hardware acceleration for embedded tasks that require faster execution speed.Xilinx Zynq SoC offers a variety of processor configurations and speeds, with even more options for FPGA structures on a chip. Choosing the SoM family based on hybrid processor FPGA SoC can expand the selection range and improve the future adaptability of the product, like Xilinx Zynq-7000 series. One example of such a SoM series is the use of the TE0782 family from Trenz Electronic (Fig.1) and the SoM supporting test panel TEBT0782-01 which adopts the Xilinx Zynq-7000. Three Members of the SoC FamilyTE0782-02-035-2I based on Xilinx Zynq Z-7035 SoCTE0782-02-045-2I based on Xilinx Zynq Z-7045 SoCTE0782-02-100-2I based on Xilinx Zynq Z-7100 SoCAll three SoMs have the same connector substrate, including three Samtec LSHM nonpolar connectors and hundreds of I / O pins, in addition, there are power and grounding pins between the SoM and the board.Fig.1 Trenz Electronic TE0782 SoMFig.1: TE0782 SoM from Trenz Electronic uses one of three Xilinx Zynq Z-7000 SoC models, as well as providing 1GB SDRAM and other non-volatile memory.The best way to see the flexibility of SoM design is to look at the TE0703 carrier board of the TE0782 SoM family, and then go back to SoM through the I / O pins to see SoM's resources.Fig.2: Trenz TE0703 Board Divides Many I / O Pins from the Relevant 4 x 5 cm SoM Boards to the Rest of the Embedded System.Many of the important I / O functions separated from the SoM board are shown in the block diagram of TE0703 as follows:1 Gbit/s EthernetUSB and Micro-USBHundreds of I/O pins(it can be configured as a singular I / O pin, or as a low-voltage differential signal pair.)Fig.3 Physical Map of Trenz TE0703-05( Trenz TE0703 family) Functions of SoM and SBCProcessing speed, response time and I / O capability are significant characteristics of SoM. However, embedded systems often integrate SBC, such as Arduino Uno and Raspberry Pi, because these products also have wide-ranging technique support. So Trenz Electronic also offers related versions of Arduino and Raspberry Pi: TE0723-03M ArduZynq and TE0726-03M ZynqBerry based on Xilinx Zynq-7000 SoC. These SBC bridges many existing plug-in cards, such as the expansion boards of  Arduino and various Raspberry.The FPGA capacity of Zynq Z-7010 SoC integrated into TE0723-03M ArduZynq and TE0726-03M ZynqBerry SBC is significantly different from that of FPGA integrated into three Trenz Electronic SoMs (using Zynq Z-7035 Zynq Z-7045 and Zynq Z-7100 SoC ). Although all Zynq-7000 SoC apply dual-core Arm Cortex-A9 processor, their FPGA on components are different. Volume of the Xilinx Zynq SoC Programmable Logic Unit Block RAM (MB) DSP slices is Z-701028K2.180Z-7035275K17.6900Z-7045350K19.2900Z-7100444K26.52020, Xilinx Zynq-7000 SoC (Z-7035, Z-7045 and Z-7100) used in Trenz Electronics SoM provides more FPGA resources than that of Zynq Z-7010 used in Trenz Electronic ArduZynq and ZynqBerry SBC.Xilinx Zynq-7000 SoC (Z-7035, Z-7045 and Z-7100) used in Trenz Electronics SoM provides more FPGA resources than that of Zynq Z-7010 used in Trenz Electronic ArduZynq and ZynqBerry SBC. In addition, TE0723-03M ArduZynq and TE0726-03M ZynqBerry SBC provide only 512-MB on-board SDRAM, while TE0782 SoM provides 1GB.Trenz Electronic provides various boards for its SoM, including TE0703-05, TE0706-02, TE0701-06, and TEB0745-02, which provide a lot of standardized I / O functionality. A certain card may be suitable for a particular embedded application, but the embedded system design can also be split into a customized design board that can accept SoM series products to meet different processing requirements. This flexibility highlights the advantages of using the SoM family as the basis for embedded design. And consistent standardized connector substrate allows SoM to be easily interchangeable to accommodate changes in system specifications. ConclusionSoM can significantly cut the time requirement of prototype embedded systems and reduce project risk. As long as the SoM profile and connector substrate are supported,  more FPGA resources of SoM can be inserted to meet the growing demand. In addition, a variety of compatible SoM based on Xilinx Zynq-7000 SoC combine the processing power of dual-core Arm Cortex-A9 processor with FPGA resources, which is helpful to accelerate the development of embedded design. The embedded design method based on SoM can not only shorten the time required to develop the hardware part, but also allow the software development to start earlier in the project, thus reducing the design cost. FAQ1. What is a FPGA used for?Image result for FPGA and ProcessorFPGAs are mainly used to design application-specific integrated circuits (ASICs). First, you design the architecture of such a circuit. Then, you use an FPGA to build and check its prototype. Errors can be corrected. 2. Is an FPGA a processor?With an FPGA, there is no chip. The user programs the hardware circuit or circuits. The programming can be a single, simple logic gate (an AND or OR function), or it can involve one or more complex functions, including functions that, together, act as a comprehensive multi-core processor. 3. What is difference between FPGA and processor?CPUs offer the most versatility and so are the best suited to perform general purpose computing. FPGAs can be used to perform more specific and specialized tasks but are not ideal for general computing purposes. 4. How many times can you reprogram an FPGA?Altera guarantees you can reprogram windowed EPROM-based devices at least 25 times. Altera does not specify the number of times you can reprogram or reconfigure FPGA devices because these devices are SRAM-based. An SRAM-based device can be reconfigured as often as a design requires; there is no specific limit. 5. What is SoM FPGA?The CompactRIO System on Module (SOM) is a small, flexible, embedded computer for industrial applications that require high performance and reliability. It combines an ARM processor, the NI Linux Real-Time OS, a programmable Xilinx FPGA, and a high-density connector to interface with application-specific I/O. You May Also LikeDiscussion on the influencing factors of clock in FPGA designTo Solve the Problems of Cloud Skyrocket--Edge Processing

Warm hints: The word in this article is about 4000 words and  reading time is about 20 minutes.SummaryThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of system clock and the delay of clock to ensure the stability of design. CoreClock in FPGA designPurposeDetermining the influencing factors of clock to ensure the stability of designEnglish nameField Programmable Gate ArrayCategoryDigital electronic circuitFunctionCreating digital circuitsFeatureTotally up to the designer to create a bit fileCatalogsCatalogsⅠ. What is Setup time and Hold timeⅢ. Analyzing with the help of timing diagram3. The composition of the state machine1. Synchronization between single bits and each pulse transmitted has at least 1 cycle width1. Setup timeⅣ. How to increase the clock working frequencyⅤ. An example showing a good method for state machine design2. The input pulse could be less than a synchronous circuit under a clock cycle width 2. Hold time1. Changing the line type for circuit wiringⅥ. The introduction of state machine Ⅱ. A basic model of synchronous design using a single clock2. Splitting the combinational logicⅦ. What we should pay attention when designing the clock in FPGA  IntroductionⅠ. What is Setup time and Hold timeThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of the system clock and the delay of the clock to ensure the stability of the design.Learn how a clock drives all sequential logic in FPGA, from Flip-Flops to Block RAMs; The clock tells you how fast you can run your FPGA;This video demonstrates how to properly deal with multiple clock domains inside your design.1. Setup timeSetup time(Tsu) is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.2. Hold timeHold time(Thd) is defined as the minimum amount of time after the clock's active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.Figure 1 Shows setup time and hold timeFigure 2 If data will change in tsu then it will cause setup violation and if data will change in thd then it will cause hold violation  DtailⅡ. A basic model of synchronous design using a single clockIn the same module of FPGA design, it often contains the combinational logic and the sequential logic. In order to guarantee the data in this logic interface can be processed steadily, then figuring out the concept of setup time and hold time is very important. Then we could be able to think about this following question:Figure 3 Shows a basic model of synchronous design using a single clockTco: Delay of the data output of the trigger;Tdelay: Delay of the combinational logic;Tsetup: The trigger's setup time;Tpd: Delay of the clock (negligible).T: clock cycleT3: D2 setup timeT4: D2 hold timeIf the first trigger D1 has a maximum setup time of T1max and a minimum of T1min, the combinational logic has a maximum delay of T2max and a minimum of T2min. The question is what conditions setup time T3 and hold time T4 of the second trigger D2 should be met, or what the maximum clock cycle given T3 and T4. This is the thing must be carefully considered in the process of design, because only by clarifying this issue can we ensure that the delay of the  combinational logic designed meets the requirements.Ⅲ. Analyzing with the help of timing diagramNow let us analyze this question with the help of timing diagram: let the input of the first flip-flop be D1, the output be Q1; the input of the second flip-flop be D2, the output be Q2;Given the clock is uniformly sampled on the rising edge, for ease of analysis we would discuss two cases, the first one: Assume that the delay of the clock Tpd is zero, which in fact, is often met in the FPGA design where the unified system clock it is generally adopted and the clock be input through the global clock pin, therefore the internal clock delay can be completely ignored. In this case, it is not necessary to consider the hold time, because each data maintains one clock tick while there is also delay line, that is, the delay based on CLOCK is much smaller than the delay based on data, so the hold time can meet the requirement. The setup time is what we should care about. If the setup time D2 meets the requirement, the timing diagram should be as shown as Figure 4.Figure 4 Shows the timing chart that meets the requirementsFrom the figure 4 we can see:T-Tco-Tdelay>T3That is Tdelay< T-Tco-T3During the setup time D2, the signal can reach D2 through the combinational logic D1, i.e. the data is already in Tsup before the second CLK arrive.Then it meets the requirement of setup time, where T as the clock period, the second flip-flop can pick up D2 on the rising edge of the second clock in this case. {D1 => setup time => hold time => trigger data output delay => combinational logic delay => D2 => ...}If the delay time of the combinational logic is too largeT-Tco-Tdelay < T3 (Tcox<D2 setup time)Then it will not meet the requirements. The second trigger will pick up an unstable state on the rising edge of the second clock, as shown in Figure 5, then the circuit will not work properly.Figure 5 The delay time of the combinational logic is too large to meet the requirementsSo you can deriveT - the Tco - T2max > = T3This is the setup time for D2.From the timing diagram above, it also can be seen that the setup time and hold time of D2 are not related to the setup and hold time of D1, except the combinational logic in front of D2 and the data transmission delay of D1. This is also a Very important conclusion, which shows that the delay has no additive effect.However, if there is a delay in the clock instead, the hold time must be considered in this case, together with the setup time. Most clocks with large delays are designed using asynchronous clocks, which is difficult to guarantee the data synchronization, so it is rarely used in actual designs. At this point, if the setup time and hold time all meet the requirements, you will see the output timing as shown in Figure 6.Figure 6. Clock has a delay but meets the timingIt can be easily seen from figure 5 that the Tpd is relaxed for the setup time, so the setup time of D2 must meet the requirements:Tpd+T-Tco-T2max>=T3 (T3 is the setup time of D2, T2max is the maximum delay of  combinatorial logic, Tpd is the clock delay)As shown in the FIG. 6, since the sum of setup time and hold time is a stable clock period (T), if the clock has a delay and the data delay is small, then the setup time will increase inevitably,  and the decrease of hold time goes with it. If it is reduced to not meet the requirement of hold time D2 , the correct data cannot be collected.That is T-(Tpd-Tco-T2min)T-(Tpd+T-Tco-T2min)>=T4 i.e. Tco+T2min-Tpd>=T4 (D2 hold time )From the formula above we could also figure out that if Tpd = 0, that is to say the delay of the clock is 0, then the same requirements goes with Tco + T2min> T4, however in practical applications the delay of T2 i.e. the delay of line is much larger than the trigger's hold time T4, it becomes not necessary to take the hold time into consideration.Figure 7 The clock has a delay and the hold time does not meet requirementsIn summary, if you do not consider the delay of the clock, the only thing you need to care about is the setup time, or the hold time instead. Then let us think about in FPGA design, how to increase the working clock in the synchronous system. AnalysisⅣ. How to increase the clock working frequencyFrom the above analysis, we can see that the requirements of setup time T3 for the D2 in the synchronization system is as follows:T-Tco-T2max>=T3So it is easy to derive:T>=T3+Tco+T2maxwhere T3 is the setup time Tset of D2, and T2 is the delay time of the combinational logic. In a design, T3 and Tco are both fixed values determined by the device, the only factor that we could control is the input delay of the combination logic T2. Therefore, by reducing T2 as much as possible, the clock working frequency can be increased. In order to achieve the reduction of T2 in the design, there are different comprehensive methods we can use.1. Changing the line type for circuit wiringAltera devices, for example, there are many bars in the quartus timing closure floorplan, so we can slice and dice them into rows and columns: Each bar represents 1 LAB, each LAB has 8 or 10 LEs in. The relationship of their routing delay is as follows: the same LAB (fastest) < the same row and column < different row and column. We could add appropriate constraints to the synthesizer (this should be given appropriate, generally 5% margin adding, for example, if the circuit works at 100Mhz, then adding constraints to 105Mhz is sufficient, because the excessive constraint could do a bad effect instead, and greatly increases the integration time) to make the relevant logic circuit wiring be placed as close as possible, thereby reducing the routing delay.2. Splitting the combinational logicSince the general synchronous circuits are more than a?single?stage latch (as shown in Figure 9), and to make the circuit stable, the clock period must meet the maximum delay requirement, and the maximum?delay of the longest path can be shortened before the operating frequency of the circuit be increased.As shown in Figure 8, we can decompose the larger combinatorial logic into smaller blocks and insert flip-flops in the middle, which can increase the operating frequency of the circuit. This is also the basic principle of the so-called "pipelining" technology.For the upper part of Figure 9, its clock frequency is subject to the delay of the second larger combinational logic. By appropriately distributing the combinational logic, excessive delay between the two flip-flops can be avoided and speed bottlenecks can be eliminated.Figure 8 Splitting combination logicFigure 9 Transferring Combination LogicHow to split the combinatorial logic in design, the better method should be accumulated in practice, but some good design ideas and methods also need to be mastered. We know that at present most of the FPGAs based on 4-input LUTs, if an output criteria corresponding is more than four inputs, then the multiple LUT cascade will be needed, thus introducing the delay of one-stage combinational logic. That is we want to reduce the number of combinational logic, the logic is nothing more than to make the input conditions as few as possible, so that less multiple LUT cascade need to be use, thereby reducing the time delay caused by combinational logic.The pipelining that we usually hear is a way to increase the operating frequency by splitting a large combinational logic (in the middle of which a singer or multiple stages of D flip-flops are inserted, thereby reducing the number of combinatorial logic between registers) to a smaller one. For example, a 32-bit counter, with a very long carry chain, will inevitably reduce the operating frequency, so we can split it into a 4-bit and a 8-bit one, whenever the 4-bit counter counts to 15 and triggers an 8-bit one, which enable the counter to be split and increases the operating frequency.Just as the same, large counters are generally moved out of the state machine, because if they, with usually more than 4 inputs, are used as state transition criteria with other conditions, they will increase the multiple LUT cascade, and then increasing the combination logic.Taking a 6-input counter as an example, we wanted to make a state transition after the counter counted to 111100, now because we put the counter out of the state machine, when it counts to 111011, a signal of "enable" is generated and then trigger the state transition, which obviously reduces the combinatorial logic.3. The composition of the state machineThe state machine generally contains three modules:An output moduleA module that determines what the next state isA module that saves the current stateThe logic used to form these three modules is also different. The output module usually contains both combinatorial logic and sequential logic; the module that determines the next state is usually composed of combinatorial logic; and the module that saves the current state is usually composed of sequential logic. The relationship between these three modules is shown in Figure 10.Figure 10 The composition of the state machineⅤ. An example showing a good method for state machine designThat is why when writing the state machine, the state machine is always divided into three parts according to these three modules. The following example shows a good method of state machine design: -----------------------------------------------------*/module arbiter2 (                    clock , // clock                    reset , // Active high, syn reset                    req_0 , // Request 0                    req_1 , // Request 1                    gnt_0 ,                    gnt_1                );//-------------Input Ports-----------------------------input    clock ;input    reset ;input    req_0 ;input    req_1 ;//-------------Output Ports----------------------------output    gnt_0 ;output    gnt_1 ;//-------------Input ports Data Type-------------------wire    clock ;wire    reset ;wire    req_0 ;wire    req_1 ;//-------------Output Ports Data Type------------------reg        gnt_0 ;reg        gnt_1 ;//-------------Internal Constants--------------------------parameter     SIZE = 3 ;parameter     IDLE = 3'b001 ,            GNT0 = 3'b010 ,            GNT1 = 3'b100 ;//-------------Internal Variables---------------------------reg        [SIZE-1:0] state ;        // Seq part of the FSMwire    [SIZE-1:0] next_state ;    // combo part of FSM //----------Code startes Here------------------------assign    next_state = fsm_function(req_0, req_1);//------------fsm_function--------------//function [SIZE-1:0] fsm_function;input     req_0;    //parameterinput     req_1;    //parameterbegin    case(state)        IDLE :                if (req_0 == 1'b1)                    fsm_function = GNT0;            else if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function = IDLE;        GNT0 :             if (req_0 == 1'b1)                fsm_function = GNT0;            else                fsm_function = IDLE;        GNT1 :            if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function =IDLE;        default : fsm_function = IDLE;        endcaseendendfunction always@(posedge clock)begin    if (reset == 1'b1)        state <= IDLE;    else        state <= next_state;end//----------Output Logic-----------------------------always @ (posedge clock)begin    if (reset == 1'b1)         begin        gnt_0 <= #1 1'b0;        gnt_1 <= #1 1'b0;        end    else         begin        case(state)            IDLE :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end            GNT0 :                 begin                gnt_0 <= #1 1'b1;                gnt_1 <= #1 1'b0;                end            GNT1 :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b1;                end            default :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end        endcase        endend // End Of Block OUTPUT_Endmodule Ⅵ. The introduction of state machineState machines are usually written in three segments to avoid excessive combinational logic.All we mentioned above shows how we could use the way of pipelining to split the combinational logic, but in some cases it is difficult for us to do that, and then what should we do?The state machine is such an example that we cannot add assembly line in the state decoding combinational logic. If there is a design of state machine with dozens of states, there is no doubt that its state decoding logic will be very large and this will be the critical path in the design. So what should we do?Just the same way, reducing the combinatorial logic. We can analyze the output of the state, reclassify and redefine them into a group of small state machines. By selecting the input (case statement) and triggering the corresponding small state machine, we can achieve a large state machine splitting into several small state machines. In the ATA6 specification (hard disk standard), there are about 20 kinds of input commands, and each piece of command corresponds to a variety of states. It is unthinkable to do it with a large state machine (nesting), however in the contrary, if you use the case statement to decode the command and trigger the corresponding state machine, in this way the module can run very fast.The key to increasing the operating frequency is to reduce the time delay from register to register, and the most effective method for reduction is to avoid large combinational logic, that is, to try to meet the four-input condition, reducing the number of LUT cascades, that’s mean that we could increase the working frequency by adding constraints, using a way of pipelining and splitting states.Ⅶ. What we should pay attention when designing the clock in FPGA1.Try to use only one clock in a module, and a module here means a module or an entity. In the design of multi-clock domain, it is better to have an extra special module for the isolation of clock domain. This allows the synthesizer to get a better results.2. Unless it is a low-power design, otherwise do not use the gated clock (gllobal Clock buffer such as IBUFG within FPGA) to control the input of clock edge of flip-flop, but use combinational logic and other timing logic (such as frequency divider) to generate signals used as the input of clock edge of flip-flop---all this is to reduce the instability of the design.3. Do not use the signals divided by counter as the clock of other modules, but  with the help of clock enable(CE). Otherwise, this clock-like manner is extremely unfavorable to the reliability of the design, and greatly increases the complexity of the static timing analysis .Ⅷ. Synchronization Between Different Clock DomainsIf two modules in a design using two respective operating clock, then at their interfaces there would emerge a phenomenon which called as Asynchronous Patterns. In order to ensure data correct processed, the two modules must be synchronized.There are usually two cases of different clock domains here (discrete clock source):1. the frequency of two clocks is different;2. the two clocks share a same frequency, but they are actually two separate clocks with no relation to the phase.Just as shown in the following two figures:Figure 11 The frequencies of two clocks are completely differentFigure 12 The frequencies of the two clocks are the same, but the phases are irrelevantThe data transmission between two clock domains usually adopts different synchronization methods according to different bit widths.1. Synchronization between single bits and each pulse transmitted has at least 1 cycle widthThis kind of synchronization is mainly used for the synchronization of some control signals. As shown in Figure 13 below:Figure 13 One bit synchronizer designThe following points are required to be explained for this synchronization:(1) synchronous circuit of figure 12 is actually called "one bit synchronizer", it can only be used for one bit asynchronous signal which must be wider than that of the Current stage’s clock, otherwise it may be unable to adopt this asynchronous signal.(2) why is the circuit in figure 13 can only be used in one bit asynchronous signals?When two or more asynchronous signals (control or address) simultaneously get into the current time domain and take control the circuit of current time domain, problems arise if these signals are all synchronized using the same circuit in FIG. 13. Skews has arisen between two or more asynchronous signals (control or address) due to connection delays or other delays, and then the skew is greatly enlarged via the synchronizer in Figure 13 when getting into the current time domain, or competition may caused and finally leading to an error in the time domain circuit.Figure 14 Problem-passing multiple control signals between clock domainsIf the asynchronous data bus is to enter the current time domain, the circuit in Figure 13 cannot be used either, because data change very randomly and the width of 0 or 1 has nothing to do with the clock pulse of the current time domain, so the circuit in Figure 13 may be unable to adopt the correct data.(3) Please note that the second trigger is not used for avoiding the occurrence of "metastable state", on the contrary, it can prevent the transmission of metastable state. In other words, once the first flip-flop becomes metastable (possibly), due to the second flip-flop, the metastability will not be transmitted to the circuit following.(4) The first-stage trigger has a metastable state, which means it will require a recovery time to stabilize again, or it is also called Withdrawal from metastable state. The recovery time plus the establishment time of the second-stage flip-flop (say more precisely, maybe also minus the clock skew) is less than or equal to the clock period, which can be easily satisfied. This is means thees two stages of flip-flop should be put together as close as possible, without any combinatorial logic between them or excessive skews to the clock, and then the second-stage flip-flop can adopt data stably and preventing the transmission of metastable state.(5) FF1 is the sampling output of FF2, so of course, what is output by FF1 is  what output by FF2, everything is the same except one cycle of delay. Note that “meta-stableit” means that once the data of FF1 enters, its electrical level would be indefinite and maybe incorrect. So although this method can prevent transmission of metastable state, it does not guarantee the data after the two-stage flip-flop is correct. Therefore, this kind of circuit always has a certain amount of fault-tolerance. This applies only to a some error-insensitive cases, but for other sensitive circuits, dual-port RAM or FIFO are better choices.2. The input pulse could be less than a synchronous circuit under a clock cycle width How is that possible? Has it not less than the original clock? For this case, the Feedback shown in Figure 15 below may usually be taken into consideration. The analysis of this circuit is as follows: Assume that the input data is high level, because the first flip-flop FF1 is high-level cleared, then all outputs should also be high and correctly adopted. On the other hand, if the input is low-level, data of FF1 would be forced to clear and the output level is zero, which ensures the correctness of the output.Figure 15 Synchronous circuit--input pulse may be less than one clock cycle width  Book SuggestionBuilding Embedded Systems: Programmable Hardware 1st ed. EditionThis is a book for embedded-system engineers and intermediate electronics enthusiasts who are seeking tighter integration between software and hardware. Those who favor the System on a Programmable Chip (SOPC) approach will in particular benefit from this book. Students in both Electrical Engineering and Computer Science can also benefit from this book and the real-life industry practice it provides.--Changyi GuDigital Integrated Circuit Design Using Verilog and Systemverilog 1st Edition, Kindle EditionFor those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. --Ronald W. MehlerPower Converters with Digital Filter Feedback Control 1st Edition, Kindle EditionThis book builds a bridge for moving a power converter with conventional analog feedback to one with modern digital filter control and enlists the state space averaging technique to identify the core control function in analytical, close form in s-domain (Laplace). It is a useful reference for all professionals and electrical engineers engaged in electrical power equipment/systems design, integration, and management.--Keng C. Wu Relevant information "Discussion on the influencing factors of clock in FPGA design"About the article "Discussion on the influencing factors of clock in FPGA design", If you have better ideas, don't hesitate to  write your thoughts in the following comment area. You also can find more articles about electronic semiconductor through Google search engine, or refer to the following related articles.To Solve the Problems of Cloud Skyrocket--Edge ProcessingFPGAs Power Facial Recognition Technology Was Issued by NECNew Software for C2000 MCUs Eliminates the FPGA in industrial designsCustomisable Ethernet switch designed for embedded applicationsMouser signs Intel FPGA board firm ReFLEX CES

TroublesAs the deployment of Industrial IoT systems continues to proliferate,the streams of data transferred to the cloud skyrockets, drastically increasing the cost for cloud computing.  SolutionIn order to meet this trouble, many systems designers are adopting edge computing,in which data processing is done close to the source like sensors in a bid to reduce data transfer,storage and processing costs,plus address a few other concerns over Cloud Computing,in particular security. What is Big DataBig Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Huge datacentres are required if you want to store Big Data.Big Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Cloud Computing's advantages and disadvantagesCloud Computing has a lot of advantages including cost efficiency (i.e. no need to invest in and maintain your own hardware), scalability, resource availability (for all your users irrespective of their geographic locations), lower latency (as you can specify servers that are closest to the relevant users/customers) and peace of mind in terms of back-ups. There are,however,some disadvantages also. The biggest of which is that no provider can guarantee 100% availability. Data security and privacy are also causes for concern, both on the cloud and for data in transit. Latency can be an issue for Big Data, and doing computationally intensive tasks on the cloud will increase the cost. Of these concerns the last two, in particular, can be negated through edge processing; i.e. performing much of the computationally intensive work near the source data. Benefits here include real-time or near-real-time data processing and reduced network traffic, as you need only transfer the product of the edge processing, thus resulting in lower Cloud Computing costs. Security and privacy can be improved by keeping the sensitive data (a.k.a. Hot Data) within the edge processing environment and only sending less sensitive (Cold) data to the cloud. FPGAs have the edgeThere are technologies that can be used for edge processing applications. These include the use of traditional CPUs (scoring high in terms of flexibility), application-specific processors (e.g. GPUs) and ASICs/SoCs (scoring high on performance). However, it is FPGAs that are slotting into most edge processing applications. Why is this so? Well, let’s consider the requirements. Edge processing needs to be high-performance and in this respect an FPGA can perform several different tasks in parallel. For example, consider executing many non-dependent computations (such as A=B+C, D=E+F and G=H+I). On a CPU, these would have to be performed sequentially, with each sum requiring a few clock cycles. In an FPGA, an array of adders could do the computations in parallel, possibly requiring only a single clock cycle. Power efficiency is essential too, as the end product may well be battery-powered. With an FPGA the function (design) need be the only circuit present, whereas the architecture of a CPU or GPU may not be fully utilized. Also, with an FPGA comes the benefit of reprogrammability. Higher security is afforded too because the edge processing functions are hard wired into the FPGA. It is also possible to encrypt the transaction bus and to even go as far as designing your own processor. ConnectingA prime example of where edge processing is extremely useful, and in which FPGAs can play a significant role, is within an embedded system in which data derived from images needs to be transferred. For example, in the automotive sector Advanced Driver Assistance Systems (ADAS) are under development to make driving safer, easier and more comfortable, and ADAS is regarded as a significant step towards fully autonomous cars. The data processed by an ADAS can be used to notify the driver of problems or to automatically trigger responses such as deceleration, braking and/or the execution of a manoeuvre. The data can also be useful outside the vehicle. Let's discuss the embedded vision system first though by considering an ADAS demo unit that was built for this year's Embedded Vision show in Santa Clara, California. The demo comprised a TySOM-2-7Z100 prototyping board (see figure 1) which includes a Xilinx Zynq XC7Z100 device and a TySOM-FMC-ADAS daughter board to interface with four 960 x 540 pixel cameras. The processing was shared between a dual-core ARM Cortex-A9 processor and FPGA logic (both of which reside within the Zynq device) and began with frame grabbing images from the cameras and applying an edge detection algorithm (‘edge’ here in the sense of physical edges, such as objects, lane markings etc.). This is a computational-intensive task because of the pixel-level computations being applied (i.e. more than 2 million pixels). To perform this task on the ARM CPU a frame rate of only 3 per second could have been realised, whereas in the FPGA 27.5 fps was achieved.This picture is a TySOM-2-7Z100 prototyping board. Mixed technology (like CPU and FPGA) boards are proving very popular for edge processing applications and for connecting with the cloud.  The ARM CPU was mainly used for superimposing detected edges over the initial camera images, colour-space conversions, the formation of a composite image (see main image) and outputting it to an HD buffer. The FPGA and CPU could also work together to recognise and distinguish between obstacles and pedestrians close to the car and to provide lane departure warnings. What goes upSending the processed data to the cloud for further processing and/or storage is then a relatively simple task. Firstly, an AWS account would be created along with an AWS IoT environment. Next, we would configure a Thing (seeing as it is the IoT) and download the public and private keys needed for secure communications with the cloud.The embedded C MQTT standard would be the ideal Software Development Kit (SDK), because it is secure and requires minimal bandwidth. An application would then be prepared to run on the ARM CPU to publish the data onto the cloud. Imagine a scenario,howevber,under which we have data from thousands of vehicles going to the cloud.Analysis of the data could be performed on the cloud and made available for traffic systems or highway maintenance organisations, for example. There may also be instances where data from the cloud feeds into an edge-processing application, in which case applications are also available from AWS. All in all,there are both advantages and disadvantages associated with cloud computing. And many of the disadvantages will be overcome though edge-processing that FPGAs are a particularly suitable activity.  Article provided by Farhad Fallah,an Application Engineer with EDA company AldecArticle edited by Kynix