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FPGA is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It appears as a semi-custom circuit in the field of application specific integrated circuits (ASIC), which not only solves the shortcomings of the custom circuit, but also overcomes the limited number of gate circuits of the original programmable device. FPGA is often used in communication, network and other fields to process a large number of network data packets. It is also widely used in aerospace, military defense and other fields. As a hardware test platform before other chips are taped out, it plays an important role in cloud computing, artificial intelligence (AI) and other fields.
FPGA Applications, Features and Selection
| Ⅳ Vacuum Cleaner Based on FPGA |
FPGA consists of 6 parts, namely programmable input/output (I/O) unit, basic programmable logic unit, embedded RAM, abundant wiring resources, bottom embedded functional unit and embedded dedicated hard core.

Figure 1. FPGA Basic Architecture
Each unit is described as follows:
🔺Programmable I/O Unit
At present, most FPGA I/O units are designed in programmable mode, that is, through the flexible configuration of software, they can adapt to different electrical standards and I/O physical characteristics; the matching impedance characteristics, the pull-up and pull-down resistors can be adjusted; the output drive current can be adjusted, etc.
🔺Basic Programmable Logic Unit
The basic programmable logic unit of FPGA is composed of a look-up table (LUT) and a register. The look-up table completes the pure combinational logic function. FPGA internal registers can be configured as flip-flops with synchronous/asynchronous reset and set, clock enabled, or as latches. FPGA generally relies on registers to complete synchronous sequential logic design. Generally speaking, the configuration of a classic basic programmable unit is a register plus a LUT. However, the internal structures of registers and look-up tables of different manufacturers are different, so the combination modes are also different.
An important aspect of learning the LUT and Register ratios of the underlying hive is device selection and sizing. In addition to the basic programmable logic units inside the FPGA, there are embedded RAM, PLL or DLL, dedicated Hard IP Core, etc. These modules can also be equivalent to a certain scale of system gates, so the simple and scientific method is use the number of Registers or LUTs of the device to measure.
🔺Embedded RAM
Now most FPGAs have embedded RAM, which can be configured as single-port RAM, dual-port RAM, pseudo-dual-port RAM, CAM, FIFO and other storage structures.
CAM is the content address memory. The data written to the CAM is compared with every data stored in it and returns the addresses of all internal data that are the same as the port data. Simply put, RAM is a storage unit for writing addresses and reading data, while CAM is just the opposite of RAM. In addition to block RAM, Xilinx and Lattice FPGAs can flexibly configure LUTs into storage structures such as RAM, ROM, and FIFO.
🔺Rich Wiring Resources
The routing resources connect all the units in the FPGA, and the length and process of the connection determine the driving ability and transmission speed of the signal on the connection. Here the division of wiring resources:
1) Full dedicated routing resources: Complete the routing of the global clock and global reset/set within the device.
2) Long-term resources: Used to complete the wiring of some high-speed signals and some second global clock signals between device banks.
3) Short-circuit resources: Used to complete the logic interconnection and wiring between basic logic units.
4) Others: There are various wiring resources and control signal lines such as dedicated clock and reset in the logic unit.
In the design process, the place and router often automatically selects the available routing resources to connect the underlying unit modules used according to the topology and constraints of the input logic netlist, so routing resources are often ignored. In fact, the optimization of routing resources is directly related to the use and implementation results.
🔺The bottom layer is embedded with functional units, and the resources embedded by different manufacturers will be different.
🔺Embedded dedicated hard core
Different from the "low-level embedded unit", the hard cores here are mainly those with relatively weak generality, and not all FPGA devices contain hard cores.
1) Using FPGA to design ASIC circuit (application-specific integrated circuit), users can get suitable chips without film production.
2) FPGA can be used as a mid-scale sample for other full-custom or semi-custom ASIC circuits.
3) There are abundant triggers and I/O pins inside the FPGA.
4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk in the ASIC circuit.
5) FPGA adopts high-speed CMOS technology with low power consumption and is compatible with CMOS and TTL levels.

Figure 2. FPGA Chip
Connection logic and control logic are the areas where FPGA played a relatively important role in the early days and are also the cornerstone of FPGA applications. In fact, it is still quite difficult to apply FPGA in circuit design, which requires developers to have corresponding hardware knowledge (circuit knowledge) and software application capabilities (development tools). So talents in this area are always in short supply, and they are often engaged in new technologies. The successful product development of new products will become the mainstream basic products in the market for designers to apply. In the near future, the design of general-purpose and special-purpose IP will become popular.
Apply relatively mature technology to some specific fields such as communication, video, information processing, etc. to develop products that meet the needs of the industry and can be accepted by industry customers. This aspect is mainly a combination of FPGA and professional technology. In addition, there are product design for interface issues with professional customers also includes professional tool products and civilian products. The former focuses on performance, while the latter focuses on price-sensitive product design to achieve product functions as the main purpose.
FPGA is a means of realization. In this field, it has the characteristics of interface, control, functional IP, embedded CPU, etc. to realize a system product design with simple structure, high degree of curing, and comprehensive functions for FPGA market.
The system-level application is the combination of FPGA and traditional computer technology to realize an FPGA version of the computer system. For example, Xilinx V-4, V-5 series FPGA is used to realize the embedded POWER PC CPU, and then cooperate with various peripheral functions. To achieve a basic environment, running LINUX and other systems on this platform also supports various standard peripherals and functional interfaces, which is very helpful for quickly forming large-scale FPGA systems.
In system-level applications, if the developers do not have the ability to expand the system, it is meaningless to just engage in programming. Of course, the development of device drivers is another case. The system-level application seems to have a high starting point, but it does not have deep development ability, it is likely to become a hobbyist, just like many people can make web pages but cannot be called programming.
Design of indoor intelligent vacuuming platform based on FPGA.
Intelligent environmental cleaners have increasingly become the focus of research because they can replace people in environmental cleaning. Although they achieve intelligence, most of them have complex structures and high integration, which are not conducive to developers to expand their functions. On the basis of researching and summarizing the relatively mature products on the market, this paper designs and implements an indoor intelligent vacuuming platform based on a highly programmable FPGA. The platform has self-navigation, can clean most of the space, and is compact in shape, stable in operation and low in noise. More importantly, it has a simple structure and a user-friendly interface, which is convenient for further development of operation and functions.

Figure 3. Body Frame
The overall frame design of the platform proposed in this paper is shown in Figure 3, and a car with four wheels is used as the carrier of the entire platform. The FPGA controller is used as the main controller of the entire platform, and is connected to the photoelectric sensors jk1, jk2, jk3, jk4 and the collision switch jk5 through I/O to realize the detection of platform obstacles. Then output PWM waveform through I/O to drive speakers and high-low, and the change of the level drives the on and off of the LED to form an acousto-optic circuit. Finally the stepper motor dj1, dj2 and the DC dust collection motor dj3 are driven by controlling the signal control line of the motor driver to realize the movement and dust collection of the platform.
The system is mainly composed of FPGA main control chip, photoelectric sensor, collision switch, wireless remote control transmitter module controlled by two STC89C52 microcontrollers, two mode selection chips, acousto-optic circuit, drive motor, vacuum cleaner motor and the power supply circuit of the whole system, such as as shown in the Figure 4.

Figure 4. Main Control System
🔺FPGA Chip Selection
According to the overall design of the platform, the basic requirements for the chip can be drawn:
(1) At least 6 PWM waveform outputs are required.
(2) One serial communication interface is required.
(3) A real-time chip that requires a higher 12 V to be converted to 3.3 V.
(4) Higher processing speed.
(5) There are more I/O interfaces.
Taking these conditions into consideration, the EP2C35F672C6 model in the CycloneII series FPGA produced by Altera can basically meet the requirements. It has excellent operation speed, low cost and DSP module, large internal memory, multi-channel PWM output, flexible design and comprehensive use of multiple languages, and the cost performance is relatively high.
🔺Configuration Circuit Design Points
(1) Power supply circuit: The power supply system uses 12V power supply as the input power supply, uses L7805CV to step down it to 5V, and then converts 5V to 3.3V and 1.2V by TPS37HD301. The power supply point of the I/O port of the FPGA is 3.3V, the core supply voltage is 1.2V. Because the motor drive system uses the 5V signal of the controller, and the port voltage of the FPGA is 3.3V, the I/O voltage must be boosted to 5V, and the 74HCT245 boost chip is used here.
(2) Clock and reset circuit: ZPB-26-16 M is an active crystal oscillator in the clock circuit, and the frequency is 16MHz, which makes the serial port baud rate more accurate. At the same time, it can support the PPL function and ISP download function inside the chip. The reset circuit takes hardware reset and software reset.
(3) Debug JTAG and download circuit: Because the soft core ISP and JTAG can be built directly inside the FPGA, the hardware circuit is connected to a JTAG interface of IDC-10.
(4) Configuration storage circuit: EPCS16 is selected as the ROM of the FPGA, which can be repeatedly programmed by the download cable or other equipment, and can also be programmed online through the AS interface. Use the 4MHz On-Chip memory inside the FPGA chip as the RAM of the FPGA.
(5) Sensor and collision switch: E3F-DS5C4.P1R photoelectric switch, used to detect obstacles and stairs, which is a cylindrical diffusion type with a maximum distance of 5cm, or an adjustable NPN type normally open photoelectric switch. The collision switch mainly cooperates with the front sensor to protect the front of the platform. When the platform hits the obstacle ahead, trigger the switch to make the platform avoid the obstacle.
(6) Wireless sending and receiving module: XL02-232AP1 wireless module is a half-duplex wireless transmission module with UART interface, which can work in the 433MHz public frequency band and meet the wireless regulatory requirements.
(7) Drive and vacuum motor: The platform adopts the front wheel dual drive, the motor selects the two-phase hybrid stepping type, and the vacuum cleaner motor adopts the DC motor. The main electrical parameters of the stepping motor are:
① Step angle: 1.8°
② Phase current: 0.87 A
③ Holding torque: 0.24 nm
④ Phase resistance: 3.3 Ω
⑤ Phase inductance: 5.0 mH
⑥ Weight: 0.2 kg
(8) Sound and light circuit and automatic cleaning time input display circuit: The sound and light circuit is mainly composed of light-emitting diodes and buzzers, which are directly connected to the FPGA to remind the working state of the platform. Use 4 buttons (OK, Initial, Up, Down) to input the cleaning time, and then three digital tubes display the set time. The cleaning time is counted by the timer inside the FPGA. When the timer is completed, the platform stops working.
Divide the program into two parts: hardware programming and software programming. For hardware programming, timing simulation of hardware circuits is required to determine the effect of debugging.
🔺Hardware Programming and Simulation
The platform mainly generates input signals through sensors and collision switches, and processes the signals through FPGA. Finally, the FPGA transmits the processed signals to the motor, and the motor completes a series of actions, as shown in Table 1. So its logic design is the key to realize intelligence. After the hardware selection is completed, use Quartus II to build the hardware schematic diagram. After compiling, perform timing simulation on jk1, jk2, jk3, and jk4, analyze the timing relationship, estimate the performance of the design, and check and eliminate competition risks.
Table 1: Relationship between Motor Status and Platform Working Status.
|
dj1 |
dj2 |
dj3 |
Cleaner Status |
|
Turn Forward |
Turn Forward |
ON |
Vacuuming Forward |
|
Turn Back |
Turn Forward |
ON |
Vacuuming Left |
|
Turn Forward |
Turn Back |
ON |
Vacuuming Right |
|
Turn Back |
Turn Back |
ON |
Vacuuming Back |
The realization of platform work in automatic cleaning mode depends on the cooperative work of sensors (jk1, jk2, jk3, jk4) and motors (dj1, dj2, dj3), and the logical relationship is designed according to their functions.
Table 2: Relationship between Sensor Status and Platform Working Status.
|
jk1 |
jk2 |
jk3 |
jk4 |
Cleaner Status |
|
1 |
1 |
1 |
1 |
Vacuuming Forward |
|
1 |
1 |
0 |
1 |
Vacuuming Left |
|
1 |
0 |
1 |
1 |
Vacuuming Right |
|
1 |
0 |
0 |
1 |
Vacuuming Forward |
|
0 |
1 |
0 |
1 |
Vacuuming Forward (Turn 90° Left) |
|
0 |
0 |
1 |
1 |
Vacuuming Forward (Turn 90° Right) |
|
0 |
0 |
0 |
1 |
Vacuuming Back |
When the hardware selection is completed, use Quartus II to build the hardware schematic diagram. After compiling, perform timing simulation on jk1, jk2, jk3, and jk4 to analyze the timing relationship.
🔺Software Programming
After the hardware design and debugging is completed, the software system design is also carried out. Write a C program in a C language file to program the SoPC. The overall algorithm flow of the platform work is shown in Figure 5. When the platform is powered on, firstly enter the automatic cleaning and manual remote cleaning mode. After the automatic cleaning mode is selected, input the working time of the platform's automatic cleaning through the keyboard, and use the sensor to judge whether it encounters obstacles or stairs during the cleaning process. Through the interrupt, check whether the set time is reached at all times. If not, the program will return to running. However, if the set time is up, the program will end and the platform will stop working. When remote cleaning is selected, platform movement is controlled by the operator.

Figure 5. Algorithm Flowchart
Through hardware selection, construction and debugging, and software language writing and debugging, a simple platform has been successfully made, and various predetermined functions have been realized. Compared with similar products on the market, its structure is simpler, the cost is lower, the flexibility and scalability are stronger, and it provides a hardware-supported platform for researchers to develop more functions, which has practical value. As microprocessors continue to advance and sensing technology evolves, their performance can continue to improve and costs can continue to decline. However, in the process of simulation and implementation, it is found that its specific process algorithm is not rigorous enough, and it is necessary to continue to improve it in the future.
1. What is FPGA architecture?
The field-programmable gate array (FPGA) is an integrated circuit that consists of internal hardware blocks with user-programmable interconnects to customize operation for a specific application.
2. What are the parts of an FPGA?
Structure of an FPGA
Configurable Logic Block (CLB)
Digital Signal Processing (DSP) Slice.
Transceivers.
Block Random Access Memory (BRAM)
Input/Output (IO) Blocks.
3. What is a basic unit of an FPGA?
The configurable logic blocks (CLBs) are the basic logic unit of an FPGA. Sometimes referred to as slices or logic cells, CLBs are made up of two basic components: flip-flops and lookup tables (LUTs).
4. What is FPGA and its types?
FPGA stands for Field Programmable Gate Array which is an IC that can be programmed to perform a customized operation for a specific application. They have thousands of gates. In the field of VLSI FPGAs have been very popular.
5. What is the function of FPGA?
FPGAs are mainly used to design application-specific integrated circuits (ASICs). First, you design the architecture of such a circuit. Then, you use an FPGA to build and check its prototype. Errors can be corrected.
6. What is FPGA and its application?
The FPGA is Field Programmable Gate Array. It is a type of device that is widely used in electronic circuits. FPGAs are semiconductor devices which contain programmable logic blocks and interconnection circuits. It can be programmed or reprogrammed to the required functionality after manufacturing.
7. What are the advantages of FPGA?
FPGA advantages
Long-term availability.
Updating and adaptation at the customer.
Very short time-to-market.
Fast and efficient systems.
Acceleration of software.
Real-time applications.
Massively parallel data processing.
8. What is inside CLB in FPGA?
A configurable logic block (CLB) is the basic repeating logic resource on an FPGA. When linked together by routing resources, the components in CLBs execute complex logic functions, implement memory functions, and synchronize code on the FPGA.
9. What are the main applications of FPGAs?
Main FPGA applications are: Medical, video & image processing, telecom & datacom, server & cloud and defense and space. FPGA chips are used in both wired and wireless communications.
10. What are the industrial applications of FPGA boards?
Such applications include multiple sensor dome cameras, HD (High Definition) cameras, night-vision cameras, etc. FPGAs provide the differentiation factor and the processing power to implement such complex solutions.
11. What are the applications of CPLDs and FPGAs?
Applications of CPLD
CPLDs can be used as bootloaders for FPGAs and other programmable systems. CPLDs are often used as address decoders and custom state machines in digital systems. Due to their small size and low power consumption, CPLDs are ideal for use in portable and handheld digital devices.
12. What programmable technology is used in a FPGA devices?
FPGA emerged from relatively simpler technologies such as programmable read-only memory (PROM) and programmable logic devices (PLDs) like PAL, PLA, or Complex PLD (CPLD). It consists of three main parts: Configurable Logic Blocks — which implement logic functions. Programmable Interconnects — which implement routing.
13. What are the features of FPGA?
The basic features of FPGA are: 1) FPGA design ASIC circuit, the user does not need to chip production, you can get a combination of chips. - 2) FPGA can do all other custom or semi-custom ASIC circuit of the sample sample. 3) FPGA has a rich internal trigger and I / O pin.
14. Is a FPGA a computer?
An FPGA is a chip consisting of a series of logic blocks which can be modified and configured by the user. ... FPGA are programmable chips and their functionality can be updated multiple times. FPGAs come in array of size and prices and are most likely used in low-mid size volume products.
Ivy is a seasoned writer with over 6 years of experience in the semiconductor electronics industry. She possesses a wealth of knowledge in the field, coupled with cutting-edge creative concepts. Ivy is a distinguished author with unique insights and a remarkable writing style.
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