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Ⅰ IntroductionWith the improvement of computer technology, the demand for non-volatile memory is increasing, their read and write speed requirements are getting faster and faster, and the power consumption  are becoming smaller and smaller as required by users. But the traditional non-volatile memory such as EEPROM , FLASH, etc. have been difficult to meet these needs.Traditional mainstream semiconductor memories can be divided into two categories: volatile and nonvolatile. Volatile memory includes static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM lose their saved data when power off. Although RAM is easy to use and performs well, a big disadvantage of it is data loss.Non-volatile memory does not lose stored data in the case of a power failure, because all mainstream non-volatile memories are derived from read-only memory (ROM) technology. ROM, what is called a read-only memory is definitely not easy to write, in fact, it cannot be written at all. All memories developed by ROM technology are difficult to write data, including EPROM, EEPROM and Flash. And these memories not only have a slow writing speed, but also can only be erased and written in a limited number of times.Based on improving semiconductor technologies, ferroelectric memory, a new type of memories, has some unique characteristics. Ferroelectric memory is compatible with all the functions of RAM, and it is a non-volatile memory like a ROM. In other words, ferroelectric memory bridges the gap between these two types of storage, a type of non-volatile RAM. Compared with traditional non-volatile memory, it has attracted much attention due to its advantages such as low power consumption, fast read and write speed, and strong anti-irradiation capability. CatalogⅠ IntroductionⅡ TerminologyⅢ Working PrincipleⅣ FRAM Material FeaturesⅤ Circuit StructureⅥ Reading and Writing ProcessⅦ FRAM StructureⅧ Comparison of FRAM with Other Storage TechnologiesⅨ FRAM UsageⅩ SummaryⅪ One Question Related to FRAM and Going Further11.1 Question11.2 AnswerⅡ TerminologyFerroelectric Memory (FeRAM)Ferroelectric memory (FRAM), also known as F-RAM or FeRAM, is a type of random access memory with fast read and write speed, and the ability to retain data after power is turned off (such as read-only memory and flash memory) is combined, which is the most commonly used type of personal computer memory. Since it is not as dense as dynamic random access memory (DRAM) and static random access memory (SRAM), that is, it cannot store as much data as they do in the same space. In other words, it cannot replace DRAM and SRAM technologies. However, because it can store data quickly with very low power conditions, it is widely used in consumer’s small devices, such as personal digital assistants (PDA), mobile phones, power meters, smart cards, and security systems. FRAM’s read and write speed is faster than flash memory. In some applications, it may also replace electrically erasable read-only memory (EEPROM) and static random access memory (SRAM), and will become a key component of future wireless products. Ⅲ Working PrincipleFeRAM or ferroelectric RAM seems to indicate that an iron element exists within the memory this is not actually the case. A ferroelectric is a material containing a crystal that can spontaneously polarize. It has two states that can be reversed by an external electric field. When an electric field is applied to the ferroelectric crystal, the central atom moves in the crystal following the electric field direction. When an atom moving, it passes through an energy barrier, causing charge breakdown. Internal circuits react to the charge breakdown and set the memory. After the electric field is removed, the central atom remains polarization state, which makes the materials non-volatile, so the state of the memory is preserved. Because there is no atomic collision in the entire physical process, the ferroelectric memory has the characteristics of high read and write speed, ultra-low power consumption, and unlimited writes, making it very suitable to act as temporary storage memory in important systems to transfer various data between subsystems, for each subsystem to read and write frequently.Therefore, with an external electric field, the polarization characteristics of ferroelectric materials will change. When this electric field is removed, the data can still be saved. Without an external electric field, there are two stable states of polarization characteristics. Figure 1 is a hysteresis loop of a ferroelectric material capacitor, showing the different polarities of the ferroelectric capacitor under different applied electric fields. Among them, the two most important parameters are the degree of residual polarization Pr, and the coercive field Ec. In the absence of electric field effect, +/- Pr represents two states of “0” and “1”. To obtain these two states, the applied electric field must be greater than +/- Ec, at this time, the required threshold voltage is also determined.Figure 1. Ferroelectric Hysteresis LoopThe industry explores the use of ferroelectric materials for DRAM: using them as dielectric materials in DRAM capacitors. That is, ferroelectrics are used to replace high-K dielectric materials in standard logic devices, and finally non-volatile transistors are formed, which are FeFETs. The two stable polarization states of the ferroelectric gate oxide change the threshold voltage of the transistor, even when the supply voltage is removed. Therefore, the binary state is encoded in the threshold voltage of the transistor. The writing operation of the memory cell can be completed by applying a pulse on the gate of the transistor, which will change the polarization state of the ferroelectric material and affect the threshold voltage. For example, applying a positive pulse will reduce the threshold voltage, making the transistor in the “on” state. Reading is done by measuring the drain current. This memory mode is similar to the operating mode of a NAND flash: electrons are injected and drawn out of the floating gate, which adjusting the threshold voltage of the transistor.In contrast, the leakage current factor of ferroelectric capacitors is not as important as traditional non-volatile memories such as EEPROM and FLASH, because the information storage of FeRAM is realized by polarization, not free electrons. Ⅳ FRAM Material FeaturesIdeal ferroelectric materials need to meet the following characteristics:Small dielectric constantReasonable self-polarization degree (~ 5μC/ cm2)High Curie temperature (outside the storage and operating temperature range of the device)The thickness of ferroelectric materials should be thin (submicron) to make the coercive field EC smaller. Ferroelectric materials should stand a certain breakdown filed strength.Internal switching speed should be fast (nanosecond level)The ability to keep the data and the long-lasting ability will be good.If used by the military, it is also required to be able to resist radiation exposure. Good chemical stabilityGood processing uniformityEasy to integrate into CMOS processNo bad effect on the surrounding circuitsSmall pollution After years of research and development, there are currently two main types of mainstream ferroelectric materials: PZT and SBT.PZT is lead zirconate titanate PbZrxTil-xO3; SBT is strontium bismuth tantalate Sr1-yBi2 + xTa2O9. The structure of these two materials is shown in Figure 2. Figure 2. Schematic Diagram of PZT and SBT Material StructurePZT is the most studied and widely used. Its advantage is that it can be made at lower temperatures by sputtering and MOCVD. It has the advantages of large residual polarization, cheap raw materials, and low crystallization temperature.; its disadvantages are fatigue degradation problems, and lead pollution to the environment. Moreover, the film deposition process of these materials has proved to be very challenging. At the same time, the extremely high dielectric constant (about 300) of these materials is a big obstacle to their integration into transistors.In addition, scientists have discovered the presence of a ferroelectric phase in a less complex material, hafnium oxide (HfO2), which raise a new concept of storage concept. The researchers found that the ferroelectric phase) can be stabilized by doping silicon (Si) into HfO2. Compared with PZT, HfO2 has a lower dielectric constant and can deposit thin films in a conformal manner (ie, the atomic layer deposition (ALD) process). Most importantly, scientists are familiar with HfO2, because it is the HK gate oxide material in the logic device HKMG. By modifying this CMOS-compatible material, logic transistors can become non-volatile FeFET memory transistors.Functional verification of FeFETs has been implemented in a two-dimensional planar architecture. At the same time, the HfO2 conformal deposition process makes 3D stacking possible, for example, depositing ferroelectric materials on vertical “walls’ to stack transistors in a vertical direction.In terms of materials, 3D FeFETs can solve some of the challenges brought by 2D FeFET structures. One challenge is related to the polycrystalline nature of the HfO2. Scaling the thickness of the HfO2 film will significantly reduce the number of grains in this layer. Because not all the crystal grains have the same polarization direction, the reduction of crystal grains will affect the consistency of the transistor’s response to the external electric field, and eventually lead to large differences between the tubes. By 3D stacking, this drawback is overcome in physical filed. That is, HfO2 does not need to be compressed too thinly, thereby reducing tube-to-tube variation.These vertical FeFETs are expected to have more advantages than complex 3D NAND flash memory, including simple process, lower power consumption and faster speed. Compared to 3D NAND flash memory, vertical FeFET can be programmed at a lower voltage, which improves memory reliability and scalability.The biggest advantage of SBT is that it does not have the problem of fatigue degradation, and it does not contain lead, which meets EU environmental standards; however, its disadvantages are that the process temperature is higher, which makes the process integration difficult, and the degree of residual polarization is small. The comparison of the two materials is shown in Table 1.Table 1. Comparison between PZT and SBT  PZTSBTStructureABO3Layered structureDeposition technologySol-gel,MOCVDSol-gel,MOCVDProcess temperature450℃~700℃750℃~850℃Residual polarity3012Fatigue10101010Data hold85℃@10a- At present, from the perspective of environmental protection, PZT has been banned, but from the perspective of performance and process integration of ferroelectric memory and cost, SBT has no advantages compared to PZT. Therefore, the selection of ferroelectric materials is worth discussing. Ⅴ Circuit StructureThe circuit structure of the ferroelectric memory is mainly divided into the following three types: 2 transistors-2 capacitors (2T2C), 1 transistor-2 capacitors (1T2C), 1 transistor-1 capacitor (1T1C), as shown in Figure 3. The 2T2C structure has two opposite capacitors for each bit as a reference to each other, so the reliability is better, but occupies too much space, which is not suitable for high-density applications. The transistor / single capacitor structure can be used like a DRAM to provide a reference for each column of the memory array, compared with the existing 2T2C structure, they effectively reduce the required space of the memory cell by half. This design greatly improves the efficiency of ferroelectric memory and reduces the production cost of ferroelectric memory products. The 1T1C structure has a higher integration density (8F2), but its reliability is poor. And the 1T2C structure is a compromise between these two structures. Figure 3. Three FRAM StructuresAt present, in order to obtain a high-density memory, 1T1C structure is mostly used (as shown in Figure 4). In addition, a chain structure is also adopted, thus Chain FeRAM is made. This structure is similar to the NAND structure. Through this method, a higher storage density than 1T1C can be obtained, but this method will also greatly increase the access time. Chain FeRAM (CFeRAM) structure is shown in Figure 5. Figure 4. 1T1C Layout Figure 5. Chain FeRAM (CFeRAM) Circuit StructureⅥ Reading and Writing ProcessAccording to the polarity of the electronic memory cell, a small charge amount is “0” and a large charge amount is “1”. This charge is converted into a reading voltage, which is “0” when it is less than the reference voltage and when it is greater than the reference voltage represents “1”. The stored information is read out as shown in Figure 6. Figure 6. Reading and Writing Process of FRAMDuring the reading process, the word line voltage is increased to turn on the MOS transistor, and then the drive line voltage is increased as VCC, so that different charges of the storage capacitor are distributed to the bit line parasitic capacitance, so different voltages appear on the BL to identify the data. During a writing process, the word line is raised to turn on the MOS transistor, and a pulse is applied to the drive line, so that different data on the bit line are stored in two different steady states of the ferroelectric capacitor.By adding a positive voltage or a negative voltage, these two voltages can make the capacitor into two different polarities. In this way, the information is written into the memory. Ⅶ FRAM StructureAt present, the most common device structures of ferroelectric memories are planar and stack structures. The difference between the two is the location of the dry ferroelectric capacitor and the way in which the capacitor is connected to the MOS tube. In the planar structure, the capacitor is placed above the field oxide, and the electrode of the capacitor is connected to the active area of the MOS tube through metal aluminum. The process is relatively simple, but the unit spacing is large. In the stack structure, the capacitor is placed in the source region, the lower electrode of the capacitor is connected to the source terminal of the MOS tube through a plug based on CMP process, which has a high integration density. In addition, the stack structure can adopt the method of making ferroelectric capacitors on metal wires, thereby reducing the mutual influence during the formation process. The following schematic diagrams of the two structures are shown in Figure 7 and Figure 8. Figure 7. Planar Structure Figure 8. Stack StructureThe process of the planar structure is relatively simple. The isolation uses the LOCOS structure, and the planarization does not require the CMP. The stacked structure has a high degree of integration based on advanced technique, and STI is used for isolation, in addition, CMP is required for planarization, and copper wires can be used.In addition, there is a structure that uses a ferroelectric material as the gate. Such a device can eliminate the destructive problem of data readout, and theoretically it is more space-saving and can make more greater integration. However, there are still serious problems with this structure, that is, the data storage capacity is very poor, only one month or less, so it is far from practical. Figure 9 is a schematic diagram of such a structure. Figure 9. FeFET Structure DiagramAt present, the ferroelectric memory generally adopts a planar structure with the line width more than 0.5 μm, and generally uses a stack structure when the line width is less than 0.5 μm. Ⅷ Comparison of FRAM with Other Storage TechnologiesAt present, Ramtron’s FRAM mainly includes two categories: serial FRAM and parallel FRAM. Among them, serial FRAM is divided into I2C two-line FM24×× series and SPI three-line FM25xx series. Serial FRAM is compatible with the traditional 24xx and 25xx E2PROM pins and timing, which can be directly replaced.FRAM products have the advantages of RAM and ROM, and fast read and write speed, in addition, they can be used as non-volatile memory. Due to the shortcoming of ferroelectric crystals, the number of accesses is limited, beyond which FRAM is no longer non-volatile. The maximum access times given is 10 billion, but it not means FRAM will be scrapped when over this upper limit. In the terms of it, FRAM is not non-volatile, but it can still be used as an ordinary RAM.FRAM vs E2PROMFRAM can be used as a second option for E2PROM. Except the performance of E2PROM, the FRAM access speed is much faster. When using FRAM, it must be determined that once there are 10 billion accesses is down to FRAM in the system, there is no damage.FRAM vs SRAMIn terms of speed, price, and convenience, SRAM is better than FRAM; but from the perspective of the entire design, FRAM has certain advantages. Non-volatile FRAM can hold startup programs and configuration information. If the maximum access speed of all the memories in the application is 70ns, one piece of FRAM can be used to complete the system, making the system structure more simpler.FRAM vs DRAMDRAM is suitable for applications where density and price are more important than access speed. For example, DRAM is the best choice for graphics display memory. There are a large number of pixels to be stored, and the recovery time is not very important. If you don’t need to save the last content at the next boot, use volatile DRAM memory. The role and cost of DRAM are reasonable compared with FRAM. In short, it turns out that DRAM cannot be replaced by FRAM totally.FRAM vs FlashAt present, the most commonly used program memory is Flash, which is more convenient and cheaper to use. The program memory must be non-volatile, and easier to rewrite, but the use of FRAM is limited by access times.Ⅸ FRAM UsageData collection and recordingFeRAM allows designers to write data faster and more frequently, and at a lower price than EEPROM.Typical applications: meters (electric meters, gas meters, water meters, flow meters), RF/ID instruments, car black boxes, air bags, GPS, power grid monitoring systems, and so on. Parameter setting and storageFeRAM helps designers solve the problem of data loss due to sudden power failure by storing data in real time. Parameter storage in the FeRAM is used to track the changes of the system in the past time. Its purpose includes restoring the system state or confirming a system error when the power is on.Typical applications: photocopiers, printers, industrial controls, set-top boxes, network equipment  and large household appliances. Non-volatile bufferFeRAM can quickly store data before it is stored in other memory, so that the data in the buffer will not be lost when having power failure.Typical applications: industrial systems, ATM teller machines, tax control machines, commercial settlement systems (POS), fax machines, non-volatile cache memory in hard disk, etc. Ⅹ SummaryFerroelectric memory is an emerging non-volatile memory. It started early and realized industrialization. Because of its advantages such as low power consumption, fast read and write speed, and strong anti-irradiation capabilities, there is a market for small-scale storage areas with low power consumption and radiation resistance. Having the characteristic of anti-radiation, in the case of electromagnetic waves or radiation, the data is still safe, so it has important applications in space science, medicine and other specific fields. However, the ferroelectric memory also has the disadvantages that it is difficult to improve the integration, the process is more contaminated, and it is difficult to be compatible with the CMOS technique. So that it needs further research and solution. Ⅺ One Question Related to FRAM and Going Further11.1 QuestionWhat is FRAM used for?11.2 AnswerFerroelectric RAM is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. It is one of a growing number of alternative non-volatile random-access memory technologies that offer the same functionality as flash memory. FRAM can be used in many fields, for example, with ultra-low power consumption, it is very suitable for intelligent water meters, gas meters and so on. Frequently Asked Questions about Ferroelectric RAM1. What is FRAM memory?Ferroelectric RAM (FeRAM, F-RAM or FRAM) is a random-access memory similar in construction to DRAM but using a ferroelectric layer instead of a dielectric layer to achieve non-volatility. 2. What is ferroelectric effect?Ferroelectricity is a characteristic of certain materials that have a spontaneous electric polarization that can be reversed by the application of an external electric field. ... Thus, the prefix ferro, meaning iron, was used to describe the property despite the fact that most ferroelectric materials do not contain iron. 3. How does FRAM work?FRAM is a nonvolatile storage memory that retains its data even after the power is turned off. However, similar to commonly used DRAM (Dynamic Random Access Memory) found in personal computers, workstations, and non-handheld game-consoles, FRAM requires a memory restore after each read. 4. What are the unique characteristics of FRAM?FRAM has the characteristics of both ROM (Read Only Memory) and RAM (Random Access Memory), and features faster write, great read/write cycle endurance, and low power consumption. 5. Which enables the read and write operation in Feram?Write Operation in Ferroelectric Random Access Memory (FRAM)Similar to read operation, a pre-charge operation follows a write access. The circuit applies 'write' data to the Ferroelectric capacitors. If necessary, the new data simply switches the state of the ferroelectric crystals.

Catalog Introduction Design Flow of Chip Design Specification Development Design Details of the Chip Draw a Blueprint for the Plane About Wafer What Is a Wafer How to Make Single Crystal Wafer Metallurgical Purification Pulling the Crystal Design Flow of Chip Manufacture What Is an IC Chip Metal Sputtering Coating Photoresistance Etching Technology Photoresist Removal Nano-Process What Is the Nano-Process How Tiny Is the Nanometer Purpose of Reducing the Process Physical Limitations of Downsizing About Encapsulation Two Common Packages DIP Package BGA Package Two Ways to Reduce Size SoC SiP Introduction A chip is a silicon chip that contains an integrated circuit, so the chip is also called an integrated circuit. It may be only 2.5 centimeters in square size, but it contains tens of millions of transistors. Simpler processors, on the other hand, may have thousands of transistors engraved on chips which are a few millimeters in size. Chip is the most important part of electronic equipment, which undertakes the function of operation and storage. Design Flow of Chip The birth of a chip can be divided into two parts: design and manufacture. First, let's take a look at the complex and tedious chip design process. Fig 1. The process of making a chip is like building a house with Lego. First, the wafer is used as the foundation and the necessary IC chips can be produced after layers are stacked on top of each other. However, there is no use in having no amount of manufacturing capacity without a design drawing. Therefore, the role of an architect is very important. But who is the architect in IC's design? The next step is to introduce the IC design. In the IC production process, IC is mostly planned and designed by professional IC design companies, such as MediaTek, Qualcomm, Intel and other well-known large factories, all of which design their own IC chips to provide different specifications and efficiency chips for downstream manufacturers to choose from. Because IC is designed by the factories themselves, so IC design depends very much on the technology of engineers and the quality of engineers affects the value of an enterprise. But what are the steps engineers take to design an IC chip? The design process can be simply divided into the following steps. Design Specification Development In IC design, the most important step is specification development. This step is like deciding how many rooms, bathrooms, what building codes to comply with, and designing after all the features have been identified so that no additional time is spent on subsequent modifications. The IC design needs to go through similar steps to ensure that the chip is designed without any errors. The first step in specification development is to determine the purpose and effectiveness of IC and to set the general direction. The next step is to see what protocols to comply with, such as the wireless card chip needs to comply with IEEE 802.11 and other specifications. Otherwise, the chip will not be compatible with the products on the market, so that it will not be able to connect to other devices. Finally, the implementation method of this IC is established, different functions are allocated into different units, and the method of connecting different units is established, so that the specification can be completed. Design Details of the Chip After designing the specifications, it is followed by the details of the design chip. This step is like making a preliminary note of the planning of the building and depicting the overall outline for subsequent drawing. In IC chip, the hardware description language (HDL) is used to describe the circuit. The commonly used HDLs are Verilog, VHDL, and so on, which can easily express the function of a IC by code. This is followed by checking the correctness of the program's functionality and continuously modifying it until it meets the desired functionality. Fig 2. Verilog Example of 32 Bits Adder Draw a Blueprint for the Plane With a complete plan, the next step is to draw a blueprint for the plane. In IC design, the step of logic synthesis is to put the unmistakable HDL code into the electronic design automation tool (EDA tool), to let the computer convert HDL code into logic circuit, resulting in the following circuit diagram. After that, it is repeatedly determined whether the logic gate design conforms to the specification and is modified until the function is correct. Fig 3. The Result of the Synthesis of the Control Unit Finally, the synthesized code is put into another set of EDA tool for circuit layout and winding (Place And Route). After continuous detection, the following circuit diagram will be formed. You can see blue, red, green, yellow and other different colors, each of which represents a mask. As for the use of the mask, how should it be used? Fig 4. The Commonly Used Calculus Chip-FFT Chip, Which Completes the Circuit Layout and the Winding Result ——The chip is stacked by layers of masks. First of all, it is now known that an IC will produce multiple masks. These masks have the difference between the upper and lower layers and each layer has its own task. The following figure is a simple mask example. Taking the most basic element CMOS in the integrated circuit as an example, the full name of CMOS is complementary metal oxide semiconductor. That is, the combination of NMOS and PMOS to form CMOS. As for what is a metal oxide semiconductor (MOS)? This kind of component which is widely used in the chip is more difficult to explain, and it is more difficult for the general reader to figure it out, so there is no more detailed study here. In the following figure, on the left is the circuit diagram formed after the circuit layout and winding, and you have already known that each color represents a mask. On the right is the way each mask is spread out. Production is to start from the bottom, in accordance with the method proposed in the manufacture of the IC chip, layer by layer, and finally the desired chip will be produced. Fig 5.  At this point, you should have a preliminary understanding of the IC design. The overall view is very clear that IC design is a very complex major, but also thanks to the maturity of computer-aided software, so that IC design can be accelerated. The IC design relies heavily on the wisdom of engineers, and each of the steps described here has its own expertise and can be separated into multiple professional courses. For example, writing a hardware description language does not simply require familiarity with the programming language. You also need to understand how logic circuits work, how to convert the required algorithms into programs, and how synthetic software converts programs into logic gates. What Is a Wafer? In semiconductor news, it is always mentioned in the size of the wafer, such as 8-inch or 12-inch wafer. But what is the so-called wafer? What part of it is 8 inches? What is the difficulty of producing large wafers? Here is a step-by-step introduction to the most important foundation of semiconductors-what is a "wafer". Wafer is the basis for making all kinds of computer chips. We can compare chip manufacturing to building a house with Lego blocks and building the shape we want (that is, all kinds of chips) by stacking one layer after another. However, if there is no good foundation, the built house will be tilted back and forth, contrary to our wishes. In order to make the perfect house, we need a smooth substrate. For chip manufacturing, this substrate is the wafer that will be described next. First of all, think back to when you were a child playing with Lego blocks, there would be a small round bulge on the surface of the building blocks. With this structure, we can stack the two blocks firmly together without using glue. Chip manufacturing, also in a way like this, binds subsequent atoms to the substrate. Therefore, we need to find a substrate with a neat surface in order to meet the conditions needed for subsequent manufacturing. Fig 6. In solid materials, there is a special crystal structure. That is, single crystal (Monocrystalline). It has the characteristics of atoms one after another closely arranged together, which can form a flat atomic surface. Therefore, using single crystal to make wafer can meet the above needs. However, how to produce such a material? There are two main steps, respectively, purification and crystal pulling. After this, such a material can be completed. How to Make Single Crystal Wafer? Metallurgical Purification The purification is divided into two stages. The first step is metallurgical purification. During this process, we add carbon and convert silicon oxide into silicon with a purity of more than 98% in a redox manner. Most metals, such as iron or copper, are refined in this way to obtain sufficient purity of metal. However, 98% is still not enough for chip manufacturing and still needs to be further improved. Therefore, Siemens process will be used for purification, so that the high purity polysilicon needed for semiconductor process will be obtained. Fig 7. Silicon Column Manufacturing Process Pulling the Crystal Then there is the step of pulling the crystal. First, the high purity polysilicon obtained earlier is melted to form liquid silicon. After that, the single crystal silicon seed is in contact with the liquid surface and slowly pulls up as it rotates. As for why single crystal silicon is needed, that is because silicon atoms are arranged in the same way as people queue up. They will need to arrange the head so that later people can arrange it correctly. And silicon seed is an important row head, so that the later atoms know how to queue up. Finally, after the silicon atoms leaving the liquid surface solidify, the neatly arranged single crystal silicon columns are completed. Fig 8. Single Crystal Silicon Column But what do 8 inches and 12 inches stand for? It refers to the diameter of thin wafers being treated and sliced into，which is from the surface of the part of a crystal column that looks like a pencil rod. What is the difficulty of making large wafers? As mentioned earlier, the crystal column is made as if it were making marshmallows, rotating and forming at the same time. If you have made marshmallows, you should know that it is very difficult to make large and solid marshmallows, and the same is true of the crystal pulling process. The speed of rotation and the control of temperature will affect the quality of the crystal column. As a result, the larger the size, the higher the speed and temperature requirements are, so it is more difficult to make high-quality 12-inch wafers than 8-inch wafers. However, a whole silicon column cannot be made into a chip-making substrate. In order to produce a silicon wafer, the silicon column needs to be cut transversely into a wafer with a diamond knife, and the wafer can be polished to form the silicon wafer needed for chip manufacturing. After so many steps, the fabrication of the chip substrate is complete, and the next step is to stack the house, that is, chip manufacturing. So, how to make a chip? Manufacture ——Stacked chips After introducing what silicon wafers are, you also know that making IC chips is like building a house with Lego blocks, creating the shape you want by stacking layer after layer. However, there are quite a few steps to build a house, and so is IC manufacturing. What are the steps to make IC? Next, the process of IC chip manufacturing will be introduced. What Is an IC Chip? Before we begin, we need to know what an IC chip is. IC, which means integrated circuit (Integrated Circuit), is the design of the circuit that is in the form of stacking together. In this way, we can reduce the area required to connect the circuit. The following figure is a 3D diagram of the IC circuit, from which you can see that its structure is like the beams and columns of a house. It is done layer by layer and this is the reason why IC manufacturing is compared to building a house. Fig 9. 3D Profile of IC Chip From the 3D profile of the IC chip in the image above, the dark blue part at the bottom is the wafer introduced in the previous step. From this picture, we can see more clearly how important the wafer substrate plays in the chip. As for the red and khaki parts, they are the places to be completed when IC is made. First of all, the red part can be compared to the hall on the first floor of the building. The hall on the first floor is the door of a house because everyone and everything come in and out of here. It has more functionality under the control of traffic. Therefore, compared with other floors, the construction will be more complex and requires more steps. In IC circuit, this hall is the logic gate layer; it is the most important part of the whole IC by combining a variety of logic gates together and completes the fully functional IC chip. The yellow part is like a normal floor. Compared with the first floor, there will not be much complex structure, and each floor will not change much when it is built. The purpose of this layer is to connect the logic gates of the red part. The reason why so many layers are needed is that there are so many lines to be connected that a single layer cannot hold all the lines. So it is necessary to stack a few more layers to achieve this goal. Among them, the lines of different layers will be connected up and down to meet the needs of the wiring. ——Layered construction, layer by layer architecture Once you know the construction of IC, let's show you how to make it. Imagine that if we want to make a fine drawing with a paint spray tank, we need to cut out the cover plate of the figure and cover it on paper. Then spray the paint evenly on the paper and remove the mask when the paint is dry. After repeating this step over and over again, you can complete neat and complex graphics. IC is made in a similar way, by covering up a layer of stacking. Fig 10.  When making IC, you can simply divide into the above four steps. Although the actual manufacturing steps will be different and the materials used will be different, but generally using a similar principle. This process is slightly different from painting: IC manufacturing is to paint first and then cover while painting is to cover and then paint. And the processes are described below. Metal sputtering:  Sprinkle the metal material which is to be used evenly on the wafer to form a thin film. Coating photoresistance:  First put the photoresist material on the wafer, and then hit the beam on the desired part through the mask to destroy the structure of the photoresist material. Next, use chemicals to wash away the damaged material. Etching technology:  The silicon wafer without photoresistance protection will be etched by ion beam. Photoresist removal:  Use the photoresist solution to dissolve the remaining photoresist, so that a process can be completed. Finally, a lot of IC chips will be completed on a whole wafer, and then as long as the completed square IC chips are cut off, they can be sent to the packaging factory for packaging. What is the packaging factory? We'll have to explain it later. Nano-Process What is the nano-process? Samsung and TSMC compete fiercely in advanced semiconductor processes because both of them want to take the lead in wafer contract manufacturing to win orders, which has almost become a battle between 14 nanometers and 16 nanometers. But what is the meaning of 14 nm and 16 nm, and where do they refer? What are the benefits and problems that will be brought about by the reduction of the process? Next we will give a brief description of the nano-process. How tiny is the nanometer? Before you start, you need to understand what nanometer really means. Mathematically, nanometers are 0.000000001 meters, but this is a pretty bad example. After all, we can only see a lot of zeros after the decimal point, but we don't actually feel it. If you compare it with the thickness of nail, it may be more obvious. If you actually measure it with a ruler, you can tell that the thickness of the nail is about 0.0001 meters (0.1mm), that is to say, try to cut the side of a nail into 100000 lines, each of which is about one nanometer. From this, we can slightly imagine how tiny a nanometer is. Purpose of Reducing the Process After knowing how small the nanometer is, it is necessary to understand the purpose of reducing the process. The main purpose of reducing the transistor is to insert more transistors into smaller chips so that the chip will not become larger as a result of technological advances; second, it can increase the computational efficiency of the processor; moreover, reducing the volume can also reduce the power consumption. Finally, after the chip size is reduced, it is easier to plug into the mobile device to meet the needs of thinness and lightness in the future. Come back to explore what the nano-process is and we will take 14 nm as an example. The process refers to the minimum size of 14 nm in the chip. The following figure shows the appearance of a traditional transistor, as an example. The main purpose of reducing transistor is to reduce power consumption, but which part needs to be reduced to achieve this goal? The L in the figure on the left is what we expect to shrink. By reducing the gate length, the current can be routed from the Drain side to the Source end in a shorter path (if you are interested, you can use Google to search for MOSFET, which will be explained in more detail). Fig 11. In addition, computers operate on 0 and 1. How can we use transistors to meet this purpose? The way to do this is to determine whether the transistor has current flow. When a voltage supply is made at the Gate (green square), the current will flow from the Drain to the Source, and if there is no supply voltage, the current will not flow, so that it can represent 1 and 0. (As to why 0 and 1 are used to judge, if you are interested, you can go to the Brin algebra. That is the way we use this method to make a computer.) Physical Limitations of Downsizing However, the process cannot be reduced indefinitely. When we narrow the transistor to about 20 nanometers, we will encounter problems in quantum physics, so that the transistor has a leakage phenomenon, offsetting the benefits of L. As a way to improve, the concept of FinFET (Tri-Gate) was imported, as shown in the figure above. The leakage caused by physical phenomena can be reduced by importing this technology. Fig 12. More importantly, this method can increase the contact area between the Gate end and the lower layer. In traditional practice (top left), the contact surface has only one plane, but with FinFET (Tri-Gate), the contact surface will become three-dimensional, and the contact area can be easily increased. This allows the Source-Drain side to be smaller while maintaining the same contact area, which is of considerable help in reducing the size. Finally, why would anyone say that it would be a pretty serious challenge for factories to enter the 10-nanometer process? It is mainly because the size of an atom is about 0.1 nanometers, and in the case of 10 nanometers, there are fewer than 100 atoms in a line. It is very difficult to make, and as long as there is an atomic defect, such as atoms falling out or impurities in the production process, there will be unknown phenomena, affecting the yield of the product. If you can't imagine the difficulty, you can do a small experiment. Line up a 10 × 10 square with 100 small beads on the table, cut a piece of paper to cover the beads, then brush off the beads next to it with a small brush, and finally make it form a 10 × 5 rectangle. In this way, we can know the difficulties faced by the major factories and how difficult it is to achieve this goal. Encapsulation After a long process, from design to manufacture, finally we got an IC chip. However, a chip is so small and thin that it can be easily scratched and damaged if it is not protected from the outside. In addition, because of the small size of the chip, if you do not use a larger size of the shell, it will not be easy to manually place on the circuit board. Therefore, the next step is to describe the encapsulation: Two Common Packages At present, there are two common packages; one is the DIP package, which is common in electric toys and looks like a centipede, the other is the BGA package, which is common when buying boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array) used in the early CPU or an improved version of QFP (plastic square flat package) of DIP. Because there are so many packaging methods, only DIP and BGA encapsulation are described below: ——Enduring Traditional Packaging DIP Package The first thing to introduce is the Dual Inline Package (DIP), we can see from the following figure that the IC chip with this package will look like a black centipede at the foot of the dual inline connection and this is the earliest IC packaging technology. It has the advantage of low cost and is suitable for small chips without too many wires. However, because most of them are plastic, the heat dissipation effect is poor, which cannot meet the requirements of the current high-speed chips. Therefore, most of the chips using this package are durable chips, such as OP741 shown in the following figure or smaller IC chips with less speed requirements and fewer holes. Fig 13.  The IC chip shown on the left is a common voltage amplifier named OP741. On the right is its section. The package connects the chip to the leadframe with a gold wire. BGA Package As for spherical array (Ball Grid Array,BGA) packaging, compared with DIP, it is smaller and can be easily placed in smaller devices. In addition, because the pin is located under the chip, it can hold more metal pins than the DIP so it is Ideal for chips that require more contacts. However, the cost of this packaging method is high and the connection method is more complex, so it is mostly used in high unit price products. Fig 14.  On the left is a chip encapsulated in BGA. On the right is a schematic diagram of BGA using a cladding packaging. ——The rise of mobile devices and the emergence of new technologies on the stage Two Ways to Reduce Size However, the use of these packaging methods will cost a considerable amount of volume. For example, today's mobile devices, wearing devices, and so on, require quite a variety of components. If each component is packaged independently, it will cost a lot of space. Therefore, there are two ways to meet the requirements of reducing size. They are SoC (System On Chip) and SiP (System In Packet). SoC At the beginning of the rise of smart phones, the term SoC can be found in major financial magazines, but what is SoC? To put it simply, ICs with different functions are integrated into one chip. By this method, not only the volume can be reduced, but also the distance between different IC can be reduced, and the calculation speed of the chip can be improved. As for the manufacturing method, during the IC design phase, different ICs are put together and then a mask is made through the design process described earlier. However, SoC is not the only advantage; to design a SoC requires considerable technical cooperation. When IC chips are encapsulated, they have their own external protection, and the distance between IC and IC is long, so there is no interactive interference. But when all the ICs are wrapped together, it is the beginning of a nightmare. The IC design factory has to change from the original simple design IC, to the IC which requires them to understand and integrate the various functions. Therefore, it increase the workload of engineers. In addition, there will also be a lot of situations, such as the high-frequency signal of the communication chip may affect the IC of other functions and so on. In addition, SoC also needs to obtain IP (intellectual property) authorization from other vendors in order to put components designed by others into SoC. Because making SoC needs to obtain the design details of the whole IC in order to make a complete mask, which also increases the design cost of SoC. Some people may question why not just design one by yourself. That is because designing all kinds of IC requires a lot of knowledge related to the IC, only a rich enterprise like Apple can have a budget to poach top engineers from well-known enterprises. It's still a lot cheaper to design a whole new IC through collaborative licensing than to develop it by yourself. SiP As an alternative, SiP has leapt onto the stage of integrating chips. Unlike SoC, it buys IC from different enterprises and finishes the last step, which is to encapsulate the IC. In this way, the IP licensing step is eliminated and the design cost is significantly reduced. In addition, because they are independent ICs, the degree of interference with each other is greatly reduced. Fig 15. Apple Watch uses SiP technology to package the entire computer architecture into a chip, not only to meet the desired performance but also to reduce the size, so that the watch has more space for battery release. The most famous product using SiP technology is Apple Watch. Because the internal space of Watch is too small, it cannot use the traditional technology, the design cost of SoC is too high, SiP has become the first choice. With SiP technology, not only the volume can be reduced, but also the distance between each IC can be shortened, so SiP can be a feasible compromise. The following figure shows the structure of the Apple Watch chip, and you can see that quite a few IC are included in it. Fig 16. Internal configuration Diagram of S1 Chip encapsulated by SiP in Apple Watch After the packaging is completed, we will enter the testing stage. At this stage, it is necessary to confirm whether the encapsulated IC is functioning properly and that it can be shipped to the assembly plant after it is correct, so that the electronic products we can see can be made. So far, the semiconductor industry has completed the task of the whole production.

As the development of social technology,computer is becoming an universal things in families.The huge increase in computing performance in recent decades also has been achieved by squeezing ever more transistors into a tighter space on microchips. However,it's the tighter space on microchips that leads to effects such as signal leakage betwwen components,which will slow down communication between different parts of the chip. People in technology call this kind of delay as " interconnect bottleneck" as it is becoming an increasing problem in high-speed computing system.  Researchers are trying their best and all their professional knowledge to consider how to solve this problem. According to Pablo Jarillo-Herrero,an associte professor of physics at MIT,however,one way to tackle the interconnect bottleneck is to use light rather that wires to communicate between different parts of a microchip.But it is a hard work that the material "sillicon" used to build chips,does not emit light easily. The article about a light emitter and detector that can be integrated into sillicon CMOS chips was published in the Journal Nature Nanotechnology,a monthly peer-reviewed scientific journal published by Nature Publishing Group.This paper was written by MIT postdoc Ya-Qing Bie who joined Jarillo-Herrero and an interdisciplinary team including Dirk Englund, an associate professor of electrical engineering and computer science at MIT . According to this paper,the device is built from a semiconductor material called molybdenum ditelluride. This ultrathin semiconductor belongs to an emerging group of materials known as two-dimensional transition-metal dichalcogenides.  Unlike conventional semiconductors, the material can be stacked on top of silicon wafers, Jarillo-Herrero says."Researchers have been trying to find materials that are compatible with silicon, in order to bring optoelectronics and optical communication on-chip, but so far this has proven very difficult,for example,gallium arsenide is very good for optics, but it cannot be grown on silicon very easily because the two semiconductors are incompatible." on the contrary,the 2-D molybdenum ditelluride can be mechanically attached to any material.Another difficulty with integrating other semiconductors with silicon is that the materials typically emit light in the visible range, but light at these wavelengths is simply absorbed by silicon.Molybdenum ditelluride emits light in the infrared range, which is not absorbed by silicon, meaning it can be used for on-chip communication.To use the material as a light emitter, the researchers first had to convert it into a P-N junction diode, a device in which one side, the P side, is positively charged, while the other, N side, is negatively charged. In conventional semiconductors, this is typically done by introducing chemical impurities into the material. With the new class of 2-D materials, however, it can be done by simply applying a voltage across metallic gate electrodes placed side-by-side on top of the material.Jarillo explained continuelly:""That is a significant breakthrough, because it means we do not need to introduce chemical impurities into the material [to create the diode]. We can do it electrically." Once the diode is produced, the researchers run a current through the device, causing it to emit light."So by using diodes made of molybdenum ditelluride, we are able to fabricate light-emitting diodes (LEDs) compatible with silicon chips." The device can also be switched to operate as a photodetector, by reversing the polarity of the voltage applied to the device. This causes it to stop conducting electricity until a light shines on it, when the current restarts,so that the devices are able to both transmit and receive optical signals. This device is a proof of concept and there are a great deal of work need to be done before the technology can be developed into a commercial product, Jarillo-Herrero says. The researchers are now investigating other materials that could be used for on-chip optical communication.Most telecommunication systems, for example, operate using light with a wavelength of 1.3 or 1.5 micrometers, howevermolybdenum ditelluride emits light at 1.1 micrometers. This makes it suitable for use in the silicon chips found in computers, but unsuitable for telecommunications systems. "It would be highly desirable if we could develop a similar material, which could emit and detect light at 1.3 or 1.5 micrometers in wavelength, where telecommunication through optical fiber operates,"  Jarillo-Herrero added. In the end,researchers are another ultrathin material called black phosphorus, which can be tuned to emit light at different wavelengths by altering the number of layers used. They hope to develop devices with the necessary number of layers to allow them to emit light at the two wavelengths while remaining compatible with silicon. The article was ended by Jarillo hopes that communication on-chip by optical signals instead of electronic signals because they can do so more quickly whle comsuming less power. Well,let's cheer researchers on and hope them get success in the near future. 

（The new device is smaller than a thumbnail with a size of 0.1 x 4mm, and could be integrated into everyday electronic devices like smartphones.） Integrated circuits, so called chips, are used in everyday electronic equipment like mobile phones and computers. It is a set of electronic circuits on one small flat piece of semiconductor material, normally silicon. But this material has some limitations when it comes to processing data. To overcome these limitations and improve data processing, researchers are developing optical circuits made of chalcogenide glass. This special type of glass is used for ultrafast telecommunication networks, transferring information at the speed of light. Integrating these glass optical circuits into silicon chips could lead to a more advanced communications system, processing data a hundred times faster. Can these two materials be combined? The answer is yes! In a collaboration with physicists in the University of Sydney's Australian Institute for Nanoscale Science and Technology (AINST), the Australian National University (ANU) and RMIT University, the CUDOS research group around PhD candidate Blair Morrison and senior researcher Dr Alvaro Casas Bedoya created compact, mass manufacturable optical circuits with enhanced functionalities by combining nonlinear glasses with silicon-based material. "In the last few years the group at the University of Sydney has repeatedly demonstrated exciting functionalities, such as broadband microwave devices that enhance radar, using these novel chalcogenide glasses," Blair Morrison said from the University of Sydney CUDOS node. "Now we have shown it is possible to combine this material with the current industry standard platform for photonic integration, silicon," he said. "We integrated a novel nonlinear glass into an industrially scalable CMOS compatible platform. We maintained the key advantages of both the silicon and the glass, and made a functional and efficient ultra-compact optical circuit," said Dr Alvaro Casas Bedoya who is the lead photonics nanofabrication manager for CUDOS. "A wealth of new opportunities will be created, and this takes us one step closer to moving our research from the lab into industrial applications," said Blair Morrison. CUDOS Director and ARC Laureate Fellow Professor Benjamin Eggleton from the University of Sydney said this new approach will one day allow the industry to miniaturise the photonics functionalities from devices that are the size of a laptop to the size of a smartphone and even smaller, allowing for deployment in real world applications. "This is exciting, because this is a platform which is more compatible with existing semiconductor manufacturing and will allow us to integrate multiple functionalities on a single silicon chip, with active and passive components, such as detectors and modulators, required for advanced applications," said Professor Eggleton who supervised the project. The multi-university research team went through the whole manufacturing process: The fabrication of these devices uses silicon wafers from a semiconductor foundry in Belgium, a dedicated facility in ANU's Laser Physics Centre for the glass deposition, lithography in the RMIT University's School of Engineering and are then characterised and tested in the University of Sydney's AINST. To showcase the potential of the new approach, the CUDOS researchers further demonstrated a compact novel laser based on the light-sound interactions, the first time in an integrated optical circuit. "The breakthrough here is this realisation that we can actually interface, we can integrate that glass onto silicon and we can interface from silicon to the glass very efficiently -- we can harness the best of both worlds," Professor Eggleton said. Professor Susan Pond, the Director of AINST, emphasized that this project is one of AINST flagship activities that deals with harnessing interactions between photons and phonon at the nanoscale. This work links fundamental research in light matter interactions at the nanoscale with an end user perspective and strong coupling to industry. Ref.KY32-LMX6502SQKY32-LN2300KY32-LN3251MPW

The giant chip maker Intel has finally released its 3ed generation chips named Ivy Bridge. They says that the new microprocessor chips used fundamentally different technology. These chips comes with 3D Transistors and are manufactured at 22nm process. The new technology will ensure high processing speed along with power saving. The chip makers keep the pace of Moore’s law by making the new chips using 3d transistor technology along with other advanced capabilities. We can hope that, customers will certainly welcome the new chip, because of the competence of it predecessors including the current Sandy Bridge chips. We know that transistors are the heart of processors and a microprocessor contains millions of it. Until today transistors were 2D (planar) devices, but Intel’s new Ivy Bridge chips comes with sophisticated 3D Tri-Gate Transistors. The new Ivy Bridge chips will power Gaming PC’s, Servers, Super Computers and all-in-one PC’s. We can hope that through this new line of chips, Intel will dominate in chip market with its major rival AMD. Now we will discuss some of the important features of the new Ivy Bridge chips. Ivy Bridge chips are relatively smaller and lighter in weight as it utilizes advanced technologies. The 3D Transistors these chips are lighter compared to transistors used in previous chips of Intel, through this Intel delivers the advantages of Moore’s law to its users. Intel has shrunk the Manufacturing technology of Ivy Bridge chips lower to 22nm because Intel notes that smaller chips are better in providing higher performance and higher efficiency. Intel says that in 2007 their CPU manufacturing process has changed to 45nm with high-k/metal gate, in 2009 to 32nm and now to 22nm with the world’s first 3-D transistor in a high volume logic process. Intel has made the new Ivy Bridge transistors in such a way that it can work efficiently even at lower voltages. Thus through this advanced sophisticated Ivy Bridge chips Intel strengthened its domination in global chip market and the company lifts up challenge not only to AMD but also to ARM holding the mobile chip market. Reference: KY32-NU80579EZ600CT KY32-NU80579ED009C

While investigating mass transit accidents, National Transportation Safety Board (NTSB) officials often rely on digital clues left behind in flash memories of any and all electronic devices—both personal and professional—at a crash site. With the physical forces and high-temperature fires associated with many crashes, memory units are often damaged and sometimes unreadable.Researchers at Binghamton University, State University of New York have figured out how much damage memory units can sustain before becoming unreadable and new repair techniques to retrieve clues off of damaged units, which might help prevent future tragedies."The biggest surprise was how much punishment these devices can take before ceasing to function," said Steve Cain, who is the project manager and a senior research support specialist in the Integrated Electronics Engineering Center (IEEC) at Binghamton University. "As part of their post-crash investigations, the NTSB collects anything and everything at the scene, including personal electronic devices. If the device was active during or just before the crash, it is possible that the data stored in the memory can provide clues as to the cause of the crash. Most of the time the device is ruined, but sometimes it is intact."The interdisciplinary Binghamton group of Cain, Preeth Sivakumar, Jack Lombardi, and Mark Poliks along with James Cash, Joseph Gregor, and Michael Budinski from the NTSB, presented "Fire Damage and Repair Techniques for Flash Memory Modules: Implication for Post-Crash Investigations" at the Fall 2016 International Symposium of Microelectronics.Scientists found plastic coverings started to break down after three hours of exposure to temperatures of 300 degrees Celsius, or about 572 degrees Fahrenheit or more, but memory chips were still readable.Researchers pointed out that even with the pressures and forces in play during past crashes, temperatures typically only reach those levels for short periods of time."Data integrity was maintained even in a plasma discharge," Cain said. "Basically, if the device doesn't burn up, there is a reasonable chance of the data being retained in the chip. The only problem is that the connections to the memory chips may be broken, so that the data cannot be read."For the second part of the study, researchers addressed the readability issue. The team purposely damaged memory units and then extracted memory chips using acid, lasers, plasma, or mechanical polishing.Lasers were the most effective extraction method and mechanical extractions was the simplest, but each method still damaged the wire bonds within memory chips and made many unreadable. A specialized metallic ink from a precision printer was used to restore functionality."These results expand the investigative scope for aviation accidents, where the data rather than the device is of paramount importance," the team concluded. "It is possible to repair the interconnections of flash memory modules, provided the chip is intact." Reference:MT16JTF51264AZ-1G6M1SDUS5EB-001GMD2202-D192