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In today's computer chips, memory management is based on what computer scientists call the principle of locality: If a program needs a chunk of data stored at some memory location, it probably needs the neighboring chunks as well.But that assumption breaks down in the age of big data, now that computer programs more frequently act on just a few data items scattered arbitrarily across huge data sets. Since fetching data from their main memory banks is the major performance bottleneck in today's chips, having to fetch it more frequently can dramatically slow program execution.This week, at the International Conference on Parallel Architectures and Compilation Techniques, researchers from MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL) are presenting a new programming language, called Milk, that lets application developers manage memory more efficiently in programs that deal with scattered data points in large data sets.In tests on several common algorithms, programs written in the new language were four times as fast as those written in existing languages. But the researchers believe that further work will yield even larger gains.The reason that today's big data sets pose problems for existing memory management techniques, explains Saman Amarasinghe, a professor of electrical engineering and computer science, is not so much that they are large as that they are what computer scientists call "sparse." That is, with big data, the scale of the solution does not necessarily increase proportionally with the scale of the problem."In social settings, we used to look at smaller problems," Amarasinghe says. "If you look at the people in this [CSAIL] building, we're all connected. But if you look at the planet scale, I don't scale my number of friends. The planet has billions of people, but I still have only hundreds of friends. Suddenly you have a very sparse problem."Similarly, Amarasinghe says, an online bookseller with, say, 1,000 customers might like to provide its visitors with a list of its 20 most popular books. It doesn't follow, however, that an online bookseller with a million customers would want to provide its visitors with a list of its 20,000 most popular books.Thinking locallyToday's computer chips are not optimized for sparse data—in fact, the reverse is true. Because fetching data from the chip's main memory bank is slow, every core, or processor, in a modern chip has its own "cache," a relatively small, local, high-speed memory bank. Rather than fetching a single data item at a time from main memory, a core will fetch an entire block of data. And that block is selected according to the principle of locality.It's easy to see how the principle of locality works with, say, image processing. If the purpose of a program is to apply a visual filter to an image, and it works on one block of the image at a time, then when a core requests a block, it should receive all the adjacent blocks its cache can hold, so that it can grind away on block after block without fetching any more data.But that approach doesn't work if the algorithm is interested in only 20 books out of the 2 million in an online retailer's database. If it requests the data associated with one book, it's likely that the data associated with the 100 adjacent books will be irrelevant.Going to main memory for a single data item at a time is woefully inefficient. "It's as if, every time you want a spoonful of cereal, you open the fridge, open the milk carton, pour a spoonful of milk, close the carton, and put it back in the fridge," says Vladimir Kiriansky, a PhD student in electrical engineering and computer science and first author on the new paper. He's joined by Amarasinghe and Yunming Zhang, also a PhD student in electrical engineering and computer science.Batch processingMilk simply adds a few commands to OpenMP, an extension of languages such as C and Fortran that makes it easier to write code for multicore processors. With Milk, a programmer inserts a couple additional lines of code around any instruction that iterates through a large data collection looking for a comparatively small number of items. Milk's compiler—the program that converts high-level code into low-level instructions—then figures out how to manage memory accordingly.With a Milk program, when a core discovers that it needs a piece of data, it doesn't request it—and a cacheful of adjacent data—from main memory. Instead, it adds the data item's address to a list of locally stored addresses. When the list is long enough, all the chip's cores pool their lists, group together those addresses that are near each other, and redistribute them to the cores. That way, each core requests only data items that it knows it needs and that can be retrieved efficiently.That's the high-level description, but the details get more complicated. In fact, most modern computer chips have several different levels of caches, each one larger but also slightly less efficient than the last. The Milk compiler has to keep track of not only a list of memory addresses but also the data stored at those addresses, and it regularly shuffles both around between cache levels. It also has to decide which addresses should be retained because they might be accessed again, and which to discard. Improving the algorithm that choreographs this intricate data ballet is where the researchers see hope for further performance gains."Many important applications today are data-intensive, but unfortunately, the growing gap in performance between memory and CPU means they do not fully utilize current hardware," says Matei Zaharia, an assistant professor of computer science at Stanford University. "Milk helps to address this gap by optimizing memory access in common programming constructs. The work combines detailed knowledge about the design of memory controllers with knowledge about compilers to implement good optimizations for current hardware."  

Imec and Holst Centre (set-up by imec and TNO) have demonstrated a prototype of a single-chip electrochemical sensor for simultaneous detection of multiple ions in fluids. The demonstrator paves the way to small-sized and low-cost detection systems for agriculture, healthcare and lifestyle applications, food quality monitoring and water management.Imec and Holst Centre's ion sensor solution is a generic platform that can be tailored towards specific applications. It enables efficient and low-cost monitoring, such as monitoring of nutrient concentrations in surface and waste water, both for agricultural applications and water quality. In the healthcare and lifestyle applications, it provides disposable point-of-care solutions, or conformable solutions for integration into patches. Depending on the application and the form factor, it can be mass produced through microfabrication or through screen-printing on inexpensive substrates such as glass or foil. As compared to commercial ion sensors, this bring a unique advantage in terms of low cost manufacturability, and size of the solution. Moreover, by changing the selective membranes on the electrodes, the sensor can be adopted to detect other ions.The presented prototype is a handheld device that integrates a single-chip sensor with different electrodes that detect pH levels in a range from 2 to 10 at a 0.1 pH accuracy. For the chemical elements chloride (Cl-), sodium (Na+), potassium (K+), and nitrate (NO3-) -ranging from 10-4 M to 1 M ions- the sensor detects at a 10 percent accuracy. Benchmarked against other available single-ion sensors, imec's prototype demonstrated comparable sensitivity and accuracy for a versatile multiple-ion solution."With small autonomous smart sensors that adapt to and wirelessly communicate with the environment and each other, imec aims to develop the building blocks that enable an Intuitive Internet of Things," stated Kathleen Phillips, program director perceptive systems at imec. "Our scientists and engineers have reached an important breakthrough demonstrating the capabilities of our technology with this versatile single-chip sensor. As we continue to improve our sensor platform, develop sensors for other ions, integrate more sensors into a single system, and extend the lifetime of our sensor, imec will be at the nucleus in driving the advancements of smart connected systems. We invite industry to join our R&D program, become a partner to jointly develop new ion sensing applications and to bring this technology to the market." 

Engineers at PARC, a Xerox company, have come up with a chip that will self-destruct on command; it was demonstrated at DARPA's Wait, What? event in St. Louis on Thursday.The chip was developed under the Defense Advanced Research Projects Agency (DARPA), part of the latter's Vanishing Programmable Resources (VAPR) program.Last year, PARC spoke of DARPA's goal, to demonstrate electronic systems capable of physically disappearing in a controlled, triggerable manner. In April 2014, PARC issued a news release, "PARC Awarded Up To $2 Million from DARPA to Develop Vanishing Electronics" in which it revealed its contract with the Defense Advanced Research Projects Agency to develop a "disappearing electronics" platform called DUST, which stands for Disintegration Upon Stress-Release Trigger."Sophisticated electronics can be made at low cost and are increasingly pervasive throughout the battlefield," the announcement said. "Large numbers can be widely proliferated and used for applications such as distributed remote sensing and communications. However, it is nearly impossible to track and recover every device, resulting in unintended accumulation in the environment, potential unauthorized use, and compromise of intellectual property and technological advantage."The chip, demonstrated at the Thursday event, could be used to store data such as encryption keys but, on command could shatter into pieces so small that it would be it impossible to reconstruct.Military applications come to mind; also, commercial and scientific could find use for the DUST technology.The 2014 announcement noted how in environment science DUST sensors could find use to measure weather patterns such as hurricane predictions or vibrations preceding earthquakes but then be removed from the environment with no footprint. PARC's Sean Garner, part of the DUST project, "Imagine," said Garner, "being able to cover a large area, like the ocean floor, with billions of tiny sensors to 'hear' what is happening within the earth's crust, and have them quickly disintegrate into, essentially, sand, leaving no trace and not harming the planet or sea life."Martyn Williams, senior U.S. correspondent, IDG News Service, reported on the Thursday event; he quoted Gregory Whiting, a PARC senior scientist:"We really wanted to come up with a system that was very rapid and compatible with commercial electronics."A chip is fabricated on a glass substrate. "We take the glass and we ion-exchange temper it to build in stress," said Whiting in the IDG News report.The glass was stressed to breaking point by heat. Reported Williams: "When a circuit was switched on, a small resistor heated up and the glass shattered into thousands of pieces. Even after it broke up, stress remained in the fragments and they continued breaking into even smaller pieces for tens of seconds afterwards." (The self-destruct circuit was triggered by a photo-diode, which switched on the circuit when a bright light fell on it. In the demo, the light was provided by a laser, but the trigger could be anything from a mechanical switch to a radio signal, said Williams.)Beyond a future in security and environmental sciences, Popular Mechanics' John Wenz offered his suggestion for its future. He said it could make for "a great hackathon for people to figure out how to break into a system and shatter the chips (supposing a triggering element is installed internally) in order to either further strengthen the security, or just to be a butthead. 

  Catalog   Brief Introduction What Is System on Chip?         Content of The Study Bus Architecture Technology IP Core Reuse Technology Reliability Design Technology   Software and Hardware Co-design Technology SoC Design Verification Technology   Chip Synthesis / Timing Analysis Technology   Testability / Debuggability Design Technology Low Power Consumption Design Technology New Circuit Implementation Technology Embedded Software Migration / Development     SoC classification   Technical Characteristics of CSoC   Technical Characteristics of SoPC Technical Characteristics of ASIC SoC Classification Principles of SoC Classification Model of SoC     Development Direction of SoC Technology   Computer Science Promotes the Level of SoC      Technology SoC Promotes the Development of Computer Architecture SoC Opens Up a New World for The Development  of      Interdisciplinary Disciplines Brief Introduction of SoC A system on chip (SoC) is a microchip which has all the necessary electronic circuits and other parts of a given system on a single integrated circuit. This technology is especially used in small yet extremely complex consumer electronic devices. There are some devices which have more processing power and memory than a standard desktop. This is possible only with the use of system on chip design. In simple terms a system on chip is an integrated circuit which integrates all components of a computer or any other electronic system into a single chip. It may include analog, digital, mixed-signal and other radio frequency funtions on a single chip substrate. Due to their low power consumption, SoCs are quite common in the mobile electronics market. Embedded systems is the best example of the use of system on chip. Figure 1   The structure of a typical system of chip consists of: —A microcontroller, digital signal processor or microprocessor core. —Memory blocks along with a selection of RAM, ROM, EEPROM and flash memory. —Oscillators, phase-locked loops and other timing sources. —Counter-timers, eral-time timers as well as power-on reset generators. —USB, FireWire, Ethernet, SPI, USART and other external interfaces as well. —Analog interfaces including ADCs and DACs.   Along with the above mentioned hardware, system on chip design also has software which controls the microcontroller, microprocessor, peripherals and interfaces. The design flow of a SoC aims at developing both the hardware and software in a parallel manner. Typically most of the system on chip are developed from pre-qualified hardware blocks along with the software drivers which control their operation. While the hardware blocks are arranged together with the help of CAD tools, software-development environment is used to integrate the software modules.   The next step is functional verification of the system on chip design to verify and debug both harware as well as software prior to tapeout. The technologies with which SoC can be fabricated are: —Standard Cell —Full Custom —Field-programmable Gate Array   As SoC designs consume less power and have higher reliability and lower cost as compared to the multi-chip systems which they replace, they are regarded as the best option to be used.   The major problems/ challenges faced by SoC designers are as follows: Functional content complexity – The amount of the content involved in build SoCs leads one to the conclusion that designing these systems is not easy even for large design teams. This is why some form of intellectual property reuse has become an inevitable part of SoC design. Along with functional content complexity, architectural as well as verification challenge are some of the major problems inherent in the SoC designing.     Content of The Study SoC design methodology mainly studies Bus Architecture Technology, IP Core Reuse Technology, Reliability Design Technology, Software and Hardware Co-design Technology, SoC Design Verification Technology, Chip Synthesis / Timing Analysis Technology, Testability / Debuggability Design Technology, Low Power Consumption Design Technology, New Circuit Implementation Technology, etc. In addition, Operating System / Embedded Software Migration, Development and Research are also needed to be done in this new interdisciplinary field of research.   Bus Architecture Technology Bus structure and interconnection technology directly affect the overall performance of the chip. For a single application field, mature bus architecture can be selected; for those with high serialization or comprehensive performance requirements, in-depth architecture research can be carried out, and the bus architecture with its own characteristics can be constructed. Therefore, it can be refined and strengthened without being restricted by third parties, develop synchronously with the system and become more competitive. At present, the development of SoC is mainly based on platform (including independent construction of the overall architecture), based on core, based on synthesis and other methods, and constantly introduce better performance, stronger scalability of the bus specification.   IP Core Reuse Technology IP core is generally divided into hard IP core, soft IP core and firm IP core. Hard IP core refers to the IP core which has been pre-arranged and cannot be modified by the system designer. The soft IP core is usually submitted in the form of HDL language. Firm IP core is composed of RTL description and synthesizable network table. The research focus of IP core reuse is to develop the integration of specification and testability to adapt to a variety of bus interfaces in order to achieve the purpose of reuse with as few outsourcing and test vectors as possible. IP cores should have good development documentation and reference manuals, including data manuals, user guidelines, simulation and reuse models, and compatibility is an important factor.   Reliability Design Technology Because SoC is composed of multi-level bus and each bus contains multiple devices (IP core). Therefore, it is very important to ensure the normal operation of the whole chip. And the anti-"deadlock" mechanism and "unlocking" mechanism must be considered, which means that a device (IP core) will not affect the other functions of the whole chip even if it is paralyzed. In addition, with the development of ultra-deep submicron technology, the reliability of bus transmission becomes a serious challenge, so it is necessary to study the fault-tolerant mechanism and fault recovery mechanism.   Software and Hardware Co-design Technology Due to the pressure of market and design risk, SoC hardware and software co-design becomes particularly important. Improving hardware / software co-description, co-analysis, co-design, co-simulation and co-verification can greatly reduce the risk of hardware design and shorten the development and debugging time of embedded software. At the same time, the fatal problems existing in the software and hardware can be found in the co-verification environment in time, and the readjustment of the software and hardware can be avoided in the final integration test.   SoC Design Verification Technology It is mainly divided into three levels: IP core verification, IP core and bus interface compatibility verification and system-level verification, including design concept verification, design implementation verification, design performance verification, fault simulation, chip testing and so on. From the type of verification, there are compatibility test, corner test, random test, real code test, regression (Regression) test, assertion verification and so on. Due to the increasing complexity of the chip and the high cost of software simulation, hardware simulation verification has become an important verification method. Verification accounts for about 70% of the whole design work. And how to improve the verification coverage and efficiency is the eternal topic of design verification.     Chip Synthesis / Timing Analysis Technology Due to the increasing complexity and scale of SoC system, new topics such as multi-clock, multi-voltage and ultra-deep submicron continue to emerge, which puts forward higher requirements for the comprehensive research of SoC. In particular, the research on how to classify and decompose the time series budget and special constraints of critical path requires researchers to master a great deal of system background knowledge. At the same time, the static timing analysis (STA) is becoming more and more complex and the efficiency of back-end dynamic simulation is low, which poses a severe challenge to the overall designers.     Testability / Debuggability Design Technology This paper mainly studies and solves the problems of batch production testability and online debuggability. The implementation technologies include DFT, SCAN, BIST, Iddq, JTAG/eJTAG. To study the SoC test architecture based on various IP cores and test the efficient transitivity of vector, It is more important to consider the parallelization of testing and reduce the time occupied by chip testing. In addition, we should pay attention to online debugging to facilitate users to develop and debug SoC-based products.   Low Power Consumption Design Technology Low power consumption has become an equally important design goal as area and performance, so accurate evaluation of power consumption has also become an important issue. The power consumption of the chip is mainly composed of jump power consumption, short circuit power consumption and leakage power consumption. In order to reduce power consumption, it is necessary to study the circuit implementation technology, input vector control (IVC) technology, multi-voltage technology, power consumption management technology and software (algorithm) low-power utilization technology from the perspective of SoC multi-level stereo to solve the problem comprehensively.   New Circuit Implementation Technology Due to the sharp increase in the number of transistors, the decreasing chip size, the increasing density, the increased reuse frequency of IP cores, the emergence of low voltage, multi-clock, high frequency, high testability, new and difficult packaging and other requirements, as well as the endless emergence of new design technologies, the minimum dimensions of semiconductor technologies develop towards deep submicron. And this requires SoC designers to constantly study new technologies, new tools, key circuit architecture, timing convergence, signal integrity, antenna effect and so on.     Embedded Software Migration / Development The main research and development of BIOS and embedded operating system transplantation / development of SoC is to support multi-task, to make program development easier, to improve the stability and reliability of the system, to make maintenance convenient, to make reading and understanding easier. Therefore, it should have the characteristics of good security, strong robustness, high code execution efficiency and so on. For example, the embedded Linux operating system code implantation research on SoC chip can reduce the difficulty based on BSP development for system developers. At the same time, it improves the development efficiency and shortens the development cycle.     SoC classification In this paper, SoC is classified into three categories: CSoC, SOPC and ASIC SoC, and then unified them into SoC architecture classification model.   Technical characteristics of CSoC CSoC is generally composed of processor, memory, ASIC-based kernel and on-chip reconfigurable components, which has obvious advantages over ASIC SoC and multi-chip board-level development based on standard components. It is characterized by:    —CPU + reconfigurable processing artifacts. —Efficiency and flexibility combine well. —Refactoring based determination processing function. —It is superior to supercomputer in image processing, pattern matching and so on. —According to the needs of the task, it can be dynamically reconfigurable to improve the performance-price ratio.   At present, the academia pays more attention to the XPP (eXtreme Processing Platform), which is the efficient processor with dynamic reconfiguration. XPP embeds programmable logic modules in a SoC based on a microprocessor core based on a bus architecture to form a reconfigurable SoC platform, as shown in figure 1. The applicable reconfigurable data processing architecture is often composed of processing array element (PAE), communication network packet oriented, hierarchical reconfiguration management tree (CM) and I/O module. XPP has the ability to automatically reconstruct streams and process data streams, breaking through the traditional John von Neumann instruction stream mode. Because of the high degree of regularity, it is easy to obtain instruction-level parallelism and pipeline efficiency.   Figure 2.     CSoC Architecture based on XPP/Leon   Technical characteristics of SoPC SoPC is a special on-chip system. It is a programmable system which has flexible design mode. It can be cut, expanded and upgraded and it also has programmable functions in the development of software and hardware on-line system. It combines the advantages of SoC and FPGA, including the following basic characteristics: —Contains at least one embedded processor IP core —Small capacity on-chip high-speed RAM resources —Rich IP core resources for choice —Sufficient on-chip programmable logic resources —Shared or coexisting processor debugging interface and FPGA programming interface —May contain partially programmable analog circuits   The block diagram of SoPC is shown in figure 2. In addition to the above characteristics, it also involves the software and hardware co-design technology, which has aroused widespread concern at present. Because the main logic design of SoPC is carried out in programmable logic devices, and BGA packaging has been widely used in the field of micropackaging, traditional debugging equipment, such as logic analyzer and digital oscilloscope, has been difficult to carry out direct test and analysis. Therefore, it is necessary to put forward higher requirements for software and hardware co-design technology based on simulation technology. At the same time, new debugging technology has been emerging.   Figure 3.  The block diagram of SoPC Technical characteristics of ASIC SoC ASIC SoC is an application-specific on-chip system, which has the characteristics of high performance, strong real-time, high reliability, low power consumption, low cost and so on. It generally has the following basic characteristics:  —At least one CPU kernel.  —Normative bus architecture  —RAM resources (or on-chip memory access controller)  —An appropriate amount of I/O equipment (including analog ones)  —Extensible interfaces (such as PCI)  —On-line debugging port (eJTAG)  —Circuits with testability   Figure 4.  L*BUS Bus Architecture Diagram   ASIC SoC is generally a product based on IP core or SoC development platform. It requires expertise, IP libraries, SoC bus architecture, and embedded software support (including BIOS, OS). It also requires a wide range of multifunctional IP cores and the design to integrate customer logic with it to meet customers’ needs for product development. SoC designers not only take advantage of the latest technology, but also reduce the development cycle and risk by reusing the proven IP core.   At present, there are many kinds of SoC bus architecture and each of them is developed to meet the requirements of its specific application field. Some are suitable for downmarket embedded products, some are suitable for handheld products, and some are suitable for high-energy products. In a word, everyone has its own advantages. The development of SoC cannot be separated from the constraints of power consumption, performance, cost, testability, reliability, IP core reusability, platform technical support and software and hardware’s co-development. Developers need to have a strong background in computer architecture in order to support its rapid development.   Classification principles of SoC SOC can be classified according to the architecture it adopts: One is the architecture based on instruction stream computing, which is typically represented by the traditional ASIC SoC. According to the control of instruction stream and data stream, this type can be divided into SISD (single instruction stream-single data stream), SIMD (single instruction stream-multiple data stream), MISD (multiple instruction stream-single data stream) and MIMD (multiple instruction stream-multiple data stream) in order to flexibly adapt to the needs of different algorithms in various applications.   The second one is an architecture based on data stream computing, which only controls the input / output data of the unit. Working according to the principle of data stream, it is more efficient than instruction stream, but less flexible. Pulsating array based on data stream computing is a typical architecture of this kind. A pulsating array is an array of data path components DPU (Data Path Unit). The data streams out of the data memory according to the beat, completes the calculation through the PU array, and the result flows back to the data memory. PU arrays have only the ability to control data, which is also the origin of FlowWare. Conventional SoPC is its typical technical representative.   The third is the architecture based on configuration stream computing. Using coarse-grained FPGA chip as carrier，SoC can dynamically reconstruct the hardware form of architecture design by adopting Morphwave. It can be an array of rPU (reconfigurable Processing Unit) and implemented by Configuwave. The configuration stream comes from the configuration memory called CM (reConfiguration Memory), which controls the changes of the rPU array through reConfiguration Manager and works according to the principle of data stream. CSoC is its typical technical representative.   Classification model of SoC According to the classification principles of the SoC architecture mentioned above, we establish a three-dimensional classification model of CDI architecture on the basis of the concepts of instruction stream, data stream and configuration stream, corresponding to I (Instruction Stream Architecture) axis, D (Data Stream Architecture) axis and C (reConfiguration Stream Architecture) axis. And it is shown in figure 4.   Any SoC with hybrid computer architecture of instruction stream computing, data stream computing and configuration stream computing can be summarized in CDI three-dimensional space. There are four basic architecture classifications on I axis: SISD, SIMD, MISD and MIMD. On the D axis, there are only two basic states: single data stream architecture and multiple data stream architecture. And there are also only two basic states on the C axis: single reconfiguration stream architecture and multiple reconfiguration stream architecture.      Figure 5.  CDI Classification Model Diagram     Development Direction of SoC Technology Since the concept of SoC was put forward in the late 1990s, the technology has been developed rapidly. Whether it is CSoC, SoPC or ASIC SoC, all of them are gradually related to computer science, microelectronics, materials and technology, electronic communication and so on. Their interdisciplinary development provides a strong support for the technical development of SoC.   Computer Science promotes the level of SoC Technology John von Neumann architecture and data stream architecture are the mainstream architectures of computers. The first one is characterized by the integration of program and data while the second one is characterized by the separation of program and data. The miniaturization of general purpose computer provides a source for the development of SoC technology.   Bus Architecture Technology, Algorithm Implementation Technology, Modular Design Technology, BIOS Technology, Software Engineering Technology, Software and Hardware Debugging Technology, System Verification Technology, performance Evaluation Technology, Real-time Processing Technology, Reliability Design Technology, Human-computer Interaction Technology, Load Balancing Technology and Low-power Consumption Design Technology in computer field are all reflected in SoC design technology. It also promotes the rapid development of SoC in a few years and becomes one of the main development directions of computers in the post-PC era.   Although the development of SoC technology is closely related to the development of technology and the improvement of EDA design means, its core is CPU core, bus architecture and various IP cores. In the overall performance evaluation and implementation technology, all of them are related to the computer professional field. Especially in upmarket applications, such as multi-CPU core integration and heterogeneous integration and other system requirements, computer science will continue to promote the development of SoC technology from different levels.   SoC promotes the Development of computer Architecture The development of SoC technology is closely related to the market demand. The main application fields of SoC are computer, communication, consumer electronics, industrial control, transportation and so on. Communications, computers and consumers account for more than 80 percent of SoC's sales, and the proportion of consumers is growing.   It can be divided into different categories if we further subdivide SoC market. For computer, there is image processing, hard disk drive, high-grade printer, personal assistant and so on. For communication, there is wired network, wireless network, mobile phone, visual equipment, communication base station and so on. For industrial control, there is process control or processing, test or instrument, medical equipment, monitoring system and so on. And for transportation, there is engine control, instrument device, safety system and so on. With the increasing scale of SoC market, it plays a more and more important role in the field of information technology and electronic products. At present, the SoC market is basically based on middle and low-grade SoC products. With the increasing demand for digital products, the demand for upmarket SoC is becoming more and more urgent. For example, in audio, video, communication and other fields, higher requirements are placed on SoC such as dual-core, quad-core and other multi-core integration. SoC will replace the traditional CPU in the middle and high grade to develop in the direction of better system performance, lower power consumption, lower cost, higher reliability and easier development in order to meet the interactive needs of people with GUI screen-centered multimedia interface and information terminals such as handwritten text input, identity recognition, voice dial-up Internet, sending and receiving e-mail, video playback, online games, videophone, language simultaneous interpretation and so on.SoC will embed enhanced processing devices such as 32-bit, 64-bit RISC chips or digital signal processing chips (DSP). At the same time, it supports the development of embedded RTOS and uses real-time multi-task programming technology and cross-development tool technology to control functional complexity to Inherit and develop computer processor technology. All of this poses greater challenges to computer architecture.   Under the guidance of computer architecture, SoC will usher in a new round of technical development. It takes embedded system application as the core, integrates software and hardware, and pursues the maximum inclusiveness of product system in system integration. SoC chip design not only needs strong background knowledge of computer architecture, but also highlights the status of software development, and puts forward higher requirements for development platform and embedded operating system. It provides a broad world for computer professionals to show their skills.   With the rapid development of processor / IP core design technology at home and abroad, it provides a powerful driving force for the development of computer architecture. Persisting in the development of processor core, core IP core and bus architecture with independent property rights, and ensuring compatibility, will make the development of SoC in China competitive thus driving the domestic IC industry to further develop. In order to meet the needs of industry, the of SoC designers’s in-depth researches on the architecture of configuration stream, instruction stream and data stream will also make a significant contribution to the development of computer science.   SoC opens up a new world for the development of interdisciplinary disciplines SoC is a new field of technology that needs the support of many disciplines. Its development has been inseparable from the technical support from computer science, microelectronics, materials and technology, electronic communications and other fields. New technology and new products will continue to emerge and more in-depth researches on SoC are needed.   At present, the development of SoC technology is mainly realized at the same process level, mainly electronic technology. However, in practical applications, higher requirements for microminiaturization and system integration technology are constantly put forward. The development of micro-systems that integrate micro-mechanisms, micro-sensors, micro-actuators, signal processing and control and communication interface circuits and energy, which can perform specific functions, has put on the agenda. MEMS, which combines microelectronics and micromechanics, will become a new basis for the development of SoC. MEMS is also a multidisciplinary frontier research field, involving electronic engineering, mechanical engineering, material engineering, information engineering, physics, chemistry, optics, biomedicine and other disciplines and technologies.   The obvious advantage of system integration is to inherit and develop the benefits of various process technologies. Although the development of various processes is extremely unbalanced, SiP (System in Package) design technology can be used to integrate various integrated circuits of different processes such as CMOS circuits, GaAs circuits, SiGe circuits or optoelectronic devices, MEMS devices, and various passive components such as capacitors, inductors, etc. into a package when multiple processes are needed to coexist in the process of system integration. The implementation of more complex systems in a single package can improve packaging efficiency, performance and reliability by about 10 times, and the size and cost can be greatly reduced.   The development trend of SoC technology will be the integration of SoC, MEMS and SiP, and the computer architecture will be constantly enriched and developed. SoC's CDI classification model can depict the development of system technology, meet the single chip requirements of more complex systems and promote the interdisciplinary development at the same time.   Related products XC7Z100-2FFG900I XC7Z010-1CLG400I    

A new type of radio frequency identification (RFID) chip has been developed that is virtually impossible to hack.If such chips were widely adopted, it could mean that an identity thief couldn't steal your credit card number or key card information by sitting next to you at a café, and high-tech burglars couldn't swipe expensive goods from a warehouse and replace them with dummy tags.Texas Instruments has built several prototypes of the new chip, to the researchers' specifications, and in experiments the chips have behaved as expected. The researchers presented their research this week at the International Solid-State Circuits Conference, in San Francisco.According to Chiraag Juvekar, a graduate student in electrical engineering at MIT and first author on the new paper, the chip is designed to prevent so-called side-channel attacks. Side-channel attacks analyze patterns of memory access or fluctuations in power usage when a device is performing a cryptographic operation, in order to extract its cryptographic key."The idea in a side-channel attack is that a given execution of the cryptographic algorithm only leaks a slight amount of information," Juvekar says. "So you need to execute the cryptographic algorithm with the same secret many, many times to get enough leakage to extract a complete secret."One way to thwart side-channel attacks is to regularly change secret keys. In that case, the RFID chip would run a random-number generator that would spit out a new secret key after each transaction. A central server would run the same generator, and every time an RFID scanner queried the tag, it would relay the results to the server, to see if the current key was valid.BlackoutSuch a system would still, however, be vulnerable to a "power glitch" attack, in which the RFID chip's power would be repeatedly cut right before it changed its secret key. An attacker could then run the same side-channel attack thousands of times, with the same key. Power-glitch attacks have been used to circumvent limits on the number of incorrect password entries in password-protected devices, but RFID tags are particularly vulnerable to them, since they're charged by tag readers and have no onboard power supplies.Two design innovations allow the MIT researchers' chip to thwart power-glitch attacks: One is an on-chip power supply whose connection to the chip circuitry would be virtually impossible to cut, and the other is a set of "nonvolatile" memory cells that can store whatever data the chip is working on when it begins to lose power.For both of these features, the researchers—Juvekar; Anantha Chandrakasan, who is Juvekar's advisor and the Vannevar Bush Professor of Electrical Engineering and Computer Science; Hyung-Min Lee, who was a postdoc in Chandrakasan's group when the work was done and is now at IBM; and TI's Joyce Kwong, who did her master's degree and PhD with Chandrakasan—use a special type of material known as a ferroelectric crystals.As a crystal, a ferroelectric material consists of molecules arranged into a regular three-dimensional lattice. In every cell of the lattice, positive and negative charges naturally separate, producing electrical polarization. The application of an electric field, however, can align the cells' polarization in either of two directions, which can represent the two possible values of a bit of information.When the electric field is removed, the cells maintain their polarization. Texas Instruments and other chip manufacturers have been using ferroelectric materials to produce nonvolatile memory, or computer memory that retains data when it's powered off.Complementary capacitorsA ferroelectric crystal can also be thought of as a capacitor, an electrical component that separates charges and is characterized by the voltage between its negative and positive poles. Texas Instruments' manufacturing process can produce ferroelectric cells with either of two voltages: 1.5 volts or 3.3 volts.The researchers' new chip uses a bank of 3.3-volt capacitors as an on-chip energy source. But it also features 571 1.5-volt cells that are discretely integrated into the chip's circuitry. When the chip's power source—the external scanner—is removed, the chip taps the 3.3-volt capacitors and completes as many operations as it can, then stores the data it's working on in the 1.5-volt cells.When power returns, before doing anything else the chip recharges the 3.3-volt capacitors, so that if it's interrupted again, it will have enough power to store data. Then it resumes its previous computation. If that computation was an update of the secret key, it will complete the update before responding to a query from the scanner. Power-glitch attacks won't work.Because the chip has to charge capacitors and complete computations every time it powers on, it's somewhat slower than conventional RFID chips. But in tests, the researchers found that they could get readouts from their chips at a rate of 30 per second, which should be more than fast enough for most RFID applications."In the age of ubiquitous connectivity, security is one of the paramount challenges we face," says Ahmad Bahai, chief technology officer at Texas Instruments. "Because of this, Texas Instruments sponsored the authentication tag research at MIT that is being presented at ISSCC. We believe this research is an important step toward the goal of a robust, low-cost, low-power authentication protocol for the industrial Internet."   

IBM is telling the world about something quite ambitious: TrueNorth's neurons could revolutionize system architecture. Dharmendra S. Modha, IBM Fellow, has given us the overview of what TrueNorth is all about in his report in IBM Research.Six years ago, he said, IBM and university partners began their effort to build a brain-inspired computer.Phase 0 turned into Phase 1, Phase 2, and Phase 3— from neuroscience to super computing to a new architecture, to a new programming language to algorithms, applications, and now, new chip, which is TrueNorth.He offered some numbers, which are bit daunting for those not accustomed to the "neuromorphic" world of computer research.Modha said, "we have shrunk the neurosynaptic core by 15-fold in area and 100-fold in power, and have tiled 4,096 cores via an on- IC chip network to create TrueNorth—with one million neurons and 256 million synapses."Cade Metz, Wired senior staff writer, went beyond the numbers to describe on Monday what he saw. "Dharmendra Modha walks me to the front of the room so I can see it up close. About the size of a bathroom medicine cabinet, it rests on a table against the wall, and thanks to the translucent plastic on the outside, I can see the computer chips and the circuit boards and the multi-colored lights on the inside. It looks like a prop from a '70s sci-fi movie, but Modha describes it differently. 'You're looking at a small rodent,' he says. He means the brain of a small rodent—or, at least, the digital equivalent."(The machine at the front of the room is really 48 separate machines, each built around its own TrueNorth processors, Metz wrote.)Not surprisingly, several websites took to the rodent comparison to report that IBM had come up with a "rat brain"-like chip that might power the phones of tomorrow.Modha, meanwhile, spelled out the applications that might result. "The architecture can solve a wide class of problems from vision, audition, and multi-sensory fusion."Making smartphones, as Wired put it, "hyper-smart"? That would be one effect. Modha said, "On one hand, with portable devices: think smart phones, sensor networks, self-driving automobiles, robots, public safety, medical imaging, real-time video analysis, signal processing, olfactory detection, and digital pathology. On the other hand, with synaptic supercomputers: —think multimedia processing on the cloud."Reporter Mike Murphy in Quartz on Tuesday talked about the technology itself which is turning the corner: "While current chips are excellent at analyzing information in sequential order, the new 'neuromorphic' types of chips Modha's team are working on are better suited to finding patterns in information—like the right side of the brain."Traditional chips follow instructions, whereas IBM's new chip manages 'spikes'—rather like spikes in electrical activity in an organic brain," Murphy said.TrueNorth, with all its comparisons, is not a brain but it is a step toward a digital brain. "Let's be clear: we have not built the brain, or any brain," said Modha in the IBM Research report. "We have built a computer that is inspired by the brain. The inputs to and outputs of this computer are spikes. Functionally, it transforms a spatio-temporal stream of input spikes into a spatio-temporal stream of output spikes."Collaboration with Samsung was critical in gaining access to their advanced 28nm foundry process, he said. This allowed balancing the low active power of the architecture with matching low power of the underlying silicon technology.He added, "I am immensely grateful to our 200+ collaborators since 2008—spanning eight IBM labs and fabs, five universities, one start-up, and two Department of Energy laboratories. Finally, DARPA's mandate, metrics, and investment were absolutely vital."