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What about using wax with a processor as part of a technique to stave off smartphone overheating? Can wax be the answer to the thermal problem confronting smartphones? That is the proposal coming from a University of Pensylvania and University of Michigan team of researchers, who have been studying ways to manage the chip performance of smartphones. Milo Martin, an associate professor with the University of Pennsylvania and his colleagues at the two schools believe the answer is in computational sprinting involving wax. "When someone cranks the chip well beyond its recommended speeds, the wax absorbs the extra heat coming off the silicon, and at 54 degrees Celsius, it starts to melt," said a report about their research in Wired. Small mobile devices don't have room for the large fans that cool a laptop. If mobile phones actually used all of their transistors at the same time, they would overheat. Only a portion of a smartphone chip's transistors can operate at once. If you hear the term "dark silicon" it refers to the large portions of a silicon chip that must remain off at a given time. As transistors get smaller, the heat problems may only get worse.This is where computational sprinting comes into view. Under the concept of computational sprinting, a chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip returns to nominal operation to cool down. The team from the two schools have been exploring computational sprinting for several years. This is a technique that uses all transistors at once, using the sprint-and-rest technique of periodic boosts.In 2012, the researchers presented a paper at the High Performance Computer Architecture (HPCA) symposium, where they noted how many mobile applications do not demand sustained performance; rather, they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, the authors explored activating otherwise powered-down cores for subsecond bursts of intense parallel computation.The authors concluded that "Although numerous engineering challenges remain (in cost, thermal materials, packaging, and power supply), our study indicates that it is feasible to capture the responsiveness of a 16W chip within the engineering constraints of a 1W mobile device via parallel computational sprinting."Back in 2012 they had wax in mind as a heat-spreading structure that includes an encapsulated phase change material—like candle wax—which would absorb heat by melting during the sprint, then slowly dissipate it by hardening while the device is at rest, according to a University of Michigan News Services report.This year, reported Wired, "they set up an Intel Core i7 test processor with a custom cooling system that could run comfortably at a maximum of 10 watts of power. In their tests, though, they would periodically boost the chip to 50 watts."That is enough to overheat the chip in seconds, "but it speeds up the chip's clock speed and it uses more transistors." The team thinks they could possibly boost the chip up to 100 watts for short periods, becoming very hot, and that is where the wax could absorb much of the heat quickly until it melts.Related products:KY56-KST2222KY56-KST06KY56-KSH2955 

The latest buzz in the information technology industry regards "the Internet of things"—the idea that vehicles, appliances, civil-engineering structures, manufacturing equipment, and even livestock would have their own embedded sensors that report information directly to networked servers, aiding with maintenance and the coordination of tasks.Realizing that vision, however, will require extremely low-power sensors that can run for months without battery changes—or, even better, that can extract energy from the environment to recharge.Last week, at the Symposia on VLSI Technology and Circuits, MIT researchers presented a new power converter chip that can harvest more than 80 percent of the energy trickling into it, even at the extremely low power levels characteristic of tiny solar cells. Previous experimental ultralow-power converters had efficiencies of only 40 or 50 percent.Moreover, the researchers' chip achieves those efficiency improvements while assuming additional responsibilities. Where its predecessors could use a solar cell to either charge a battery or directly power a device, this new chip can do both, and it can power the device directly from the battery.All of those operations also share a single inductor—the chip's main electrical component—which saves on circuit board space but increases the circuit complexity even further. Nonetheless, the chip's power consumption remains low."We still want to have battery-charging capability, and we still want to provide a regulated output voltage," says Dina Reda El-Damak, an MIT graduate student in electrical engineering and computer science and first author on the new paper. "We need to regulate the input to extract the maximum power, and we really want to do all these tasks with inductor sharing and see which operational mode is the best. And we want to do it without compromising the performance, at very limited input power levels—10 nanowatts to 1 microwatt—for the Internet of things."The prototype chip was manufactured through the Taiwan Semiconductor Manufacturing Company's University Shuttle Program.Ups and downsThe circuit's chief function is to regulate the voltages between the solar cell, the battery, and the device the cell is powering. If the battery operates for too long at a voltage that's either too high or too low, for instance, its chemical reactants break down, and it loses the ability to hold a charge.To control the current flow across their chip, El-Damak and her advisor, Anantha Chandrakasan, the Joseph F. and Nancy P. Keithley Professor in Electrical Engineering, use an inductor, which is a wire wound into a coil. When a current passes through an inductor, it generates a magnetic field, which in turn resists any change in the current.Throwing switches in the inductor's path causes it to alternately charge and discharge, so that the current flowing through it continuously ramps up and then drops back down to zero. Keeping a lid on the current improves the circuit's efficiency, since the rate at which it dissipates energy as heat is proportional to the square of the current.Once the current drops to zero, however, the switches in the inductor's path need to be thrown immediately; otherwise, current could begin to flow through the circuit in the wrong direction, which would drastically diminish its efficiency. The complication is that the rate at which the current rises and falls depends on the voltage generated by the solar cell, which is highly variable. So the timing of the switch throws has to vary, too.Electric hourglassTo control the switches' timing, El-Damak and Chandrakasan use an electrical component called a capacitor, which can store electrical charge. The higher the current, the more rapidly the capacitor fills. When it's full, the circuit stops charging the inductor.The rate at which the current drops off, however, depends on the output voltage, whose regulation is the very purpose of the chip. Since that voltage is fixed, the variation in timing has to come from variation in capacitance. El-Damak and Chandrakasan thus equip their chip with a bank of capacitors of different sizes. As the current drops, it charges a subset of those capacitors, whose selection is determined by the solar cell's voltage. Once again, when the capacitor fills, the switches in the inductor's path are flipped."In this technology space, there's usually a trend to lower efficiency as the power gets lower, because there's a fixed amount of energy that's consumed by doing the work," says Brett Miwa, who leads a power conversion development project as a fellow at the chip manufacturer Maxim Integrated. "If you're only coming in with a small amount, it's hard to get most of it out, because you lose more as a percentage. [El-Damak's] design is unusually efficient for how low a power level she's at.""One of the things that's most notable about it is that it's really a fairly complete system," he adds. "It's really kind of a full system-on-chip for power management. And that makes it a little more complicated, a little bit larger, and a little bit more comprehensive than some of the other designs that might be reported in the literature. So for her to still achieve these high-performance specs in a much more sophisticated system is also noteworthy."Related products:XC7Z100-2FFG900IXC7Z010-1CLG400IA2F200M3F-1FGG256 

By combining 3D holographic lithography and 2D photolithography, researchers from the University of Illinois at Urbana-Champaign have demonstrated a high-performance 3D microbattery suitable for large-scale on-chip integration with microelectronic devices."This 3D microbattery has exceptional performance and scalability, and we think it will be of importance for many applications," explained Paul Braun, a professor of materials science and engineering at Illinois. "Micro-scale devices typically utilize power supplied off-chip because of difficulties in miniaturizing energy storage technologies. A miniaturized high-energy and high-power on-chip battery would be highly desirable for applications including autonomous microscale actuators, distributed wireless sensors and transmitters, monitors, and portable and implantable medical devices.""Due to the complexity of 3D electrodes, it is generally difficult to realize such batteries, let alone the possibility of on-chip integration and scaling. In this project, we developed an effective method to make high-performance 3D lithium-ion microbatteries using processes that are highly compatible with the fabrication of microelectronics," stated Hailong Ning, a graduate student in the Department of Materials Science and Engineering and first author of the article, "Holographic Patterning of High Performance on-chip 3D Lithium-ion Microbatteries," appearing in Proceedings of the National Academy of Sciences."We utilized 3D holographic lithography to define the interior structure of electrodes and 2D photolithography to create the desired electrode shape." Ning added. "This work merges important concepts in fabrication, characterization, and modeling, showing that the energy and power of the microbattery are strongly related to the structural parameters of the electrodes such as size, shape, surface area, porosity, and tortuosity. A significant strength of this new method is that these parameters can be easily controlled during lithography steps, which offers unique flexibility for designing next-generation on-chip energy storage devices."Enabled by a 3D holographic patterning technique—where multiple optical beams interfere inside the photoresist creating a desirable 3D structure—the battery possesses well-defined, periodically structured porous electrodes, that facilitates the fast transports of electrons and ions inside the battery, offering supercapacitor-like power."Although accurate control on the interfering optical beams is required to construct 3D holographic lithography, recent advances have significantly simplified the required optics, enabling creation of structures via a single incident beam and standard photoresist processing. This makes it highly scalable and compatible with microfabrication," stated John Rogers, a professor of materials science and engineering, who has worked with Braun and his team to develop the technology."Micro-engineered battery architectures, combined with high energy material such as tin, offer exciting new battery features including high energy capacity and good cycle lives, which provide the ability to power practical devices," stated William King, a professor of mechanical science and engineering, who is a co-author of this work.   

Using microfluidic passages cut directly into the backsides of production field-programmable gate array (FPGA) devices, Georgia Institute of Technology researchers are putting liquid cooling right where it's needed the most - a few hundred microns away from where the transistors are operating.Combined with connection technology that operates through structures in the cooling passages, the new technologies could allow development of denser and more powerful integrated electronic systems that would no longer require heat sinks or cooling fans on top of the integrated circuits. Working with popular 28-nanometer FPGA devices made by Altera Corp., the researchers have demonstrated a monolithically-cooled chip that can operate at temperatures more than 60 percent below those of similar air-cooled chips.In addition to more processing power, the lower temperatures can mean longer device life and less current leakage. The cooling comes from simple de-ionized water flowing through microfluidic passages that replace the massive air-cooled heat sinks normally placed on the backs of chips."We believe we have eliminated one of the major barriers to building high-performance systems that are more compact and energy efficient," said Muhannad Bakir, an associate professor and ON Semiconductor Junior Professor in the Georgia Tech School of Electrical and Computer Engineering. "We have eliminated the heat sink atop the silicon die by moving liquid cooling just a few hundred microns away from the transistors. We believe that reliably integrating microfluidic cooling directly on the silicon will be a disruptive technology for a new generation of electronics."Liquid cooling has been used to address the heat challenges facing computing systems whose power needs have been increasing. However, existing liquid cooling technology removes heat using cold plates externally attached to fully packaged silicon chips - adding thermal resistance and reducing the heat-rejection efficiency.To make their liquid cooling system, Bakir and graduate student Thomas Sarvey removed the heat sink and heat-spreading materials from the backs of stock Altera FPGA chips. They then etched cooling passages into the silicon, incorporating silicon cylinders approximately 100 microns in diameter to improve heat transmission into the liquid. A silicon layer was then placed over the flow passages, and ports were attached for the connection of water tubes.In multiple tests - including a demonstration for DARPA officials in Arlington, Virginia - a liquid-cooled FPGA was operated using a custom processor architecture provided by Altera. With a water inlet temperature of approximately 20 degrees Celsius and an inlet flow rate of 147 milliliters per minute, the liquid-cooled FPGA operated at a temperature of less than 24 degrees Celsius, compared to an air-cooled device that operated at 60 degrees Celsius.Sudhakar Yalamanchili, a professor in the Georgia Tech School of Electrical and Computer Engineering and one of the research group's collaborators, joined the team for the DARPA demonstration to discuss electrical-thermal co-design."We have created a real electronic platform to evaluate the benefits of liquid cooling versus air cooling," said Bakir. "This may open the door to stacking multiple chips, potentially multiple FPGA chips or FPGA chips with other chips that are high in power consumption. We are seeing a significant reduction in the temperature of these liquid-cooled chips."The research team chose FPGAs for their test because they provide a platform to test different circuit designs, and because FPGAs are common in many market segments, including defense. However, the same technology could also be used to cool CPUs, GPUs and other devices such as power amplifiers, Bakir said.In addition to improving overall cooling, the system could reduce hotspots in circuits by applying cooling much closer to the power source. Eliminating the heat sink could allow more compact packaging of electronic devices - but only if electrical connection issues are also addressed.In a separate research project, Bakir's group has demonstrated the fabrication of copper vias that would run through the silicon columns that are part of the cooling structure fabricated on the FPGAs. Graduate student Hanju Oh, co-advised with College of Engineering Dean Gary May, fabricated high aspect ratio copper vias through the silicon columns, reducing the capacitance of the connections that would carry signals between chips in an array."The moment you start thinking about stacking the chips, you need to have copper vias to connect them," Bakir said. "By bringing system components closer together, we can reduce interconnect length and that will lead to improvements in bandwidth density and reductions in energy use."The cooling research was funded by DARPA's Microsystems Technology Office, through the ICECOOL program. At Georgia Tech, DARPA funds two major cooling and system integration projects, one called STAECool directed by George W. Woodruff School of Mechanical Engineering Professor Yogendra Joshi, and the other, called SuperCool, that is directed by Bakir. In collaboration with the STAECool effort, Bakir and Joshi, along with Professors Andrei Fedorov and Suresh Sitaraman from the School of Mechanical Engineering, developed a thermal design vehicle to emulate challenging power maps to test the benefits of microfluidic cooling."We have reached an important milestone that we hope to use as a stepping stone to reach other objectives," said Bakir. "There is still a big challenge ahead, but we expect this to allow much denser, higher-performance computing systems that will dissipate less power. We can think of many interesting applications for these cooling technologies."Altera's principal investigator for the project, Arifur Rahman, said: "Future high-performance semiconductor electronics will be increasingly dominated by thermal budget and ability to remove heat. The embedded microfluidic channels provide an intriguing option to remove heat from future microelectronics systems."   

It's only a centimeter long, it's placed under your skin, it's powered by a patch on the surface of your skin and it communicates with your mobile phone. The new biosensor chip developed at EPFL is capable of simultaneously monitoring the concentration of a number of molecules, such as glucose and cholesterol, and certain drugs.The future of medicine lies in ever greater precision, not only when it comes to diagnosis but also drug dosage. The blood work that medical staff rely on is generally a snapshot indicative of the moment the blood is drawn before it undergoes hours - or even days - of analysis.Several EPFL laboratories are working on devices allowing constant analysis over as long a period as possible. The latest development is the biosensor chip, created by researchers in the Integrated Systems Laboratory working together with the Radio Frequency Integrated Circuit Group. Sandro Carrara is unveiling it today at the International Symposium on Circuits and Systems (ISCAS) in Lisbon.Autonomous operation"This is the world's first chip capable of measuring not just pH and temperature, but also metabolism-related molecules like glucose, lactate and cholesterol, as well as drugs," said Dr Carrara. A group of electrochemical sensors works with or without enzymes, which means the device can react to a wide range of compounds, and it can do so for several days or even weeks.This one-centimetre square device contains three main components: a circuit with six sensors, a control unit that analyses incoming signals, and a radio transmission module. It also has an induction coil that draws power from an external battery attached to the skin by a patch. "A simple plaster holds together the battery, the coil and a Bluetooth module used to send the results immediately to a mobile phone," said Dr Carrara.Contactless, in vivo monitoringThe chip was successfully tested in vivo on mice at the Institute for Research in Biomedicine (IRB) in Bellinzona, where researchers were able to constantly monitor glucose and paracetamol levels without a wire tracker getting in the way of the animals' daily activities. The results were extremely promising, which means that clinical tests on humans could take place in three to five years - especially since the procedure is only minimally invasive, with the chip being implanted just under the epidermis."Knowing the precise and real-time effect of drugs on the metabolism is one of the keys to the type of personalised, precision medicine that we are striving for," said Dr Carrara.  

Japan's Toshiba is teaming up with US chip giant SanDisk to produce a "3D" memory chip they hope will allow users to save up to 50 hours of ultra-high definition video.In a deal worth a reported 500 billion yen ($4.84 billion) the companies will build a factory to make flash memory consisting of several layers of semiconductors stacked together to give as much as a terabyte—1,000 gigabytes—of storage.That is around 16 times bigger than the largest 64-gigabyte Toshiba memory currently available in smart phones and tablet devices.Toshiba will demolish its existing plant in Japan to build a new facility that will house production apparatus using technologies from both firms and which the firms hope will start operating in 2016, a statement said."In about five years (from the planned start of the factory), we would like to produce one-terabyte products," said a Toshiba spokeswoman.The plan comes at a time of increasing competition among the world's technology firms to meet demand for ever-higher capacity memory chips for consumers increasingly using mobile devices such as smart phones, tablet computers and wearable gadgets.The spread of high-definition video, with so-called 4K screens at the leading edge, is boosting demand for computing memory to store content."Small, high-capacity memories can of course be applied to smartphones, but they could also be used for wearable devices," the Toshiba spokeswoman said.Manufacturers have traditionally competed with regular chips by trying to make the physical object smaller.Toshiba, along with major rivals such as Samsung, believe they are reaching the physical limit, and are shifting toward 3D memories, where layering—effectively a third dimension—is used to boost the capacity of objects the same size.Yasuo Naruke, Toshiba senior vice president, said in a statement: "Our determination to develop advanced technologies underlines our commitment to respond to continued demand (for) flash memory."SanDisk president and chief executive Sanjay Mehrotra said the plant "will advance our leadership in memory technology into the 3D... era".