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Tokyo Tech researchers demonstrate operation energy-savings in a low price silicon power transistor structure by scaling down in all three dimensions. In electronics, lower power consumption leads to operation cost savings, environmental benefits and the convenience advantages from longer running devices. While progress in energy efficiencies has been reported with alternative materials such as SiC and GaN, energy-savings in the standard inexpensive and widely used silicon devices are still keenly sought.K Tsutsui at Tokyo Institute of Technology and colleagues in Japan have now shown that by scaling down size parameters in all three dimensions their device they can achieve significant energy savings.Tsutsui and colleagues studied silicon insulated gate bipolar transistors (IGBTs), a fast-operating switch that features in a number of every day appliances. While the efficiency of IGBTs is good, reducing the ON resistance, or the voltage from collector to emitter required for saturation (Vce(sat)), could help increase the energy efficiency of these devices further.Previous investigations have highlighted that increases in the “injection enhancement (IE) effect”, which give rise to more charge carriers, leads to a reduction in Vce(sat). Although this has been achieved by reducing the mesa width in the device structure, the mesa resistance was thereby increased as well.Reducing the mesa height could help counter the increased resistance but is prone to impeding the (IE) effect. Instead the researchers reduced the mesa width, gate length, and the oxide thickness in the MOSFET to increase the IE effect and so reduce Vce(sat) from 1.70 to 1.26 V. With these alterations the researchers also used a reduced gate voltage, which has advantages for CMOS integration.They conclude, “It was experimentally confirmed for the first time that significant Vce(sat) reduction can be achieved by scaling the IGBT both in the lateral and vertical dimensions with a decrease in the gate voltage.”These are three terminal devices used as switches or rectifiers. With simple gate-drive characteristics and high-current and low-saturation-voltage capabilities they combine the benefits of two other types of transistors - metal-oxide-semiconductor field effect transistors (MOSFETs) and bipolar transistors.The researchers reduced the mesa width, gate length, and the oxide thickness in the MOSFET by a factor of 1/k, and compared devices with values of 1 and 3 for k. Because the fabrication of narrow mesas can cause problems they also reduced the trench depth by 1/k.Although this has a slightly negative effect on the IE effect, it has considerable benefits for fabrication ease and cost and the dependence of (Vce(sat)) on the trench depth was deemed to be small. The gate voltage was also decreased by a factor of 1/k, while the cell pitch was maintained at 16 μm.Reference:2SA1987C4706FJA4213RTU

In an advance that helps pave the way for next-generation electronics and computing technologies—and possibly paper-thin gadgets —scientists with the U.S. Department of Energy's Lawrence Berkeley National Laboratory (Berkeley Lab) developed a way to chemically assemble transistors and circuits that are only a few atoms thick. What's more, their method yields functional structures at a scale large enough to begin thinking about real-world applications and commercial scalability. The scientists controlled the synthesis of a transistor in which narrow channels were etched onto conducting graphene, and a semiconducting material called a transition-metal dichalcogenide, or TMDC, was seeded in the blank channels. Both of these materials are single-layered crystals and atomically thin, so the two-part assembly yielded electronic structures that are essentially two-dimensional. In addition, the synthesis is able to cover an area a few centimeters long and a few millimeters wide. "This is a big step toward a scalable and repeatable way to build atomically thin electronics or pack more computing power in a smaller area," says Xiang Zhang, a senior scientist in Berkeley Lab's Materials Sciences Division who led the study. Zhang also holds the Ernest S. Kuh Endowed Chair at the University of California (UC) Berkeley and is a member of the Kavli Energy NanoSciences Institute at Berkeley. Other scientists who contributed to the research include Mervin Zhao, Yu Ye, Yang Xia, Hanyu Zhu, Siqi Wang, and Yuan Wang from UC Berkeley as well as Yimo Han and David Muller from Cornell University. Their work is part of a new wave of research aimed at keeping pace with Moore's Law, which holds that the number of transistors in an integrated circuit doubles approximately every two years. In order to keep this pace, scientists predict that integrated electronics will soon require transistors that measure less than ten nanometers in length. Transistors are electronic switches, so they need to be able to turn on and off, which is a characteristic of semiconductors. However, at the nanometer scale, silicon transistors likely won't be a good option. That's because silicon is a bulk material, and as electronics made from silicon become smaller and smaller, their performance as switches dramatically decreases, which is a major roadblock for future electronics. Researchers have looked to two-dimensional crystals that are only one molecule thick as alternative materials to keep up with Moore's Law. These crystals aren't subject to the constraints of silicon. In this vein, the Berkeley Lab scientists developed a way to seed a single-layered semiconductor, in this case the TMDC molybdenum disulfide (MoS2), into channels lithographically etched within a sheet of conducting graphene. The two atomic sheets meet to form nanometer-scale junctions that enable graphene to efficiently inject current into the MoS2. These junctions make atomically thin transistors. "This approach allows for the chemical assembly of electronic circuits, using two-dimensional materials, which show improved performance compared to using traditional metals to inject current into TMDCs," says Mervin Zhao, a lead author and Ph.D. student in Zhang's group at Berkeley Lab and UC Berkeley. Optical and electron microscopy images, and spectroscopic mapping, confirmed various aspects related to the successful formation and functionality of the two-dimensional transistors. In addition, the scientists demonstrated the applicability of the structure by assembling it into the logic circuitry of an inverter. This further underscores the technology's ability to lay the foundation for a chemically assembled atomic computer, the scientists say. "Both of these two-dimensional crystals have been synthesized in the wafer scale in a way that is compatible with current semiconductor manufacturing. By integrating our technique with other growth systems, it's possible that future computing can be done completely with atomically thin crystals," says Zhao. Reference: 2N3811 EMX2T2R DMA204020R  

In a development beneficial for both industry and environment, UC Santa Barbara researchers have created a high-quality coating for organic electronics that promises to decrease processing time as well as energy requirements."It's faster, and it's nontoxic," said Kollbe Ahn, a research faculty member at UCSB's Marine Science Institute and corresponding author of a paper published in Nano Letters.In the manufacture of polymer (also known as "organic") electronics—the technology behind flexible displays and solar cells—the material used to direct and move current is of supreme importance. Since defects reduce efficiency and functionality, special attention must be paid to quality, even down to the molecular level.Often that can mean long processing times, or relatively inefficient processes. It can also mean the use of toxic substances. Alternatively, manufacturers can choose to speed up the process, which could cost energy or quality.Fortunately, as it turns out, efficiency, performance and sustainability don't always have to be traded against each other in the manufacture of these electronics. Looking no further than the campus beach, the UCSB researchers have found inspiration in the mollusks that live there. Mussels, which have perfected the art of clinging to virtually any surface in the intertidal zone, serve as the model for a molecularly smooth, self-assembled monolayer for high-mobility polymer field-effect transistors—in essence, a surface coating that can be used in the manufacture and processing of the conductive polymer that maintains its efficiency.More specifically, according to Ahn, it was the mussel's adhesion mechanism that stirred the researchers' interest. "We're inspired by the proteins at the interface between the plaque and substrate," he said.Before mussels attach themselves to the surfaces of rocks, pilings or other structures found in the inhospitable intertidal zone, they secrete proteins through the ventral grove of their feet, in an incremental fashion. In a step that enhances bonding performance, a thin priming layer of protein molecules is first generated as a bridge between the substrate and other adhesive proteins in the plaques that tip the byssus threads of their feet to overcome the barrier of water and other impurities.That type of zwitterionic molecule—with both positive and negative charges—inspired by the mussel's native proteins (polyampholytes), can self-assemble and form a sub-nano thin layer in water at ambient temperature in a few seconds. The defect-free monolayer provides a platform for conductive polymers in the appropriate direction on various dielectric surfaces.Current methods to treat silicon surfaces (the most common dielectric surface), for the production of organic field-effect transistors, requires a batch processing method that is relatively impractical, said Ahn. Although heat can hasten this step, it involves the use of energy and increases the risk of defects.With this bio-inspired coating mechanism, a continuous roll-to-roll dip coating method of producing organic electronic devices is possible, according to the researchers. It also avoids the use of toxic chemicals and their disposal, by replacing them with water."The environmental significance of this work is that these new bio-inspired primers allow for nanofabrication on silicone dioxide surfaces in the absence of organic solvents, high reaction temperatures and toxic reagents," said co-author Roscoe Lindstadt, a graduate student researcher in UCSB chemistry professor Bruce Lipshutz's lab. "In order for practitioners to switch to newer, more environmentally benign protocols, they need to be competitive with existing ones, and thankfully device performance is improved by using this 'greener' method."Reference:KY56-2N3811KY56- EMX2T2RKY0-PEMZ1,115 

Transistors, the workhorses of the electronics world, are plagued by leakage current. This results in unnecessary energy losses, which is why smartphones and laptops, for example, have to be recharged so often. Tom van Hemert and Ray Hueting of the University of Twente's MESA+ Institute for Nanotechnology have shown that this leakage current can be radically reduced by "squeezing" the transistor with a piezoelectric material (which expands or contracts when an electrical charge is applied to it). Using this approach, they have smashed the theoretical limit for leakage current. Tom van Hemert will defend his PhD dissertation on 6 December.If silicon is squeezed, this affects the freedom of movement of the electrons in this material. This can promote or restrict the flow of electrical current. Compare it to a garden hose. When you stand on it, less water comes out. But strangely enough, the flow of electrons in silicon actually increases when the material is compressed.Only pinch when necessaryIn modern microchips, every single transistor is continuously exposed to enormous pressures of up to 10,000 atmospheres. This pressure is sealed in during the manufacturing process, by surrounding the transistors with compressive materials. While this boosts the chip's processing speed, the leakage current also increases. The use of piezoelectric material means that the transistors are only put under pressure when this is necessary. This can generate considerable savings in terms of energy consumption.Limit smashedThe underlying concept was originally developed by Ray Hueting. In order to turn this into reality, Tom van Hemert had to find a way of linking theories of mechanical deformation with quantum-mechanical formulas describing the electrical behaviour of transistors. The calculations indicate that "garden hose transistors" are much better than conventional transistors at switching from off to on. According to the classical theoretical limit, a charge of at least 60 millivolts is needed to make a transistor conduct ten times more electricity. The piezoelectric transistor uses just 50 millivolts. As a result, either the leakage current can be reduced, or more current can be carried in the on-state. Either way, this will boost the performance of modern microchips, while - importantly - cutting their energy consumption.Reference:KY56-2SA1987KY56-C4706KY56-2sb1647 

A newly-developed form of transistor opens up a range of new electronic applications including wearable or implantable devices by drastically reducing the amount of power used. Devices based on this type of ultralow power transistor, developed by engineers at the University of Cambridge, could function for months or even years without a battery by 'scavenging' energy from their environment.Using a similar principle to a computer in sleep mode, the new transistor harnesses a tiny 'leakage' of electrical current, known as a near-off-state current, for its operations. This leak, like water dripping from a faulty tap, is a characteristic of all transistors, but this is the first time that it has been effectively captured and used functionally. The results, reported in the journal Science, open up new avenues for system design for the Internet of Things, in which most of the things we interact with every day are connected to the Internet.The transistors can be produced at low temperatures and can be printed on almost any material, from glass and plastic to polyester and paper. They are based on a unique geometry which uses a 'non-desirable' characteristic, namely the point of contact between the metal and semiconducting components of a transistor, a so-called 'Schottky barrier.'"We're challenging conventional perception of how a transistor should be," said Professor Arokia Nathan of Cambridge's Department of Engineering, the paper's co-author. "We've found that these Schottky barriers, which most engineers try to avoid, actually have the ideal characteristics for the type of ultralow power applications we're looking at, such as wearable or implantable electronics for health monitoring."The new design gets around one of the main issues preventing the development of ultralow power transistors, namely the ability to produce them at very small sizes. As transistors get smaller, their two electrodes start to influence the behaviour of one another, and the voltages spread, meaning that below a certain size, transistors fail to function as desired. By changing the design of the transistors, the Cambridge researchers were able to use the Schottky barriers to keep the electrodes independent from one another, so that the transistors can be scaled down to very small geometries.The design also achieves a very high level of gain, or signal amplification. The transistor's operating voltage is less than a volt, with power consumption below a billionth of a watt. This ultralow power consumption makes them most suitable for applications where function is more important than speed, which is the essence of the Internet of Things."If we were to draw energy from a typical AA battery based on this design, it would last for a billion years," said Dr Sungsik Lee, the paper's first author, also from the Department of Engineering. "Using the Schottky barrier allows us to keep the electrodes from interfering with each other in order to amplify the amplitude of the signal even at the state where the transistor is almost switched off.""This will bring about a new design model for ultralow power sensor interfaces and analogue signal processing in wearable and implantable devices, all of which are critical for the Internet of Things," said Nathan.Reference:2SA19872sb1647FJA4213RTU  

Holst Centre, imec and their partner Evonik have realized a general-purpose 8-bit microprocessor, manufactured using complementary thin-film transistors (TFTs) processed at temperatures compatible with plastic foil substrates (250°C). The new "hybrid" technology integrates two types of semiconductors—metal-oxide for n-type TFTs (iXsenic, Evonik) and organic molecules for p-type TFTs—in a CMOS microprocessor circuit, operating at unprecedented for TFT technologies speed—clock frequency 2.1kHz. The breakthrough results were published online in Scientific Reports, an open access journal from the publisher of Nature.Low temperature thin-film electronics are based on organic and metal-oxide semiconductors. They have the potential to be produced in a cost effective way using large-area manufacturing processes on plastic foils. Thin-film electronics are, therefore, attractive alternatives for silicon chips in simple IC applications, such as radio frequency identification (RFID) and near field communication (NFC) tags and sensors for smart food packaging, and in large-area electronic applications, such as flexible displays, sensor arrays and OLED lamps. Holst Centre's (imec and TNO) research into thin-film electronics aims at developing a robust, foil-compatible, high performance technology platform, which is key to making these new applications become a reality.The novel 8-bit microprocessor performs at a clock frequency of 2.1 kHz. It consists of two separate chips: a processor core chip and a general-purpose instruction generator (P2ROM). For the processor core chip, a complementary hybrid organic-oxide technology was used (p:n ratio 3:1). The n-type transistors are 250°C solution-processed metal-oxide TFTs with typically high charge carrier mobility (2 cm2/Vs). The p-type transistors are small molecule organic TFTs with mobility of up to 1 cm2/Vs.The complementary logic allows for a more complex and complete standard cell library, including additional buffering in the core and the implementation of a mirror adder in the critical path. These optimizations have resulted in a high maximum clock frequency of 2.1kHz. The general-purpose instruction generator or P2ROM is a one-time programmable ROM memory configured by means of inkjet printing, using a conductive silver ink. The chip is divided into a hybrid complementary part and a unipolar n-TFT part and is capable of operating at frequencies up to 650 Hz, at an operational voltage of Vdd=10V.Reference:KY56-KST2222KY56-KST06KY56-KSP14