The Kynix Blog

Summary As is listed in the market,there is a little of small,inexpensive switch for latching power to a load unless you buy low-current,momentary action pushbotton switches like PCB-mount‘tactile types'. However, we can get a suitable latching power switch passing by converting a pushbutton's momentary action into a latching function.   New Design Idea Previous Design Ideas have proposed solutions based on discrete components  and IC-based circuits . The circuit outlined below, however, requires just two transistors and a handful of passive components to achieve the same result.   Circuit One The circuit in Figu1(a) is configured to latch power to a low-side (ground-referred) load. It works in 'toggle' mode; that is, the first switch closure applies power to the load, the second removes power, and so on. fig1  Circuit converts momentary action push switch into latching power switch     To understand how the circuit operates, assume that the DC power supply, +VS, has just been applied, capacitor C1 is initially uncharged, and Q1 is off. The P-channel MOSFET, Q2, is held in its off state by R1 and R3, which work in series to pull the gate up to +VS, such that VGS is zero. The circuit is now in its 'unlatched' state, where the load voltage, VL, at the OUT (+) terminal is zero.   If the normally-open push switch is momentarily closed, C1 – being uncharged – pulls Q2's gate to 0V, thus turning on the MOSFET. The load voltage at OUT (+) now rises immediately toward +VS , and Q1 receives base bias via R4 and turns on. Under these conditions, Q1 saturates and pulls Q2's gate low via R3, thus holding the MOSFET on when the switch has opened. The circuit is now in its 'latched' state, where both transistors are on, the load is energized, and C1 charges up to +VS via R2.   When the switch is momentarily closed for a second time, the voltage on C1 (by now approximately equal to +VS) is transferred to Q2's gate. Since Q2's gate-source voltage is now roughly zero, the MOSFET turns off and the load voltage falls to zero. Q1's base-emitter voltage also falls to zero and the transistor turns off. Therefore, when the switch is released, there is nothing to hold Q2 on, and the circuit reverts to its 'unlatched' state, where both transistors are off, the load is de-energized, and C1 discharges via R2. Resistor R5 across the output terminals is an optional component that acts as a pull-down. When the switch is released, C1 discharges via R2 into the load. If the load impedance is very high (i.e., similar in magnitude to R2), or if it contains active devices such as LEDs, the load voltage at the instant Q2 turns off may be large enough to bias Q1 on via R4, thereby preventing the circuit from turning off properly. The presence of R5 pulls the OUT (+) terminal down to 0V when Q2 turns off, thus ensuring that Q1 turns off rapidly, and allowing the circuit to revert to its unlatched state in a proper manner.   Provided the transistors are correctly rated, the circuit will work over a wide voltage range and is well suited to driving loads such as relays, solenoids, LEDs, and so on. However, beware that certain DC fans and motors continue to rotate when their drive power is removed. This rotation can generate an EMF large enough to bias Q1 on, thereby preventing the circuit from switching off. You can eliminate this problem by inserting a blocking diode in series with the output, as shown in Fig1(b). You must also include R5 to ensure Q1 turns off properly.   Ciruit Two The complementary circuit outlined in Fig2 is intended for 'high-side' loads connected to the positive supply rail such as the relay shown in this example. fig2 Complementary circuit intended for high-side loads   Note that Q1 has been replaced with a PNP transistor, and Q2 is now an N-channel MOSFET. The circuit operates in a similar way to the one described above. Here, R5 acts as a pull-up resistor which pulls the OUT (-) terminal up to +VS when Q2 turns off, thus ensuring that Q1 turns off quickly. As in the previous circuit, R5 is optional and only necessary for the types of load mentioned previously.   Note that in both circuits, the time constant produced by C1-R2 provides for debouncing of the push switch contacts. Normally, a value of 0.25s to 0.5s should be adequate. Smaller time constants may lead to erratic behaviour, whereas a larger time constant increases the waiting time between switch closures necessary to ensure that C1 charges and discharges properly. With C1 = 330nF and R2 = 1MΩ as shown, the time constant is nominally 0.33s. This is usually sufficient to debounce the contacts and to allow the load power to be toggled after a couple of seconds or so.   Both circuits are intended to latch and unlatch in response to brief, momentary switch closures. However, they have each been designed to ensure correct operation even if the push switch is held closed for any length of time. Consider the circuit in Fig2 when Q2 is on. When the switch is pressed to unlatch the circuit, the gate is pulled down toward 0V (since C1 is uncharged) and the MOSFET switches off, allowing  the junction of R1-R2 to rise toward +VS via R5 and the load impedance. At the same time, Q1 also switches off, such that Q2's gate is pulled to 0V via the series combination of R3 & R4. If the switch is released immediately, C1 will simply charge up toward +VS via R2. However, if the switch is kept closed, Q2's gate voltage will be defined by the potential divider formed mainly by R2 and R3+R4. If we assume that the OUT (-) terminal is roughly equal to +VS when the circuit is unlatched, Q2's gate-source voltage is given by: VGS = (+VS) × (R3 + R4)/(R2 + R3 + R4) = 0.02(+VS). Even if +VS is as high as 30V, the resulting gate-source voltage of around 0.6V will be too low to switch the MOSFET on again. Consequently, both transistors remain off until the switch contacts open.   The circuit in Fig2 is latched on by momentarily closing the push switch when C1 has charged up to +VS , which causes OUT (-) to drop to 0V as Q2 immediately turns on, rapidly followed by Q1. A momentary switch closure would allow C1 to discharge to zero via R2 after the contacts open. However, if the switch is held closed, Q2's gate voltage will be defined by the potential divider formed by R2 and R3. Since Q1 is saturated, the junction of R3-R4 at Q1's collector will be pulled up to +VS, and the junction of R1-R2 will be pulled down to 0V via Q2. Therefore, with the switch held closed, Q2's gate-source voltage is given by: VGS = (+VS) × R2/(R2 + R3) = 0.99(+VS). Consequently, provided the supply voltage is at least equal to Q2's gate-source threshold voltage, both Q2 and Q1 will remain on until the switch contacts open.   Both circuits provide an inexpensive way of deriving a latching function from a momentary switch and, just like a mechanical latching switch, the quiescent (unlatched) power dissipation is zero.

SummarryWhen I see this paper,The things occurred in my mind is that I need to let others to know it and prevent it.From morning until now,I always solve my computer's Trojans.This is terrible. Trojans may break our computer although it look like there doesn't matter.Trojans aren everywhere even the hardware in some instances, hardware Trojans could even open backdoors in custom silicon. BodyOutsourcing has reshaped the way electronics products are made – and helped to cut manufacturing costs massively. But, as production margins have fallen, so too has trust in the organisations that make up the supply chain. Companies which rely on outsourced manufacturing are having to come up with ways of ensuring that the products shipped to them have not had secure keys leaked or stuffed with viruses and compromised software. Even custom silicon is not safe.Almost a decade ago, researchers from Case Western Reserve University described to delegates at the IEEE High-Level Design Validation and Test Workshop the ways in which they could see hardware malware – or Trojans – being introduced to an IC-design project. The widespread use of foundry services, third-party intellectual property and standard-cell libraries – as well as designers bribed to make circuit-level changes – all provide ways in which Trojans could be sneaked into circuitry.Once it receives a trigger signal, the Trojan could open a backdoor to the group that wanted it introduced. In some use-cases, the Trojan may be introduced simply to compromise the product; no matter how it is used. However, the nature of IC design makes hardware Trojans difficult to deploy as they require skills and levels of access that are probably out of reach of most cybercriminals. But other, lower hanging, fruit remains available to them. State actors have the skills, access and motive that may make the surrepticious deployment of some kinds of silicon highly attractive to them. In practice, such organisations may not bother trying to introduce backdoors without the knowledge of the manufacturer or find other ways to make gain access to secrets. In 2015, the BBC identified declassified documents that confirmed the government convinced Crypto AG in the mid-1950s to compromise the security of its C-52 electromechanical encryption machines. Rather than making physical changes to the hardware itself, the company told the US National Security Agency (NSA) and the UK’s GCHQ which models target governments had bought – a practice that would allow the agencies to target decryption resources more effectively. In 2013, the NSA came under suspicion of encouraging the use of algorithms supplied by specialist RSA that had been subtly weakened to make decryption easier. While some ICs behave as if they have Trojans installed, in reality the backdoors were placed intentionally into the silicon by authorised designers. Usually, they are debug aids that were meant to stay secret, but often did not. Five years ago, Sergei Skorobogatov of the University of Cambridge and Christopher Woods of Quo Vadis Labs used side-channel emissions from the devices to uncover the key that would open the backdoor in the JTAG circuitry of an FPGA and to provide access to the encryption keys stored inside. Although side-channel emissions provide one way to determine whether an IC has been compromised with a backdoor, designers have other options available through the deployment of EDA techniques with Trojan detection in mind. As with anything in cybersecurity, a cat-and-mouse game has produced ever more subtle ways of introducing Trojans and more powerful ways of detecting them. The hardware Trojan is the subject of regular hacking competitions between research teams. For example, the Cyber Security Awareness Week (CSAW) organised by New York University has run several challenges around Trojans. In these challenges, red teams try to circumvent the detection mechanisms used by blue teams. 2013’s CSAW challenge focused on methods to beat FANCI, a largely effective detector developed at Columbia University and NYU. FANCI works on the basis that a Trojan would only have a loose connection to the design such that its logic would seem to be practically unreachable. Code-coverage analysis of the RTL can identify such unconnected lumps of circuitry and flag them up as possible Trojans. A couple of years later, the DeTrust technique created by Jie Zhang and colleagues at the Chinese University of Hong Kong showed one method for fooling FANCI: spreading the suspicious logic across many otherwise independent gates. Months later, Syed Haider and coworkers from the University of Connecticut developed the hardware Trojan catcher (HaTCH), designed to track down stealthier functions inserted at the logic level. Rather than isolate the Trojans before manufacture so they can be removed, HaTCH focuses on remediation. It adds tagging circuitry to legitimate cores that work to prevent any on chip Trojans from activating or succeeding in displaying malicious behaviour, such as opening a backdoor. A more wide-ranging technique that could serve as a defence against Trojans is to insist that all IP be supplied with formal proofs that describe the operations it would be allowed to perform. Any changes would be flagged by formal-verification tools during design and prototyping. Such approaches could still be vulnerable to attacks that tweak designs below the abstraction of RTL. As with the cases where the NSA is understood to have sought the help of manufacturers, weakened encryption is one of the most likely ways in which a practical hardware Trojan might work and evade detection by all but side-channel analysis. And it is possible using a tiny change at manufacture according. At the 2013 International Workshop on Cryptographic Hardware and Embedded Systems, Georg Becker and colleagues from the University of Massachusetts at Amherst showed a proof of concept that simply switched dopants used for one of the transistors in an inverter within a larger AOI standard cell (see figure 1). The result would be an inverter that generated a constant output.A transistor that no longer switched might be caught by a scan test looking for stuck-at faults. But embedded in a pseudorandom number generator, the inverter’s problem could be very hard to track down. Once there, the Amherst team estimated the fault could massively reduce the entropy of the random numbers it produced, resulting in very weak cryptographic keys. In 2014, Takeshi Sugawara of Mitsubishi Electric and a team from the company and Ritsumeikan University showed such a tiny change in manufacturing could be detected after the fact. A combination of focused ion beams and scanning electron microscopy can reveal the dopants diffused into the substrate. It is an expensive proposition, involving delayering of the design and extensive analysis against a layout that contains a map of the expected dopants. However, for the kinds of high-value cryptographic IC that might be the targets of well-financed attackers, it is arguably one more in a list of checks that are readily justified. As with other areas of embedded cybersecurity, the most feasible approach to dealing with the risk of hardware Trojans is one of focusing effort. Architectures such as Trustzone pull functions that need high levels of protection into a small portion of the overall SoC. In principle, this subset is much easier to verify than a design that calls for the either chip to analysed for vulnerabilities. If the secure core is guaranteed to not leak information or provide trapdoors, the value to an attacker of putting a Trojan in the more weakly protected part of the SoC diminishes greatly. For the user of SoCs and the buyer of IP to go into them, the question then becomes one of the level of expected risk and the degree of trust they can put in staff, suppliers and contractors.

SummaryFor years,people had treated the poor conductivity of organics as an unavoidable fact,and this shows that that is no always the case. Said Stephen Forrest,the Peter A. Franken Distinguished University Professor of Engineering and Paul G. Goebel Professor of Engineering at U-M, who led the research,which is  a way to coax electrons to travel much further than was previously thought possible in the materials often used for organic solar cells and other organic semiconductors under the condition of pushing cheap,ubiquitous solar power closer to reality. The fatal weakness of organic material may adjust its conductivityUnlike the inorganic solar cells widely used today, organics can be made of inexpensive, flexible carbon-based materials like plastic. Manufacturers could churn out rolls of them in a variety of colors and configurations, to be laminated unobtrusively into almost any surface. Organics’ notoriously poor conductivity, however, has slowed research. Forrest believes this discovery could change the game.  The team showed that a thin layer of fullerene molecules—the curious round carbon molecules also called Buckyballs—can enable electrons to travel up to several centimeters from the point where theyre knocked loose by a photon. That’s a dramatic increase; in today's organic cells, electrons can travel only a few hundred nanometers or less. But organic materials have much looser bonds between individual molecules, which can trap electrons. This has long been an Achilles’ heel of organics, but the new discovery shows that it may be possible to tweak their conductive properties for specific applications. The ability to make electrons move more freely in organic semiconductors The ability to make electrons move more freely in organic semiconductors could have far-reaching implications. For example, the surface of today's organic solar cells must be covered with a conductive electrode that collects electrons at the point where they’re initially generated. But freely moving electrons can be collected far away from their point of origination. This could enable manufacturers to shrink the conductive electrode into an invisible grid, paving the way for transparent cells that could be used on windows and other surfaces. “This discovery essentially gives us a new knob to turn as we design organic solar cells and other organic semiconductor devices,” said Quinn Burlingame, a U-M electrical engineering and computer science graduate researcher and author on the study. “The possibility of long-range electron transport opens up a lot of new possibilities in device architecture.” Burlingame says that the initial discovery of the phenomenon came as something of an accident as the team was experimenting with organic solar cell architecture in hopes of boosting efficiency. Using a common technique called vacuum thermal evaporation, they layered in a thin film of C60 fullerenes—each made of 60 carbon atoms—on top of an organic cell's power-producing layer, where the photons from sunlight knock electrons loose from their associated molecules. On top of the fullerenes, they put another layer to prevent the electrons from escaping. They discovered something they’d never seen before in an organic—electrons were skittering unfettered through the material, even outside the power-generating area of the cell. Through months of experimentation, they determined that the fullerene layer formed what's known as an energy well—a low-energy area that prevents the negatively charged electrons from recombining with the positive charges left behind in the power-producing layer.“You can imagine an energy well as sort of a canyon—electrons fall into it and can’t get back out,” said Caleb Cobourn, a graduate researcher in the U-M Department of Physics and an author on the study. “So they continue to move freely in the fullerene layer instead of recombining in the power-producing layer, as they normally would. It's like a massive antenna that can collect an electron charge from anywhere in the device.”Forrest cautions that widespread use of the discovery in applications like solar cells is theoretical at this point. But, he is excited by the discovery’s larger implications for understanding and exploiting the properties of organic semiconductors. “I believe that ubiquitous solar power is the key to powering our constantly warming and increasingly crowded planet, and that means putting solar cells on everyday objects like building facades and windows,” Forrest said. “Technology like this could help us produce power in a way that’s inexpensive and nearly invisible.” The study is titled “Centimeter-Scale Electron Diffusion in Photoactive Organic Heterostructures.” The research was supported by the U.S. Department of Energy SunShot Program and by the Air Force Office of Scientific Research.    Article from University of MichiganArticle edited by kynix 

SummaryAn innovative new method to engineer computer chips more easily and cheaper than conventioanl methods have been developed by researchers who from the University of Exeter.This new technique to produce cutting-edge,versatile microchips could revolutionize the speed,efficiency and capability of the next-gen of computers.About the researchThe discovery could revolutionise the production of optoelectronic materials – or devices that produce, detect and control light – which are vital to the next generation of renewable energy, security and defence technologies, the researchers said.Dr Anna Baldycheva, from Exeter's Centre for Graphene Science and author of the paper said:"This breakthrough will hopefully lead to a revolution in the development of vital new materials for computer electronics. The work provides a solid platform for the development of novel next-generation optoelectronic devices. Additionally, the materials and methods used are extremely promising for a wide range of further potential applications beyond the current devices." This innovative new research focused on developing a versatile,multi-functional technology to significantly enhance future computing capabilities. The team used microfluidics technology, which uses a series of minuscule channels in order to control the flow and direction of tiny amounts of fluid. For this research, the fluid contains graphene oxide flakes,that are mixed together in the channels, to construct the chips.While the graphene oxide flakes are two-dimensional- consisting of length and width only- the research team used a new sophisticated light-based system to drive the assembly of the three-dimensional chip structures.Crucially, the research team have analysed their methodology to not only confirm the technique is successful, but also to provide a blueprint for others to use to help manufacture the chips. "We are very excited about the potential of this breakthrough and look forward to seeing where it can take the optoelectronics industry in the future." added by professor Monica Craciun, co-author of the paper and Associate Professor of Nanoscience at Exeter.  This article provide by University of Exeter,and the research is  published in the respected journal Scientific Reports.Article edited by kynix. 

    This article shows how to use the buck converter for inverting or non-inverting voltage rails, and use it as an inverting buck-boost converter.     Catalog I. Brief Introduction II. Buck Converter III. Three DC/DC Converter Topologies 3.1 Isolated Buck Topology 3.2 Inverting Buck-boost (step-up and step-down)   Topology4 3.3 Isolated   Buck-boost Topology: +/- output5 FAQ   I. Brief Introduction   As we all known,power supply circuits come in the form of voltage step-up or step-down DC/DC converter. Nowadays,more and more applications require multiple voltage rails to drive ICs.The rails may be inverting,or non-inverting,with or without isolation.   While designers typically use multiple buck converters with single filter inductors, they add cost, footprint, and height. A simpler alternative is to use a single buck converter with coupled inductors or transformers configured in isolated converter topologies. Designers can use the buck converter for inverting or non-inverting voltage rails, and they can configure it for use as an inverting buck-boost converter.   Coupled inductors or transformers can also be used with a buck-boost converter to generate multiple inverting or non-inverting outputs with voltage step-up/down function. However, do you know what is isolated non-isolate DC/DC converter topologies? How they can be implemented using a single synchronous buck converter?   II. Buck Converter   A step-down transformer is a transformer that converts the higher voltage of the input end to the ideal voltage with relatively low output to achieve the purpose of reducing the pressure. A step-down transformer is a very important piece of equipment in the power transmission and transformation system.   Its normal operation is related to not only its own safety, but also the reliable power supply of users, and directly affects the stability of the power system. The protection configuration of the step-down transformer should satisfy in any case, the transformer can not be burned, the accident is enlarged, and the stability of the power system is affected. The principle of its work, the principle of relay protection, operation conditions, operation and requirements, and the abnormal operation and processing methods are introduced in detail. III. Three DC/DC Converter Topologies   The beauty of generating various converter topologies based on a single buck converter is that an optocoupler and its related circuitry are not required. This provides the benefit of a smaller footprint, lower component count, reduced complexity, and cost savings. Besides generating multiple outputs, the buck converter is configurable to operate as an inverting buck-boost converter, essentially providing a voltage step-up function. In addition, designers can create an isolated buck-boost converter using a similar concept.   3.1 Isolated Buck Topology A. +/- Step-down output: circuit operation1 An inverting and non-inverting step-down output can be generated with an isolated buck topology. Fig1 shows how it delivers a +/- output rail to any application that requires a positive and a negative supply. Fig1 Synchronous buck regulator uses isolated buck topology to generate ± Vout rail1   With reference to Fig1, the primary and secondary outputs are given by the following equations, assuming the leakage inductance of the coupled inductor or transformer and the DC resistance of the windings is negligible: where VIN is the input voltage, VO1 and VO2 are the primary and secondary outputs, respectively, D is the duty cycle, N is the turns ratio of the transformer, and Vdiode is the forward voltage drop across the diode.   During the cycle when the high side switch is on (current flow indicated by the green arrow in Fig1), the primary current ramps up and stores the energy in the magnetizing inductance of the transformer and the primary output capacitor. The diode on the secondary side is reverse biased and the load current on the secondary side is supplied by the output capacitor.   During the cycle when the low side switch is on (current flow indicated by the red arrow in Fig1), the primary current ramps down and releases the stored energy in the magnetizing inductance of the transformer, and the load current on the primary side is supplied by the output capacitor.   The diode on the secondary side is forward biased and the current flows from the transformer to supply current to the load, and charges up the secondary output capacitor. At steady state, the voltage at the secondary output is proportionally inverted compared to the voltage at the primary output, assuming the diode voltage drop, transformer winding resistance, and leakage inductances are negligible. Fig2 shows the operating waveforms for this architecture.   Fig2 Operating waveforms for a +/- step-down design1   B. +/+ step-down output2 Employing the same concept of generating secondary outputs using a coupled inductor or transformer, the secondary side can be configured differently to generate positive or negative secondary voltages. To generate a positive secondary output, the polarities of the transformer/coupled inductor as well as the secondary side diode are reversed. Fig3 shows an isolated buck topology to generate a dual +VOUT rail. Fig3 Isolated buck topology to generate a dual + VOUT rail2 C. +/+/- step-down output3 Fig4 shows an isolated buck topology to generate three outputs (dual +VOUT and single –VOUT rail). For a multiple output configuration, the total current of the various outputs reflected to the primary side must accounted for to make sure the IC is able to handle the resultant current. Fig4 Isolated buck topology to generate three outputs, dual +VOUT and single –VOUT rail3 The equations for the above circuit are as given below: Where VO1 is the primary output and VO2 and VO3 are the positive and negative secondary outputs, respectively, D is the duty cycle, N1 and N2 are the turns ratio of the transformer for VO2 and VO3, respectively. Vdiode is the forward voltage drop across the diode. IOUT1, IOUT2, and IOUT3 are the output current drawn from VO1, VO2, and VO3, respectively, IDS_pk is the peak current through the top switch and Δi is the triangular portion of the primary inductor ripple current.   3.2 Inverting Buck-boost (step-up and step-down) Topology4 An inverting buck-boost converter can be derived from the synchronous buck converter by connecting its GND terminal as the negative output of the buck-boost converter and the VOUT terminal of the buck converter as the GND of the buck-boost converter. Fig5 shows the circuit diagram of configuring the ISL85415 buck switcher as an inverting buck-boost converter. FigConfiguring a buck converter into an inverting buck-boost converter4 The equation for output voltage and output current are as follows: where VIN is the input voltage, VO1 is the output voltage, D is the duty cycle, IOUT is the output current, and IL is the inductor current.   During the cycle when the high side switch is on (current flow indicated by the green arrow in Fig5), the inductor current ramps up and stores energy in the inductor, and the output capacitor provides current to the load.    During the cycle when the low side switch is on (current flow indicated by the red arrow in Fig5), the inductor current ramps down and provides current to the load as well as charges the output capacitor. Operating waveforms for the inverting buck-boost design are shown in Fig6.     Fig6 Operating waveforms for an inverting buck-boost design4   3.3 Isolated Buck-boost Topology: +/- output5 A ± step-up/down output voltage can be realized using the isolated buck-boost topology. The filter inductor can be replaced with a transformer (or coupled inductor) to obtain a positive secondary output. Fig7 shows an isolated buck-boost topology to generate a ± step-up/down VOUT rail. Fig8 shows the operating waveforms for the isolated buck-boost design.   Fig7 Isolated buck-boost topology to generate a ± VOUT rail5 The voltage and current equations for the above circuit are given below: where VIN is the input voltage, VO2 is the secondary output voltage, Vdiode is the forward voltage drop across the diode, D is the duty cycle, N is the turns ratio of the transformer, IDS_pk is the peak current through the top switch, Δi is the triangular portion of the primary inductor ripple current, and IOUT1 and IOUT2 are the output current drawn from VO1 and VO2, respectively. Fig8 Operating waveforms for an Isolated buck-boost Topology: +/- output5 FAQ   1. What does a buck converter do? The buck converter is a very simple type of DC-DC converter that produces an output voltage that is less than its input. The buck converter is so named because the inductor always “bucks” or acts against the input voltage. The output voltage of an ideal buck converter is equal to the product of the switching duty cycle and the supply voltage. Like many power supply topologies, the buck converter operates on the principal of storing energy in an inductor. The voltage drop across an inductor is proportional to changes in electric current flowing through the device. 2. What is principle of Buck-boost converter? A Buck-Boost converter transforms a positive DC voltage at the input to a negative DC voltage at the output. The circuit operation depends on the conduction state of the MOSFET: On-state: The current through the inductor increases and the diode is in blocking state. 3. Are buck converters safe? A buck converter is probably no less reliable than most other topologies. It usually comes down to the reliability of the solder joints. The thing to remember about buck regulators is; if the series switch transistor fails SC - it dumps the full unregulated voltage into the load. 4. Are buck converters efficient? Buck converters can be highly efficient (often higher than 90%), making them useful for tasks such as converting a computer's main (bulk) supply voltage (often 12 V) down to lower voltages needed by USB, DRAM and the CPU (5V, 3.3V or 1.8V, see PSU). 5. How do buck converters work? The buck Converter circuit consists of the switching transistor, together with the flywheel circuit (Dl, L1 and C1). While the transistor is on, current is flowing through the load via the inductor L1. The action of any inductor opposes changes in current flow and also acts as a store of energy. 6. Do buck converters waste power? In a buck or boost converter, some energy is transferred directly from the source to the load as well, but the same principle applies. You can also look at a buck converter as an L-C filter on a square wave from the source. Again, all components are lossless, so there's no waste. 7. Does a buck converter limit current? The buck converter must operate at a very small duty cycle to keep the inductor current below the peak current limit threshold. ... Valley Current Limiting: Provides an additional level of protection. You can implement valley current limiting by sensing the inductor current when the low-side switch is on. 8. How do you adjust the current in a buck converter? You don't "adjust" output current. Loads draw whatever amount of current they need, provided the power supply can deliver it. If your total load exceeds the buck converter's rating of 3A, then you will be overloading it. If your total load is less than 3A, then you need not adjust anything. 9. How do you control a buck converter? A Buck converter consists of a transistor and diode that applies the supply voltage on an inductor capacitor, LC, circuit. The output voltage is the voltage across the capacitor. The input voltage u on the LC circuit is controlled by pulse width modulation, PWM. 10. What is the difference between buck and boost converter? In PV applications, generally, a Buck converter is used to charge the battery (since the output from a Buck converter is supposed to be less than its input), while a Boost converter is used to "match the load voltage" from the (supposedly) low voltage PV input.  

Summary As the emergence of a range of electronic technologies appear,major changes in the design of real-time embedded systems like the internet of things,augmented reality,or artificial intelligence occurred. The unifying thread between all of them is a greater focus on the use of distributed systems coupled with a need for high performance to deal with the data they generate and consume. Different design direction There are tensions that pull the engineering of real-time devices employing such technologies in different directions. Edge devices such as IoT sensor nodes and gateways call for the lowest-power operation.However,It's not the only area that needs energy efficiency. Despite their reliance on high-performance graphics and responsiveness to movement, AR-enabled systems (such as head-up displays for machine operators) also have to preserve as much energy as possible, protecting battery life and preventing head-mounted displays from becoming uncomfortably warm. Similarly, versatile robots enabled by AI need to be able to operate away from mains power. Distributed processing allows intensive computational work to be moved to the cloud and so offload the embedded systems. However, the real-time nature of these applications calls for low latency. Applications such as motion control and AR suffer if the delay from input to response is too long. This issue is leading to the deployment of edge computing server or ‘cloudlets’ - efficient server blades located relatively close to the edge devices themselves. To support real-time applications such cloudlets are in a position to take advantage of changes in memory technology to better fit the real-time nature of the clients they serve than traditional server designs. Historically, engineers have been forced to choose between performance and persistence when designing bulk memories into real-time computer systems. DRAM is cost-effective for storing large amounts of data close to the processor but is volatile. To ensure data is not lost through power issues - which are more likely to occur in edge nodes - data often has to be copied to persistent storage, which have often much slower access times.The move from rotating disk drives to flash memory for larger applications has already helped significantly when it comes to read access times. But flash still has its drawbacks when it comes to write performance. The erasing and rewriting of data from/to flash memory takes multiple cycles during which high-voltage pulses are delivered to the target memory cells. That takes both time and energy that system designers do not want to waste.   Next generation memory technologies Next generation memory technologies are now appearing that overcome the write delays and power demands of flash. These technologies include ferroelectric memory, phase-change memory (PCM), magnetic random-access memory (MRAM) and resistive random-access memory (ReRAM). As devices based on these concepts become available, engineers can consider using them in novel memory hierarchies that optimise cost, increase resilience and improve real-time responsiveness. Here we may mention that PCM,which was first put forward as a possible memory material as long ago as the 1970s,It is based on the same group of chalcogenide materials as those used in rewritable optical disks. A useful feature of the chalcogenides is the way they react to heat. High-current pulses will melt the material. If left to cool quickly it turns to a resistive amorphous state. But the amorphous state can be converted to a crystalline form with a much higher conductivity by applying a small amount of heat. Thanks to this change in properties, readout circuitry can interpret the difference in resistivity between cells as representing ones and zeros. Though similar in behaviour to PCM, with the same core approach of switching between high-resistance and low-resistance states, ReRAM uses different materials to chalcogenide. Typically, the movement of ions within the cell under the influence of pulses of current forms conductive filaments. Reset pulses disrupt these filaments, greatly increasing resistance. One potential advantage of ReRAM is that a large number of candidate materials could be chosen to implement them. This provides the scope for manufacturers to introduce memories with different levels of resilience and storage time. Although these memories use current pulses, the total charge required to program a cell is much lower than that required for flash. In the memories being developed today, ReRAM requires less write energy than PCM but the write times are similar. However, endurance is better in PCM than ReRAM and PCM currently lies further ahead on the development path. Experts believe both PCM and ReRAM will scale better than flash in the long term and so could ultimately supplant flash entirely.   about Ferroelectric Memory Ferroelectric memory and MRAM use the spin properties of electrons for storage. The spin can be controlled with very little energy through a spin-valve structure similar to that used in high-density read heads for magnetic disks. In an MRAM, this spin valve is made from a sandwich of materials formed in a via that lies between two metal interconnect lines on the surface of an integrated circuit (IC). The valve alters the resistance of the via based on the spin states of different materials in the sandwich.Ferroelectric memory has been available for several decades but in comparatively low densities to those envisaged for the resistance-based memories. Ferroelectric memory requires both a capacitor and transistor to be formed on the base layer of the wafer. The other memories are all formed in the metal interconnect layers and, potentially, can be stacked for higher integration.What's more,a key advantage  for ferroelectric memory is its use of materials that polarise in two different directions based on an applied electric field. This polarisation requires even less power than is needed for MRAM, which makes it suitable for systems that need to be highly energy efficient.   The potential problem A potential problem for all the novel memories today is that they lack the cost-effectiveness and density of flash, which is now beginning to take advantage of 3D manufacturing techniques. In reality, for cloudlets and also edge devices themselves, the density is not a major issue as these memories can serve as the underpinning for persistent caches. The low-power and relatively fast write times of the novel memories provides applications with the ability to copy important data to the persistent cache. Data objects that need to be stored permanently can, from there, be copied to flash or disk storage. However, there is no longer any need to transfer data to flash or disk storage continually just to ensure that important but transient data is not lost. When the system restarts, it can recover its state from combining data in both the permanent and persistent arrays.As costs come down and performance improves, there is the potential for MRAM, PCM or ReRAM to begin to displace DRAM and so move the architecture to one in which only the caches on the processors themselves employ a volatile memory architecture (such as SRAM).Persistent memory technologies need not be isolated to cloudlets and high-performance systems. The use of ferroelectric memory by Texas Instruments in its MSP430 line of microcontrollers provides an example of the impact it can have in IoT edge nodes such as sensors. Many IoT applications will rely on energy harvesting to at least supplement a built-in battery. Some may dispense with the battery altogether. The problem with energy harvesting is one of reliability. There are situations, such as vibrational energy capture on heavily used industrial machinery, where the power source is predictable. But in many cases, even with the use of a supercapacitor for an energy reservoir, the system may run temporarily short of power and need to shut down. When enough external energy is supplied, it can resume normal duties.The use of ferroelectric technology provides the microcontroller with the ability to ensure data persists through unexpected power outages without incurring an energy penalty even when data is written to it frequently.