transistor Related Articles

Holst Centre, imec and their partner Evonik have realized a general-purpose 8-bit microprocessor, manufactured using complementary thin-film transistors (TFTs) processed at temperatures compatible with plastic foil substrates (250°C). The new "hybrid" technology integrates two types of semiconductors—metal-oxide for n-type TFTs (iXsenic, Evonik) and organic molecules for p-type TFTs—in a CMOS microprocessor circuit, operating at unprecedented for TFT technologies speed—clock frequency 2.1kHz. The breakthrough results were published online in Scientific Reports, an open access journal from the publisher of Nature.Low temperature thin-film electronics are based on organic and metal-oxide semiconductors. They have the potential to be produced in a cost effective way using large-area manufacturing processes on plastic foils. Thin-film electronics are, therefore, attractive alternatives for silicon chips in simple IC applications, such as radio frequency identification (RFID) and near field communication (NFC) tags and sensors for smart food packaging, and in large-area electronic applications, such as flexible displays, sensor arrays and OLED lamps. Holst Centre's (imec and TNO) research into thin-film electronics aims at developing a robust, foil-compatible, high performance technology platform, which is key to making these new applications become a reality.The novel 8-bit microprocessor performs at a clock frequency of 2.1 kHz. It consists of two separate chips: a processor core chip and a general-purpose instruction generator (P2ROM). For the processor core chip, a complementary hybrid organic-oxide technology was used (p:n ratio 3:1). The n-type transistors are 250°C solution-processed metal-oxide TFTs with typically high charge carrier mobility (2 cm2/Vs). The p-type transistors are small molecule organic TFTs with mobility of up to 1 cm2/Vs.The complementary logic allows for a more complex and complete standard cell library, including additional buffering in the core and the implementation of a mirror adder in the critical path. These optimizations have resulted in a high maximum clock frequency of 2.1kHz. The general-purpose instruction generator or P2ROM is a one-time programmable ROM memory configured by means of inkjet printing, using a conductive silver ink. The chip is divided into a hybrid complementary part and a unipolar n-TFT part and is capable of operating at frequencies up to 650 Hz, at an operational voltage of Vdd=10V.Reference:KY56-KST2222KY56-KST06KY56-KSP14  

The electronics world has been dreaming for half a century of the day you can roll a TV up in a tube. Last year, Samsung even unveiled a smartphone with a curved screen—but it was solid, not flexible; the technology just hasn't caught up yet.But scientists got one step closer last month when researchers at the U.S. Department of Energy's Argonne National Laboratory reported the creation of the world's thinnest flexible, see-through 2-D thin film transistors.These transistors are just 10 atomic layers thick—that's about how much your fingernails grow per second.Transistors are the basis of nearly all electronics. Their two settings—on or off—dictate the 1s and 0s of computer binary language. Thin film transistors are a particular subset of these that are typically used in screens and displays. Virtually all flat-screen TVs and smartphones are made up of thin film transistors today; they form the basis of both LEDs and LCDs (liquid crystal displays)."This could make a transparent, nearly invisible screen," said Andreas Roelofs, a coauthor on the paper and interim director of Argonne's Center for Nanoscale Materials. "Imagine a normal window that doubles as a screen whenever you turn it on, for example."To measure how good a transistor is, you measure its on-off ratio—how completely can it turn off the current?—and a property called "field effect carrier mobility," which measures how quickly electrons can move through the material."We were pleased to find that the on/off ratio is just as good as current commercial thin-film transistors," said Argonne postdoctoral scientist and first author Saptarshi Das, "but the mobility is a hundred times better than what's on the market today."The team also tried bending the films to test what happens under stress. In most thin film transistors, the material starts to crack, which, as you might imagine, affects performance. "But in ours, the properties didn't change at all," Roelofs said. "The layers just slide and don't crack."The transistors also maintained performance over a wide range of temperatures (from -320°F to 250°F), a useful property in electronics, which can run very hot.To build the transistors, the team started with a trick that earned its original University of Manchester inventors the Nobel Prize: using a strip of scotch tape to peel off a sheet of tungsten diselenide just atoms thick."We chose tungsten diselenide because it provides the electron and hole conduction necessary for making transistors with logic gates and other p-n junction devices," said Argonne scientist and coauthor Anirudha Sumant.Then they used chemical deposition to grow sheets of other materials on top to build the transistor layer by layer. The final product is 10 atomic layers thick. (See sidebar for an illustration).Next, the team is interested in adding logic and memory to flexible films, so you could make not just a screen but an entire flexible and transparent TV or computer."However, more work needs to be done in developing large-area synthesis of tungsten selenide to realize the true potential for applications of our work," said Sumant.    

VTT Technical Research Centre of Finland has developed a method for the manufacture of thin film transistors using a roll-to-roll technique only. Thin film transistors can now be manufactured using roll-to-roll techniques, such as printing, for the deposition of patterns on the substrate layer of film. This is set to expand the range of electronic components and products, while slashing their production costs. Thin film transistors are more suitable than traditional silicon chip transistors for applications such as large-surface display screens, certain sensor applications, toys, games and smart cards.A transistor is a basic electronic component which can function as an electrical switch, an amplifier or a memory element. For transistor technology, roll-to-roll fabrication techniques have a range of advantages. These include the possibility to use large surface areas, as well as mechanical flexibility, transparency and low production start-up costs. Until now, production of thin film transistors has typically been only partly based on roll-to-roll techniques, resulting in fairly high mass production costs.As the technology matures, it is predicted that the markets for thin film transistors will grow from their current value of three million dollars to around 180 million over the next decade.VTT has developed thin film transistor production techniques as part of the EU POLARIC research project. With the aid of a special self-aligning technique, the method under development eliminates the challenge of aligning the patterns in the different thin film layers accurately against each other in the roll-to-roll process. In addition, the pattern size for transistor components is pushed to the limit of minuteness possible for printing techniques; this means patterns of a few dozen micrometres at their tiniest..Producing thin film transistors using a self-aligning roll-to-roll manufacturing process is one of the few demonstrations internationally so far. Initial experiences of this thin film transistor manufacturing process are promising. It provides VTT with the ideal basis for using the process to test thin film materials as they develop, to develop more complex electronic circuits and to trial various applications. The goal is to keep developing the technology until it matures enough to provide a springboard for new business activities. VTT is now seeking companies interested in developing applications based on printed thin film transistors. 

Researchers from the University of Twente MESA+ research institute, together with the company SolMateS, have developed a new type of transistor to reduce the power consumption of microchips. The basic element of modern electronics, namely the transistor, suffers from significant current leakage. By enveloping a transistor with a shell of piezoelectric material, which distorts when voltage is applied, researchers were able to reduce this leakage by a factor of five (compared to a transistor without this material). An article presenting the prototype of the transistor appears in the June issue of IEEE Transactions on Electron Devices, an authoritative scientific journal in the field of transistor research.Current leakage in transistors is one of the causes of battery depletion in portable electronic devices, such as smartphones and laptops. With the new type of transistor, either the current leakage (while the transistor is not active) or the energy consumption (while the transistor is active) can be addressed. In the latter case, it is estimated that energy consumption can be reduced by approximately 10%.Intelligent squeezingThe trick lies in a piezoelectric material which is applied to the exterior of the transistor. The piezoelectric material expands when you apply a voltage to it and compresses the silicon in the transistor with a pressure of about 10,000 atmospheres. This high pressure ensures that electrons flow through the transistor faster. You can therefore make microchips more efficient by 'intelligently squeezing the transistor'.Incidentally, existing transistors are already put under high pressure in order to improve their efficiency. In this case, however, the pressure is permanently built in, which actually increases the current leakage. In the prototype designed by the UT, the transistor is only put under pressure when required and this makes a big difference. The electric current needed to switch the transistor from on to off is thereby partly replaced by mechanical tension.CrudeAccording to dr. ir. Ray Hueting from the chair Semiconductor Components, this is an initial prototype that can already produce energy savings. "The design is still fairly crude where the material is concerned. With the further development of the transistor, it should therefore be possible to achieve a further significant increase in efficiency."The operating principle of this transistor was theoretically predicted in 2013 by the same research group. But in advance it was by no means certain that the transistor would be a success. The reason for this is that piezoelectric materials and silicon (which transistors are made of) are difficult to combine. The researchers solved this by inserting a buffer layer between the two materials.    

A new type of transistor that could make possible fast and low-power computing devices for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultra-mobile computing is feasible, according to Penn State researchers. Called a near broken-gap tunnel field effect transistor (TFET), the new device uses the quantum mechanical tunneling of electrons through an ultrathin energy barrier to provide high current at low voltage.Penn State, the National Institute of Standards and Technology and IQE, a specialty wafer manufacturer, jointly presented their findings at the International Electron Devices Meeting in Washington, D.C. The IEDM meeting includes representatives from all of the major chip companies and is the recognized forum for reporting breakthroughs in semiconductor and electronic technologies.Tunnel field effect transistors are considered to be a potential replacement for current CMOS transistors, as device makers search for a way to continue shrinking the size of transistors and packing more transistors into a given area. The main challenge facing current chip technology is that as size decreases, the power required to operate transistors does not decrease in step. The results can be seen in batteries that drain faster and increasing heat dissipation that can damage delicate electronic circuits. Various new types of transistor architecture using materials other than the standard silicon are being studied to overcome the power consumption challenge."This transistor has previously been developed in our lab to replace MOSFET transistors for logic applications and to address power issues," said lead author and Penn State graduate student Bijesh Rajamohanan. "In this work we went a step beyond and showed the capability of operating at high frequency, which is handy for applications where power concerns are critical, such as processing and transmitting information from devices implanted inside the human body." For implanted devices, generating too much power and heat can damage the tissue that is being monitored, while draining the battery requires frequent replacement surgery. The researchers, led by Suman Datta, professor of electrical engineering, tuned the material composition of the indium gallium arsenide/gallium arsenide antimony so that the energy barrier was close to zero—or near broken gap, which allowed electrons to tunnel through the barrier when desired. To improve amplification, the researchers moved all the contacts to the same plane at the top surface of the vertical transistor.This device was developed as part of a larger program sponsored by the National Science Foundation through the Nanosystems Engineering Research Center for Advanced Self-Powered Systems of Integrated Sensors and Technologies (NERC-ASSIST). The broader goal of the ASSIST program is to develop battery-free, body-powered wearable health monitoring systems with Penn State, North Carolina State University, University of Virginia, and Florida International University as participating institutions.   

One of the greatest challenges in the evolution of electronics has been to reduce power consumption during transistor switching operation. In a study recently reported in Nature, engineers at University of California, Santa Barbara, in collaboration with Rice University, have demonstrated a new transistor that switches at only 0.1 volts and reduces power dissipation by over 90% compared to state-of-the-art silicon transistors (MOSFETs).     MOSFETs have been the building blocks of everyday electronic products since the 1970s. However, to sustain the ever-growing need for increased transistor densities, miniaturization of MOSFETs has given rise to a power dissipation challenge due to the fundamental limitations of their turn-on characteristics. "The steepness of a transistor's turn-on is characterized by a parameter known as the subthreshold swing, which cannot be lowered below a certain level in MOSFETs," explained Kaustav Banerjee, Professor of Electrical and Computer Engineering at UC Santa Barbara. A minimum gate voltage change of 60 millivolts at room temperature is required to change the current by a factor of ten in MOSFETs. In essence, the existing state of transistor technology limits the energy efficiency potential of digital circuits in general. The research group of Professor Kaustav Banerjee at UC Santa Barbara took a new approach to subverting this fundamental limitation. They employed the quantum mechanical phenomenon of band-to-band tunneling to design a tunnel field effect transistor (TFET) with sub-60mV per decade of subthreshold swing. "We restructured the transistor's source to channel junction to filter out high energy electrons that can diffuse over the source/channel barrier even in the off state, thereby making the off state current negligibly small," explained Banerjee. At UCSB, Banerjee's Nanoelectronics Research Lab includes Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, and Stephan Kraemer, as well as Yongji Gong and Pulickel Ajayan of Rice University. Banerjee and his colleagues are motivated by a global electronics industry that loses billions of dollars each year to the impact of power dissipation on chip cost and reliability. "This translates into lower battery lifetime in personal devices like cell phones and laptops, and massive power consumption of servers in large data centers," adds Banerjee, pointing out the global scale of this energy demand. An industry that relies on conventional semiconductors such as silicon or III-V compound semiconductors as the channel material for TFETs, Banerjee explains, "faces limitations because these materials have high density of surface states, which increase leakage current and degrade the subthreshold swing." The TFET designed by the UCSB team overcame this challenge in a few ways, most significant being the use of a layered two-dimensional (2D) material called molybdenum disulphide (MoS¬2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3nm. The resulting vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS¬2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area. "The crux of our idea is to combine 3D and 2D materials in a unique heterostructure, to achieve the best of both worlds. The matured doping technology of 3D structures is married to the ultra-thin nature and pristine interfaces of 2D layers to obtain an efficient quantum-mechanical tunneling barrier, which can be easily tuned by the gate," commented Deblina Sarkar, lead author of the paper and PhD student in Banerjee's lab. "We have engineered what is, at present, the thinnest-channel subthermionic transistor ever made," said Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve subthermionic subthreshold swing (~30 millivolts/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1V. Ajayan, co-author and professor of chemical and biomolecular engineering at Rice University, commented, "This is a remarkable example showing the uniqueness of 2D atomic layered materials that enables device performance which conventional materials will not be able to achieve. This is perhaps the first breakthrough in a series of novel devices that people will now aspire to build using 2D materials." "The work is a significant step forward in the search for a low voltage logic transistor. The demonstration of sub-thermal operation over four orders of magnitude is impressive, and the on-current also advances the state-of-the-art. There is still a long ways to go, but this work demonstrates the potential of 2D materials to realize the long-sought, low-voltage device," commented Mark Lundstrom, professor of electrical and computer engineering at Purdue University. "We have demonstrated how to achieve the most important metric of steep subthreshold swing that meets ITRS requirements. Our transistor can be utilized for a number of low-power applications including arenas where the steep subthreshold swing is the main requirement, such as biosensors or gas sensors. With improved performance, the range of applications of this transistor can be further expanded," explained Wei Cao, a PhD student in Banerjee's group and a co-author of the article. "This work represents an important step of bringing 2D materials closer to real applications in electronics. The use of 2D materials in tunneling transistors started only recently, and this paper gives the whole field yet another strong boost in improving the characteristics of such devices even further," commented Dr. Konstantin Novoselov, a professor of physics at University of Manchester. Novoselov was co-recipient of the 2010 Nobel Prize in Physics, awarded for the discovery of graphene. "When I first heard Banerjee's idea of using 2D materials for designing inter-band tunneling transistors in 2012, I recognized its merit and immense potential for ultra-low power electronics. I am pleased to see that his vision has been realized," commented James Hwang, professor of electrical engineering at Lehigh University, who was then the AFOSR program manager responsible for funding this research.