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SummaryDo you think that electornics and light one day can go well toghther on a standard‘CMOS' chip one day? It's reported that researchers have succeeded in introducting a light connection into the heart of a semiconductor chip a few days. In this way,two circuits can communicate.Or: the worlds of electronics and photonics are connected. BodyWhat is particularly attractive is researcher of the university of Twente--Satadal Dutta's solution--A light connection into the heart of a semiconductor chip. There is no special materials or manufacturing processes are needed: the light comes from silicon. The light source, detector and the light channel can be made using the technology that is used to make the electronic circuits. Fully optical circuits are available nowadays, but they use materials like indium phosphide and gallium arsenide, which can't easily be combined with the CMOS chip processes used for semiconductor chips you'll find in today's smartphones.  Connecting WorldsThere is a predictions say that all-optical circuits may become the‘new electronics'. In the transition from electronic to optic circuits, hybrid circuits, like the one Dutta designed, could play an important role. Satadal Dutta (1990, Barrackpore, India) did his PhD research in the Semiconductor Components group of Prof Jurriaan Schmitz, together with the Integrated Circuit Design group of Prof. Bram Nauta. Dutta defended his thesis 'Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology' on 8 November. It was supported financially by NWO-TTW in The Netherlands and by NXP Semiconductors.  Avalanche LEDThe alternative would be: make a LED out of silicon. And that's the problem: silicon only emits a tiny amount of infrared light, while a detector made out of silicon needs visible light. They are talking and listening at different wavelengths. Dutta therefore chooses a remarkable way out: connect the LED reverse. At low voltages, there's no current, but at a voltage that is high enough, there will be a small current that amplifies itself like an avalanche. In this 'avalanche mode', the LED will transmit visible light. Using the same process, the light detector, as well as the light channel in-between can be made. Thanks to the special comb structure that Dutta designed, the light source gets more uniform and energy efficient. IsolationAn optical link on a chip is a good way to 'galvanically' isolate two circuits from each other. This is often necessary in cases where one circuit is a low-voltage and low-current one, while the other is a high-power circuit. They should be connected, but not by conducting wires, for reasons of safety. A classic transformer is an option then, but an optical connection is often used as well. Until now, this is a separate 'optocoupler', which is large and has a limited bit rate. Dutta's new solution is much more compact as an alternative: it total, it is just a few tens of microns and it offers the protection that's needed. Compared to optical channels in full-optical circuits, the energy consumption is relatively high, as there is quite some scattering of light. On the other hand: designing the electronics around the optical link in an efficient way, the amount of light needed for a successful connection, can be kept to a minimum. 

DescriptionIt's not weird to discover that applications are becoming more complex,with connectivity just one of the drivers. And,as it become more complex.the number of sensors grows,as does the need for more capable user interfaces. At the same time,algoriths need more processing power,wireless stacks mandate larger memories and power budgets are shrinking.In order to coping with the growing list of demands, a great number of leading MCU manufacturers have recently launched Micro Controller Unit built around the ARM Cortex-M4 core. BodyThe M3 is general purpse and the M0+is low cost but the M4 is a more capable core in general if look at the Cortex range. Oivind Loe,a senior strategic marketing manager with Sillicon Laboratories said. Microchip's product marketing manager--Anand Rangara commented:“Something that sat around without the need to communicate now needs connectivity. When that happens, you need more flash and RAM, as well as graphics capability and perhaps the ability to support a touch interface. All this has to be offered at good power/performance and an attractive price.”  'Industrial Strength' MCUsSilicon Labs has expanded its EFM32 Gecko portfolio with what it calls ‘industrial strength’ MCUs. It says the EFM32GG11 Giant Gecko MCU family offers the ‘most advanced’ feature set available in the low-power MCU market.Loe noted that MCU development isn’t just about power. “It’s also about executing tasks efficiently. A simple program with a few clocks will run efficiently on an M0+ core. But if the workload is larger, the M4 core has some special instructions that can allow it to use less energy than the M0+ and more efficiently than some larger cores – and that's crucial for a range of application.” GG11 Geckos offer up to 2Mbyte of flash and 512kbyte of RAM to accommodate more code and comms stacks, such as a 10/100 Ethernet MAC and a dual CAN interface. Looking to meet power budgets, the parts boast an active power consumption of 77μA/MHz, while drawing 1.6μA in deep sleep mode. FPU to Increase System EffiencyMicrochip’s SAM D5x/E5x MCUs also take advantage of the Cortex-M4’s floating point unit (FPU) to increase system efficiency. Running at up to 120MHz, the D5x and E5x MCUs come with up to 1Mbyte of dual-panel flash and up to 256kbyte of SRAM. Rangarajan noted: “We’ve listened to our customers, so we’ve included more connectivity in these MCUs. But it's not just about adding memory , it’s also about more performance and the ability to provide more flexible peripherals, interfaces and connectivity options.” Meanwhile,he  pointed out that the original SAM D MCUs – developed by Atmel prior to its acquisition by Microchip – were based on the Cortex-M0+. “But we’ve always wanted to take the product line to the next level of performance. This allows Microchip to address a broader range of consumer and industrial automation applications.” Limited the Clock RateBucking the trend to a certain extent, both Silicon Labs and Microchip have limited the clock rate in their latest MCUs. Giant Geckos, for example, have a maximum clock of 72MHz. “These products are focused on energy efficiency,” Loe claimed. “If you build an MCU to run at 200MHz, for example, then each clock cycle will consume more energy than in an MCU running at 72MHz. A lot of MCUs will be used in battery powered apps, so we need to be energy efficient and to enable the CPU to sleep a lot.” Rangarajan agreed that clock rate is not always the primary factor when it comes to developing MCU portfolios. “We hear our customers saying don’t give me faster clock rates, make sure the MCUs meet my requirements. An app that runs from a battery requires a power efficient MCU. If you want a fast MCU, then you have to make trade offs.” In Loe’s views, MCU selection is all about the ability to perform certain tasks at a particular power efficiency. “That is always going to involve trade offs, but an M4 based MCU will generally be good for embedded applications with challenging energy consumption requirements.” Adopt the Concept of Smart PeripheralsBoth companies have adopted the concept of smart peripherals in their recent products. Loe explained: “Twenty years ago, most MCUs saw the CPU doing everything. That took a lot of CPU cycles, which meant you couldn’t do as much as you might have liked.“Today, most apps will take advantage of DMA, which offloads the CPU. In turn, this allows the CPU to do more.” Rangarajan said Microchip provides what he called ‘sleepwalking’ peripherals. “If there’s a requirement for them to do small numbers of transactions, this can be done without waking the CPU.” On the other hand,Sillicon Loe Noted that It’s all about when you have to wake up the M4 core. We’re trying to allow it to sleep for as much as possible. More than half of the peripherals in a Giant Gecko can run autonomously in deep sleep mode. Both Companies are Keen to Highlight Their Provision Silicon Labs has launched a starter kit to support Giant Gecko based application development(following picture) With this approach, a Giant Gecko’s A/D converter can operate while the CPU is in deep sleep mode. “It can sample and use DMA to pull the data into RAM,” Loe continued.Loe highlighted a couple of aspects. “We have included a cyrotimer that runs in shut off; the lowest energy mode. It’s a simple timer that’s useful when you need the CPU to be asleep for minutes. there’s the Peripheral Reflex System, which allows peripherals to talk. For example, the real time clock could tell the A/D converter to take a sample. It gives a level of determinism which you don’t get from a CPU.  Microchip's Product brings better power efficiency How does an MCU developer differentiate their products from similar devices with an M4 core? Rangarajan pointed to the integration of a buck regulator. “This brings better power efficiency,” he claimed, “which means lower active power consumption; as little as 65µA/MHz. The parts also support flexible pin options.”“We’re offering the best integrated security features,” Rangarajan contended. “SAM Dx/Ex MCUs have crypto hardware acceleration – symmetrical and asymmetrical – and public key encryption, amongst other features. It’s something Microchip has taken to heart and has made sure it’s all in the MCU.“We’re offering the best integrated security features,” Rangarajan contended. “SAM Dx/Ex MCUs have crypto hardware acceleration – symmetrical and asymmetrical – and public key encryption, amongst other features. It’s something Microchip has taken to heart and has made sure it’s all in the MCU.  EndLoe pointed to the security management unit (SMU) as an ‘upgrade’ to the memory protection unit (MPU) associated with the M4’s core. “While the MPU allows you to segment memory into eight regions, the SMU takes that further. The MPU is restricted to eight regions, so there is limited granularity. The SMU allows you to selectively say which pieces of code can access each peripheral.” “All of this is important,” Rangarajan concluded, “as security will become standard in the next few years.” 

Summary As we all know,originally developed to support analogue computers,the op amp has an elegantly simple core design. The industries are contining to spare no effect in creating‘ideal op-amp'.     Simply by wiring in different feedback configurations using passives,op amp can be massaged into roles that include buffers and integrators as well has high-gain amplifiers. It is little wonder the op amp has been as successful as it has been. What's more, people in the industry expect a few core parts to do almost any job and for the circuit to be ripe for integration cause the op amp is so readily tunerable.In practice,the choice of discrete op amps has never been wider. Steve Logan, executive business manager for Maxim Integrated’s core products groups, says: “If you don’t need terribly high bandwidth, high voltage for industrial systems or very low voltage for portable designs, those are times when op amps can be integrated.”   Subtly different edge cases push designer to discrete options Op amps often interface electronics to the outside world, so they need to take account of numerous subtly different edge cases, which pushes designers to discrete options. Each variant uses a specific choice of process and circuit topology to take on a job. Logan cites the wrist-worn heart rate monitor, which measures the light reflected back from a green LED. In these systems, input current noise has a large effect on signal quality, calling for op amps that can deliver much lower levels than generic options.   Signal-Conditioning of Systems Signal-conditioning of systems can turn out to be more complex than first appears. Logan says "“One application that’s not immediately obvious is driving a high-speed, high-resolution SAR A/D converter; it can be pretty demanding circuitry. The difference between a SAR and sigma-delta is in how it takes a big gulp of current. The op amp has to settle quickly, so you are talking settling time, slew rate and total harmonic distortion. You may need multiple stages to get the settling time, along with an input buffer, plus a gain stage and filter stage in front of that. You might think at first: how tough can it be? Then it turns into a two- or three-stage op-amp circuit.”   Dwight Byrd, marketing manager at Texas Instruments, says: “As demand for further sensors and signals increases, better conditioning and amplification of the sensor becomes paramount, thus making the proliferation of op amps possible.”     Art Eck, senior product marketing manager at Microchip Technology, adds: “We see a trend toward more designer op amps: op amps that are built for a particular application or set of applications.” At the same time,Kevin Tretter,the product marketing manager of Microchip notes that changes in application needs are creating new problems for op-amp components to address. “With the rapid expansion of wireless capabilities the industry has seen over the years, the presence of electromagnetic interference is becoming a larger issue. Sensitive analogue sensor circuits commonly sit next to wireless communication modules. More and more amplifier manufacturers are trying to combat the adverse effects by implementing on-chip filtering.”   Demand for Futher Sensors A lot of designs call for sensors to be added but for boards to be shrunk cause increasing noise is partly a by-product of the shrinking size of many designs as well ass the recent focus on making systems more aware of their surrounding environment.   Byrd notes: “Where the biggest driver in further technology trends comes in is package size. Previously, an SC-70 package was considered one of the smallest one-channel op amps available. Now, SOT553 is becoming commonplace.”   Logan says the trend continues all the way to wafer-level packages, measuring just more than 1mm on the longer side. Such tiny packages support the idea of an ‘analogue insurance policy’, where op amps and similar parts provide additional conditioning and protection such as buffering to integrated mixed-signal SoCs. “For a little extra size and cost, you can add these functions and make them more robust. The wafer-level package lets you do that.”   Renesas subsidiary Intersil Engineer Tom Kugelstadt said there is otential for circuit-level advances that could reduce the need for op-amp proliferation and so aid integration. “The biggest inevitable tradeoff is between low-power and high-bandwidth, or high-speed. In general, high-speed amplifiers require the fast charging and discharging of the gate capacitances of the internal transistors. This requires increases in bias and supply currents, which often leads to increased offset current and voltages. While high-speed op amps have improved significantly in these parameters, they still tower a magnitude above their low-speed, precision counterparts.“However, there are circuit topologies that aim for increased precision while trading only a minute portion of their high-speed performance. These designs, known as composite amplifiers, consist of a precision amp in open-loop and a high-speed amp in a closed-loop differentiator configuration.”   Complesity of Picking Right Op-amp The multiple novel circuit topologies that have appeared over the past few decades to deal with problems such as temperature drift and power consumption can have unexpected side effects that designers need to take into account. That adds to the complexity of picking the right op amp.   Logan points to the use of chopper-stabilised amplifiers. “These are great for low offsets, but push the noise out to a single frequency. One that pushes it out to 60kHz is great for DC, but if you have signals that reach 50kHz, you start to get into the noise skirt. These are nuanced things you might not see immediately from the datasheet.”   Frequency-related interactions often need careful examination, says Byrd, and datasheets should show them. “If the output impedance is relatively low and unchanging over a frequency range, it is normally indicative that the op amp will be more stable than one that does have a wide varying output impedance. The output impedance will be interacting directly with the op amp load, and normally a capacitor, it would create various filters as the frequency and therefore the output impedance changes.”   Kugelstadt says interactions with manufacturing choices at the PCB level can introduce unforeseen issues. “High-precision designs using auto-zeroing amplifiers can suffer in precision from asymmetric circuit design. Here, the solder joints around the amplifier form thermocouples that contribute more differential input voltage than the specified offset in the data sheet. Customers unfamiliar with this pitfall blame the device manufacturer for overstating its device performance. The remedy is good application support, such as including layout guidelines in the application section of the data sheet.”   Design Issues TI marketing manager Ying Zhou points out that the need to consider how the op amp is designed, particularly if the op amp is being co-opted for a secondary purpose. “If a dual- or quad-channel op amp is already used elsewhere on the board, sometimes the engineers would assign the left channels for comparator functions,” she says.Although many op amps have input clamping diodes to protect the input transistors but these can affect their behaviour as comparators. Zhou says ‘mux friendly’ versions of op amps that remove the clamps make them more suitable for use as comparators.   Logan notes: “Getting an evaluation kit and putting it on the board is a great thing to do. There is a lot of pin compatibility out there, so you can easily drop another one in to check its performance. But, you do have the issue of having a lot to choose from.”   The industry continues to strive to create the ‘ideal op amp’ and, although we continually get closer to that ideal, there will always be design trade-offs among speed, noise, power usage, size, et cetera. These trade-offs, coupled with continually growing application specific needs, will continue to drive a variety of amplifier types.”  

TroublesAs the deployment of Industrial IoT systems continues to proliferate,the streams of data transferred to the cloud skyrockets, drastically increasing the cost for cloud computing.  SolutionIn order to meet this trouble, many systems designers are adopting edge computing,in which data processing is done close to the source like sensors in a bid to reduce data transfer,storage and processing costs,plus address a few other concerns over Cloud Computing,in particular security. What is Big DataBig Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Huge datacentres are required if you want to store Big Data.Big Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Cloud Computing's advantages and disadvantagesCloud Computing has a lot of advantages including cost efficiency (i.e. no need to invest in and maintain your own hardware), scalability, resource availability (for all your users irrespective of their geographic locations), lower latency (as you can specify servers that are closest to the relevant users/customers) and peace of mind in terms of back-ups. There are,however,some disadvantages also. The biggest of which is that no provider can guarantee 100% availability. Data security and privacy are also causes for concern, both on the cloud and for data in transit. Latency can be an issue for Big Data, and doing computationally intensive tasks on the cloud will increase the cost. Of these concerns the last two, in particular, can be negated through edge processing; i.e. performing much of the computationally intensive work near the source data. Benefits here include real-time or near-real-time data processing and reduced network traffic, as you need only transfer the product of the edge processing, thus resulting in lower Cloud Computing costs. Security and privacy can be improved by keeping the sensitive data (a.k.a. Hot Data) within the edge processing environment and only sending less sensitive (Cold) data to the cloud. FPGAs have the edgeThere are technologies that can be used for edge processing applications. These include the use of traditional CPUs (scoring high in terms of flexibility), application-specific processors (e.g. GPUs) and ASICs/SoCs (scoring high on performance). However, it is FPGAs that are slotting into most edge processing applications. Why is this so? Well, let’s consider the requirements. Edge processing needs to be high-performance and in this respect an FPGA can perform several different tasks in parallel. For example, consider executing many non-dependent computations (such as A=B+C, D=E+F and G=H+I). On a CPU, these would have to be performed sequentially, with each sum requiring a few clock cycles. In an FPGA, an array of adders could do the computations in parallel, possibly requiring only a single clock cycle. Power efficiency is essential too, as the end product may well be battery-powered. With an FPGA the function (design) need be the only circuit present, whereas the architecture of a CPU or GPU may not be fully utilized. Also, with an FPGA comes the benefit of reprogrammability. Higher security is afforded too because the edge processing functions are hard wired into the FPGA. It is also possible to encrypt the transaction bus and to even go as far as designing your own processor. ConnectingA prime example of where edge processing is extremely useful, and in which FPGAs can play a significant role, is within an embedded system in which data derived from images needs to be transferred. For example, in the automotive sector Advanced Driver Assistance Systems (ADAS) are under development to make driving safer, easier and more comfortable, and ADAS is regarded as a significant step towards fully autonomous cars. The data processed by an ADAS can be used to notify the driver of problems or to automatically trigger responses such as deceleration, braking and/or the execution of a manoeuvre. The data can also be useful outside the vehicle. Let's discuss the embedded vision system first though by considering an ADAS demo unit that was built for this year's Embedded Vision show in Santa Clara, California. The demo comprised a TySOM-2-7Z100 prototyping board (see figure 1) which includes a Xilinx Zynq XC7Z100 device and a TySOM-FMC-ADAS daughter board to interface with four 960 x 540 pixel cameras. The processing was shared between a dual-core ARM Cortex-A9 processor and FPGA logic (both of which reside within the Zynq device) and began with frame grabbing images from the cameras and applying an edge detection algorithm (‘edge’ here in the sense of physical edges, such as objects, lane markings etc.). This is a computational-intensive task because of the pixel-level computations being applied (i.e. more than 2 million pixels). To perform this task on the ARM CPU a frame rate of only 3 per second could have been realised, whereas in the FPGA 27.5 fps was achieved.This picture is a TySOM-2-7Z100 prototyping board. Mixed technology (like CPU and FPGA) boards are proving very popular for edge processing applications and for connecting with the cloud.  The ARM CPU was mainly used for superimposing detected edges over the initial camera images, colour-space conversions, the formation of a composite image (see main image) and outputting it to an HD buffer. The FPGA and CPU could also work together to recognise and distinguish between obstacles and pedestrians close to the car and to provide lane departure warnings. What goes upSending the processed data to the cloud for further processing and/or storage is then a relatively simple task. Firstly, an AWS account would be created along with an AWS IoT environment. Next, we would configure a Thing (seeing as it is the IoT) and download the public and private keys needed for secure communications with the cloud.The embedded C MQTT standard would be the ideal Software Development Kit (SDK), because it is secure and requires minimal bandwidth. An application would then be prepared to run on the ARM CPU to publish the data onto the cloud. Imagine a scenario,howevber,under which we have data from thousands of vehicles going to the cloud.Analysis of the data could be performed on the cloud and made available for traffic systems or highway maintenance organisations, for example. There may also be instances where data from the cloud feeds into an edge-processing application, in which case applications are also available from AWS. All in all,there are both advantages and disadvantages associated with cloud computing. And many of the disadvantages will be overcome though edge-processing that FPGAs are a particularly suitable activity.  Article provided by Farhad Fallah,an Application Engineer with EDA company AldecArticle edited by Kynix 

SummaryThe robot comes perfectly if they can walk more naturally for humans.However,it's not an easy job for robots and their designers. Walking on two legs is actually a complicated task,requiring several muscles to perform delicate balancing acts.That's why in spite of years of major technological advancements in the field,humanoid robots are still far from being able to get around easily and reliably. Engineers at EPFL's Biorobotics Laboratory are testing new walking algoritms on a plateform called COMAN, short for COmpliant HuMANoid. This 95-cm-tall humanoid is designed specifically for studying walking – which is why it has no head. COMAN was developed under the EU AMARSi project and is being used by several research teams. The EPFL team is looking specifically at the "brains" of the machine. "We developed algorithms that can improve the robot's balance while it's walking," says Hamed Razavi, a researcher scientist at the Biorobotics Lab.  Body One:Climbing Stairs and Opening Doors The algorithms are geared towards three types of realworld applications. The first is carrying out rescue missions in disastrous scenarios. "In environments designed by humans - like a nuclear power plant where there are stairs to climb and doors to open – humanoid robots can get around more easily than robots with wheels," says Razavi. The second is helping with tasks like carrying heavy boxes or moving objects (see box). And the third is creating exoskeletons for the disabled. "Making the robots more stable is just the tip of the iceberg," says Razavi. The next step is refining the algorithms so that the humanoids have a wider range of movement and can overcome obstacles and walk on irregular or sloped surfaces. Two:In Harmony with Symmetries One of COMAN's distinguishing features is its joints,which are integrated with elastic elements that give it greater flexibility when performing different tasks.The EPFL team came up with a novel control algorithm for the robot, based on the existing symmetries in the structure and dynamics of the robot' as well as the mathematical equations representing the robot dynamics. "You could say we're working in harmony with these symmetries rather than against them. As a result, we obtain a more natural and robust walking gait," says Razavi. The control algorithm uses sophisticated computer programs to carefully analyze the date received from the robot – including its position, velocity, joint angles, etc. – and sends appropriate commands to the motors, telling them what to do in order to maintain the robot's balance. "For example, if someone pushes COMAN, for example, our algorithms will calculate exactly where its foot should land in order to counteract the perturbation," says Razavi. Three: Humanoids Helping Humans As part of this project,Jessica Lanini and Hamed Razavi studied how two people carrying an object together are able to walk,turn and speed up in a coordinated manner - without communicating with each other.Their findings,recently published in PLOS ONE,indicate that the two people automatically synchronize their steps, like a quadruped. Now the researchers plan to apply their results to humanoid robots. Lanini explained:"Whether for manufacturing or natural disasters, we need robots that can interact with humans and help us carry heavy objects,but such robots don't exist. That's because, in order to operate safely and effectively, the robots would need to be able to make decisions and respond to unexpected circumstances." But such robots don't exist. The reason is that in order to operate safely and effectively, the robots would need to be able to make decisions and respond to unexpected circumstances." Article provided by  Ecole Polytechnique Federale de Lausanne. 

As one of the world-leading research and innovation hub in nanoelectronics and digital technology,IMEC announced at the 2017 Symposia on VLSI Technology and Circuits that the world's first demonstration of a vertically stacked ferroelectric,AI doped HfO2 device for NAND applications.Using a new material and a novel architecture,imechas created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention. The achievement shows that ferro-electric memory is a highly promising technology at various points in the memory hierarchy, and as a new technology for storage class memory. Imec will further develop the concept in collaboration with the world's leading producers of memory ICs.  Ferro-electric materials consist of crystals that exhibit spontaneous polarization; they can be in one of two states, which can be reversed with a suitable electric field. This non-volatile characteristic resembles ferromagnetism, after which they have been named. Discovered more than five decades ago, ferro-electric memory has always been considered ideal, due to its very low power needs, non-volatile character and high switching speed. However, issues with the complex materials, the breakdown of the interfacial layer and bad retention characteristics have presented significant challenges. The recent discovery of a ferro-electric phase in HfO2, a well-known and less complex material, has triggered a renewed interest in this memory concept.  "With HfO2, there is now a material with which we can process ferro-electric memories that are fully CMOS compatible. This allows us to make a ferro-electric FET (FeFET) in both planar and vertical varieties," noted Jan Van Houdt, imec's chief scientist for memory technology. "We are working to overcome some of the remaining issues, such as retention, precise doping techniques and interface properties, in order to stabilize the ferro-electric phase. We are now confident that our FeFET concept has all the required characteristics. It is, in fact, suitable for both stand-alone and embedded memories at various points in the memory hierarchy, going all the way from non-volatile DRAM to Flash-like memories. It has particularly interesting characteristics for future storage-class memory, which will help overcome the current bottleneck caused by the differences in speed between fast processors and slower mass memory." Imec recently presented the first, extremely positive results to its partners. The research center is now offering further development and industrialization of the vertical FeFET as a program to all its memory partners, which include the world's major companies producing memory ICs.  Van Houdt explained "FeFETs can be used as a technology to build memory very similar to Flash-memory, but with additional advantages for further scaling, simplified processing, and power consumption,with our longstanding R&D and processing experience on advanced Flash, we are uniquely positioned to offer our partners a head start in this exciting opportunity. They can then decide how best to fit ferro-electric memories in their products and chips." This is a breakthrough in CMOS-compatible ferroelectric memory, let's look forward to the CMOS-compatible ferroelectric memory together.