The Kynix Blog

Researchers at the University of Alabama at Birmingham have found a novel and practical way to combat malicious attacks on motion sensors inside mobile devices.In a study published in proceedings of the 9th Association for Computing Machinery Conference on Security & Privacy in Wireless and Mobile Networks, associate professor Nitesh Saxena, Ph.D., and Ph.D. students Prakash Shrestha and Manar Mohamed have created a way to defend mobile device users against motion-based touchstroke leakage with the injection of noise.Previous research shows that, much like the way a hacker can covertly capture inputs made from a regular computer keyboard, it is also possible to capture a user's inputs on a touchscreen. Currently, motion sensors on Android devices can be accessed by any application downloaded to the device, without a user's being prompted to give permission. By tricking a user into unknowingly downloading a malicious program, hackers could obtain sensitive information like passwords and PINs by tracking the vibrations made from the touchscreen and decoding the movements based on a keyboard's layout. Given the accuracy rate of this type of attack, mobile security experts consider it a significant threat to user privacy and are exploring methods to combat it."Most mobile platforms have established a sensor security access control model," Saxena said. "Android follows a model where read access to many sensitive sensors, like a phone's camera or microphone, is very restrictive or requires special permissions granted by the user. However, the read access to other sensors, like inertial sensors, is not restricted because Android may not consider these sensors explicitly sensitive. This openness in the Android sensor security architecture has given rise to potentially significant threat of motion-based side channel attacks."By utilizing a recently developed framework called SMASheD (Sniffing and Manipulating Android Sensor Data), initially created as a malicious application, the study's authors built a defense mechanism called Slogger that can be used to thwart sensor-based touchstroke logging attacks. As a user enters sensitive information, Slogger transparently inserts noisy sensor readings in order to obscure the original readings. Slogger works in the background of a device and is completely unnoticeable to a user and other trusted applications. It can be installed through the Android Debug Bridge, without the need to root the device or change its operating system.To test Slogger's effectiveness, the authors compromised an Android device using two of the latest touchstroke logging algorithms developed for touchstroke detection and inference. During this type of attack, the start and end points of a user's taps are monitored. With data recorded by the accelerometer, a hacker could determine whether a user is holding the device vertically or horizontally. They can also predict what areas of the screen were tapped by applying machine learning tools. Later, by mapping the predicted areas with the standard keyboard layout, a hacker can determine the series of taps.After installing the malicious application, the authors also installed Slogger. Upon being installed, Slogger prompts the user to do a series of typing tests, holding the device in various positions. This allows Slogger to learn the range of the sensor values based on the user's typing style. The user types while holding the phone in his or her hand and while it is lying on a flat surface. The values are later used to set the range of values for injecting noise during an attack."During the evaluation phase, we implemented Slogger in such a way that, whenever the user launches the application used for the attack, a noise inject request is sent to the Slogger server," Saxena said. "When the user closes the application, a request to stop Slogger is sent. The application can also be updated to send an inject request whenever the keyboard is running or whenever a user is entering sensitive information."Slogger searches for system files related to motion sensors such as an accelerometer or gyroscope, and injects noise until it receives a request to stop, like when the application being used for the malicious attack is closed. Without Slogger, the touchstroke detector had an 85 percent rate of accuracy. Once the Slogger application was enabled, the touchstroke detector was unable to detect any touchstrokes. During the touchstroke inference test, there was a 90 percent accuracy rate without Slogger. Slogger was able to reduce inference accuracy to 56 percent while the device lay on a flat surface. While the user held the device, inference accuracy was reduced by more than 20 percent.During the evaluation, the authors discovered Slogger was also highly effective in minimizing touchstroke leakage even when more than one motion sensor is leveraged by an attacker. 

Japan's Toshiba is teaming up with US chip giant SanDisk to produce a "3D" memory chip they hope will allow users to save up to 50 hours of ultra-high definition video.In a deal worth a reported 500 billion yen ($4.84 billion) the companies will build a factory to make flash memory consisting of several layers of semiconductors stacked together to give as much as a terabyte—1,000 gigabytes—of storage.That is around 16 times bigger than the largest 64-gigabyte Toshiba memory currently available in smart phones and tablet devices.Toshiba will demolish its existing plant in Japan to build a new facility that will house production apparatus using technologies from both firms and which the firms hope will start operating in 2016, a statement said."In about five years (from the planned start of the factory), we would like to produce one-terabyte products," said a Toshiba spokeswoman.The plan comes at a time of increasing competition among the world's technology firms to meet demand for ever-higher capacity memory chips for consumers increasingly using mobile devices such as smart phones, tablet computers and wearable gadgets.The spread of high-definition video, with so-called 4K screens at the leading edge, is boosting demand for computing memory to store content."Small, high-capacity memories can of course be applied to smartphones, but they could also be used for wearable devices," the Toshiba spokeswoman said.Manufacturers have traditionally competed with regular chips by trying to make the physical object smaller.Toshiba, along with major rivals such as Samsung, believe they are reaching the physical limit, and are shifting toward 3D memories, where layering—effectively a third dimension—is used to boost the capacity of objects the same size.Yasuo Naruke, Toshiba senior vice president, said in a statement: "Our determination to develop advanced technologies underlines our commitment to respond to continued demand (for) flash memory."SanDisk president and chief executive Sanjay Mehrotra said the plant "will advance our leadership in memory technology into the 3D... era". 

Researchers at Japan's National Institute for Materials Science revealed that improvements should soon be expected in the manufacture of transistors that can be used, for example, to make flexible, paper-thin computer screens.The scientists reviewed the latest developments in research on photoactive organic field-effect transistors; devices that incorporate organic semi-conductors, amplify weak electronic signals, and either emit or receive light.Organic field-effect transistors (OFETs) were developed to produce low-cost, large-area electronics, such as printable and/or flexible electronic devices.The researchers reported that much progress has been made in the development of light-emitting organic field-effect transistors (LE-OFETs) since they first appeared in 2003.Research in this area has resulted in advances in the manufacture of novel organic photonics applications using cost-effective approaches. Light emission efficiency and brightness of these transistors will soon improve. And the production of new display technologies is expected to be the result of further research.LE-OFETs are also expected to become fully compatible with well-established electronic technologies. This may allow further development of optical communication systems and optoelectronic systems, such as those using laser technologies.LE-OFETs are being used to develop, for example, flexible, transparent computer screens. These screens are purported to provide faster response times, better efficiency, and no need for backlighting. They also have very low energy needs.Light-receiving organic field-effect transistors (LR-OFETs), on the other hand, are much less developed than their light-emitting siblings. LR-OFETs convert light into electrical signals, opening a way to new optoelectronic devices.Phototransistors, used in CD players, are an example of such devices that hold much promise. But their durability needs to be improved for them to be used in more flexible applications.Further development is also required in other kinds of light-receiving OFETs before they can be used in all-plastic computing devices.Light-receiving organic field-effect transistors could open new frontiers for photonic and electronic devices. Flexible displays, in which all the device components – such as the light-emitting parts, the switching parts, and the substrates – consist of plastic materials have already been developed and will appear on the market in the near future. However, similar memory devices are still lacking. If "plastic memory" is developed, it will open a new frontier.The researchers found that the performance of devices that incorporate both light-emitting and light-receiving transistors faces several issues. They recommend interdisciplinary collaborations between organic chemists and device physicists for these issues to be resolved. They estimate that it will still be another ten years before all-plastic, flexible computing devices appear on the market.

In a word first, researchers from Tohoku University have successfully developed a technology to stack magnetic tunnel junctions (MTJ) directly on the vertical interconnect access (via) without causing deterioration to its electric/magnetic characteristics. The via in an integrated circuit design is a small opening that allows a conductive connection between the different layers of a semiconductor device. This new discovery will be particularly significant in reducing the chip area of spin-transfer torque magnetic random access memory (STT-MRAM), making its commercialization more practical. The team led by Professor Tetsuo Endoh, Director of the Center for Innovative Integrated Electronic Systems (CIES), focused on reducing the memory cell area of STT-MRAMs in order to lower manufacturing costs, making them competitive with conventional semiconductor memories like dynamic random access memory (DRAM). Because MTJs use magnetic properties, the quality of the surface between the MTJ and its lower electrode is important. If the surface area is not smooth, the electric/magnetic characteristics of the MTJ will degrade. For this reason, placing an MTJ directly on the via holes in STT-MRAMs has been avoided until now, although it increases the size of the memory cell. Endoh's group has tackled the issue by developing a special polishing process technology to prevent any interference between the MTJ and its lower electrode. The technology's effectiveness was successfully verified by an experiment using single-MTJ test chips. To further test the success of this development, a 2-Mbit STT-MRAM test chip integrating the new technology has been designed to verify the space needed for the integrated circuits—this includes more than 1million MTJs. "Not only does this test chip show a 70% improvement in its memory bit yield compared to standard STT-MRAM, but its memory cell area is reduced by 30%," says Endoh. "It will be very effective for reducing the chip area of MRAM." CIES develops material, process, circuit and test technologies in integrated electronic systems. The center's main focus is on developing high-performance, low-power technologies for a more energy-efficient society.    

In today's computer chips, memory management is based on what computer scientists call the principle of locality: If a program needs a chunk of data stored at some memory location, it probably needs the neighboring chunks as well.But that assumption breaks down in the age of big data, now that computer programs more frequently act on just a few data items scattered arbitrarily across huge data sets. Since fetching data from their main memory banks is the major performance bottleneck in today's chips, having to fetch it more frequently can dramatically slow program execution.This week, at the International Conference on Parallel Architectures and Compilation Techniques, researchers from MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL) are presenting a new programming language, called Milk, that lets application developers manage memory more efficiently in programs that deal with scattered data points in large data sets.In tests on several common algorithms, programs written in the new language were four times as fast as those written in existing languages. But the researchers believe that further work will yield even larger gains.The reason that today's big data sets pose problems for existing memory management techniques, explains Saman Amarasinghe, a professor of electrical engineering and computer science, is not so much that they are large as that they are what computer scientists call "sparse." That is, with big data, the scale of the solution does not necessarily increase proportionally with the scale of the problem."In social settings, we used to look at smaller problems," Amarasinghe says. "If you look at the people in this [CSAIL] building, we're all connected. But if you look at the planet scale, I don't scale my number of friends. The planet has billions of people, but I still have only hundreds of friends. Suddenly you have a very sparse problem."Similarly, Amarasinghe says, an online bookseller with, say, 1,000 customers might like to provide its visitors with a list of its 20 most popular books. It doesn't follow, however, that an online bookseller with a million customers would want to provide its visitors with a list of its 20,000 most popular books.Thinking locallyToday's computer chips are not optimized for sparse data—in fact, the reverse is true. Because fetching data from the chip's main memory bank is slow, every core, or processor, in a modern chip has its own "cache," a relatively small, local, high-speed memory bank. Rather than fetching a single data item at a time from main memory, a core will fetch an entire block of data. And that block is selected according to the principle of locality.It's easy to see how the principle of locality works with, say, image processing. If the purpose of a program is to apply a visual filter to an image, and it works on one block of the image at a time, then when a core requests a block, it should receive all the adjacent blocks its cache can hold, so that it can grind away on block after block without fetching any more data.But that approach doesn't work if the algorithm is interested in only 20 books out of the 2 million in an online retailer's database. If it requests the data associated with one book, it's likely that the data associated with the 100 adjacent books will be irrelevant.Going to main memory for a single data item at a time is woefully inefficient. "It's as if, every time you want a spoonful of cereal, you open the fridge, open the milk carton, pour a spoonful of milk, close the carton, and put it back in the fridge," says Vladimir Kiriansky, a PhD student in electrical engineering and computer science and first author on the new paper. He's joined by Amarasinghe and Yunming Zhang, also a PhD student in electrical engineering and computer science.Batch processingMilk simply adds a few commands to OpenMP, an extension of languages such as C and Fortran that makes it easier to write code for multicore processors. With Milk, a programmer inserts a couple additional lines of code around any instruction that iterates through a large data collection looking for a comparatively small number of items. Milk's compiler—the program that converts high-level code into low-level instructions—then figures out how to manage memory accordingly.With a Milk program, when a core discovers that it needs a piece of data, it doesn't request it—and a cacheful of adjacent data—from main memory. Instead, it adds the data item's address to a list of locally stored addresses. When the list is long enough, all the chip's cores pool their lists, group together those addresses that are near each other, and redistribute them to the cores. That way, each core requests only data items that it knows it needs and that can be retrieved efficiently.That's the high-level description, but the details get more complicated. In fact, most modern computer chips have several different levels of caches, each one larger but also slightly less efficient than the last. The Milk compiler has to keep track of not only a list of memory addresses but also the data stored at those addresses, and it regularly shuffles both around between cache levels. It also has to decide which addresses should be retained because they might be accessed again, and which to discard. Improving the algorithm that choreographs this intricate data ballet is where the researchers see hope for further performance gains."Many important applications today are data-intensive, but unfortunately, the growing gap in performance between memory and CPU means they do not fully utilize current hardware," says Matei Zaharia, an assistant professor of computer science at Stanford University. "Milk helps to address this gap by optimizing memory access in common programming constructs. The work combines detailed knowledge about the design of memory controllers with knowledge about compilers to implement good optimizations for current hardware."  

Imec, the Belgian nanoelectronics research center, will present at this week's 'CMOS Image Sensors for High Performance Applications' workshop in Toulouse (France) a prototype of a high-performance, time-delay-integration (TDI) image sensor. The image sensor is based on imec's proprietary embedded charge-coupled device (CCD) in CMOS technology. Imec developed and fabricated the sensor for the French Space Agency, CNES, which plans to utilize the technology for space-based earth observation.  The prototype image sensor combines a light-sensitive, CCD-based TDI pixel array with peripheral CMOS readout electronics. By integrating CCD with CMOS technology, imec combined the best of both worlds. The CCD pixel structure delivers low-noise TDI performance in the charge domain, while CMOS technology enables low-power, on-chip integration of fast and complex circuitry readouts.A TDI imager is a linear device that utilizes a clever synchronization of the linear motion of the scene with multiple samplings of the same image, thereby increasing the signal to noise ratio. CCDs fit extremely well with the TDI application since they operate in the charge domain, enabling the movement of charges without creating excess noise. By combining the TDI pixels array with CMOS readout circuitry on the same die, imec produced a camera-on-a-chip or system-on-a-chip (SOC) imager, which reduces the overall system complexity and cost. The CMOS technology enables on-chip readout electronics, such as clock drivers and analog-to-digital convertors (ADCs), operating at higher speeds and lower power consumption not possible with traditional CCD technology.The prototypes were fabricated using imec's 130nm process with an additional CCD process module. An excellent charge transfer efficiency of 99.9987 % has been measured ensuring almost lossless transport of charges in the TDI array, and guaranteeing high image quality. Imec's specialty imaging platform combines custom design (i.e., specialized pixels, high-performance readout circuits and chip architectures) with optimized silicon processing, such as dedicated implants and backside thinning, to achieve high-end specialized imagers.