The Kynix Blog

Random-access memory, or RAM, is where computers like to store the data they're working on. A processor can retrieve data from RAM tens of thousands of times more rapidly than it can from the computer's disk drive.But in the age of big data, data sets are often much too large to fit in a single computer's RAM. The data describing a single human genome would take up the RAM of somewhere between 40 and 100 typical computers.Flash memory—the type of memory used by most portable devices—could provide an alternative to conventional RAM for big-data applications. It's about a tenth as expensive, and it consumes about a tenth as much power.The problem is that it's also a tenth as fast. But at the International Symposium on Computer Architecture in June, MIT researchers presented a new system that, for several common big-data applications, should make servers using flash memory as efficient as those using conventional RAM, while preserving their power and cost savings.The researchers also presented experimental evidence showing that, if the servers executing a distributed computation have to go to disk for data even 5 percent of the time, their performance falls to a level that's comparable with flash, anyway.In other words, even without the researchers' new techniques for accelerating data retrieval from flash memory, 40 servers with 10 terabytes' worth of RAM couldn't handle a 10.5-terabyte computation any better than 20 servers with 20 terabytes' worth of flash memory, which would consume only a fraction as much power."This is not a replacement for DRAM [dynamic RAM] or anything like that," says Arvind, the Johnson Professor of Computer Science and Engineering at MIT, whose group performed the new work. "But there may be many applications that can take advantage of this new style of architecture. Which companies recognize: Everybody's experimenting with different aspects of flash. We're just trying to establish another point in the design space."Joining Arvind on the new paper are Sang Woo Jun and Ming Liu, MIT graduate students in computer science and engineering and joint first authors; their fellow grad student Shuotao Xu; Sungjin Lee, a postdoc in Arvind's group; Myron King and Jamey Hicks, who did their PhDs with Arvind and were researchers at Quanta Computer when the new system was developed; and one of their colleagues from Quanta, John Ankcorn—who is also an MIT alumnus.Outsourced computationThe researchers were able to make a network of flash-based servers competitive with a network of RAM-based servers by moving a little computational power off of the servers and onto the chips that control the USB flash drives. By preprocessing some of the data on the flash drives before passing it back to the servers, those chips can make distributed computation much more efficient. And since the preprocessing algorithms are wired into the chips, they dispense with the computational overhead associated with running an operating system, maintaining a file system, and the like.With hardware contributed by some of their sponsors—Quanta, Samsung, and Xilinx—the researchers built a prototype network of 20 servers. Each server was connected to a field-programmable gate array, or FPGA, a kind of chip that can be reprogrammed to mimic different types of electrical circuits. Each FPGA, in turn, was connected to two half-terabyte—or 500-gigabyte—flash chips and to the two FPGAs nearest it in the server rack.Because the FPGAs were connected to each other, they created a very fast network that allowed any server to retrieve data from any flash drive. They also controlled the flash drives, which is no simple task: The controllers that come with modern commercial flash drives have as many as eight different processors and a gigabyte of working memory.Finally, the FPGAs also executed the algorithms that preprocessed the data stored on the flash drives. The researchers tested three such algorithms, geared to three popular big-data applications. One is image search, or trying to find matches for a sample image in a huge database. Another is an implementation of Google's PageRank algorithm, which assesses the importance of different Web pages that meet the same search criteria. And the third is an application called Memcached, which big, database-driven websites use to store frequently accessed information.Chameleon clustersFPGAs are about one-tenth as fast as purpose-built chips with hardwired circuits, but they're much faster than central processing units using software to perform the same computations. Ordinarily, either they're used to prototype new designs, or they're used in niche products whose sales volumes are too small to warrant the high cost of manufacturing purpose-built chips.But the MIT and Quanta researchers' design suggests a new use for FPGAs: A host of applications could benefit from accelerators like the three the researchers designed. And since FPGAs are reprogrammable, they could be loaded with different accelerators, depending on the application. That could lead to distributed processing systems that lose little versatility while providing major savings in energy and cost."Many big-data applications require real-time or fast responses," says Jihong Kim, a professor of computer science and engineering at Seoul National University. "For such applications, BlueDBM"—the MIT and Quanta researchers' system—"is an appealing solution."  

A new, environmentally-friendly electronic alloy consisting of 50 aluminum atoms bound to 50 atoms of antimony may be promising for building next-generation "phase-change" memory devices, which may be the data-storage technology of the future, according to a new paper published in the journal Applied Physics Letters, which is produced by AIP Publishing.Phase-change memory is being actively pursued as an alternative to the ubiquitous flash memory for data storage applications, because flash memory is limited in its storage density and phase-change memory can operate much faster.Phase-change memory relies on materials that change from a disordered, amorphous structure to a crystalline structure when an electrical pulse is applied. The material has high electrical resistance in its amorphous state and low resistance in its crystalline state—corresponding to the 1 and 0 states of binary data.Flash memory has problems when devices get smaller than 20 nanometers. But a phase-change memory device can be less than 10 nanometers—allowing more memory to be squeezed into tinier spaces. "That's the most important feature of this kind of memory," said Xilin Zhou of the Shanghai Institute of Microsystem and Information Technology at the Chinese Academy of Sciences. Data can also be written into phase-change memories very quickly and the devices would be relatively inexpensive, he added.So far, the most popular material for phase-change memory devices contains germanium, antimony, and tellurium. But compounds with three elements are more difficult to work with, Zhou said."It's difficult to control the phase-change memory manufacturing process of ternary alloys such as the traditionally used germanium-antimony-tellurium material. Etching and polishing of the material with chalcogens can change the material's composition, due to the motion of the tellurium atoms," explained Zhou.Zhou and his colleagues turned to a material with just two elements: aluminum and antimony. They studied the material's phase-changing properties, finding that it's more thermally stable than the Ge-Sb-Te compound. The researchers discovered that Al50Sb50, in particular, has three distinct levels of resistance—and thus the ability to store three bits of data in a single memory cell, instead of just two. This suggests that this material can be used for multilevel data storage."A two-step resistance drop during the crystallization of the material can be used for multilevel data storage (MLS) and, interestingly, three distinct resistance levels are achieved in the phase-change memory cells," Zhou says. "So the aluminum-antimony material looks promising for use in high-density nonvolatile memory applications because of its good thermal stability and MLS capacity."  

Arash Moradi and Mohamad Sawan from Polytechnique Montreal in Canada discuss their new low-power VCO design for medical implants. This oscillator was implemented to provide the frequency deviation of frequency-shift-keying (FSK) modulation in implantable radio-frequency (RF) transceivers.How are wireless RF transceivers used in medical applications?Implantable medical sensors keep short-range wireless communication a challenging and hot research topic for the monitoring and detection of various health parameters, such as temperature, pressure, oxygenation, seizures and other signs of diseases. For instance, the continuous monitoring of oxygen levels of the blood for patients suffering from epilepsy may help locate, treat and even prevent the emergence of seizures, thanks to low-power, high-data-rate wireless links. Even monitoring the behaviour of freely-moving animals, where light and free-running circuits are demanded, offers the chance to extract medical information in realistic conditions.Why is it so challenging to build wireless RF transceivers for implantable sensors?The constraints of the RF transceivers for wireless body area networks are different from conventional ones. The two main challenges are reducing the size and the power consumption of the transmitter front-end to maintain real-time, long-term data transmission. Thanks to CMOS technology, the small size of the wireless interface helps to get rid of most of the external bulky components. In practice, since the implanted devices have limited power storage, different circuits and systems design techniques have to be invented to achieve an energy-efficient communication interface. The battery cell of the current power-hungry wireless transmitter in existing medical implants has to be recharged or replaced through frequent medical surgeries, which is not adequate, and the transmitter power budget may be notably reduced.What motivated you to develop a new low power VCO?As reported in the literature, crystal-less and inductor-less voltage-controlled oscillators (VCOs) help to implement the fundamental building blocks in implantable and VLSI systems with different frequency ranges. Specifically, in widely-used binary FSK-based transceiver architectures, the carrier frequency gets shifted up and down by a frequency deviation to distinguish between the signal levels low (0) and high (1). Such frequency deviation is usually defined by differential quadrature signals that can be generated by cascaded flip-flops acting as a frequency divider fed by an external reference clock or crystal oscillators. However, crystal oscillators may not be suitable for integrated and implantable sensors. The frequency may also vary, depending on the application and the available channel bandwidth. As a result, a quadrature VCO (QVCO) is designed to provide the required quadrature signals with specific characteristics to help realise the target energy-efficient FSK-based RF transceiver.Previous VCOs with such frequency range did not offer all the desired features including consuming small current and providing rail-to-rail, differential and quadrature versions of the signal at the same time.Can you describe the design of the VCO reported in your Electronics Letters paper?Our low-power differential rail-to-rail QVCO is composed of a 2-stage quadrature oscillator, where each stage is acting similar to a bi-stable circuit triggered by the output of the other one. This can be considered as a ring oscillator where no external clock signal is required and facilitates the integration of the oscillator; therefore, it only needs a small silicon area and a low current consumption. The start-up circuit is also designed to initiate the oscillation and is then automatically disconnected from the oscillator's circuit so as not to affect the oscillation.Single-ended variable-frequency ring-oscillators have been already presented with similar frequency and power range to the new QVCO. However, this is the first design of a fully-integrated low-power QVCO that is capable of providing rail-to-rail, differential and quadrature versions of a variable-frequency signal, simultaneously.When will you have a prototype?The first prototype of the designed QVCO is in the fabrication and packaging process and is due to be tested soon. Challenges include the parasitic capacitance and resistance within the test-setup, as well as probing itself, which may play major roles in changing the behaviour of the expected output signals. Besides, producing the input signals – including the ones for enabling or disabling different blocks – with proper falling and rising time and providing the power supply, will have to be carefully planned.We plan to use a functional implemented QVCO as an actual block to characterise the target implemented RF transceiver. More controlling signals may be added in future prototypes so that it can be used for several communication applications with different frequency and current ranges, such as providing the optimum carrier frequency for wireless power transfer using inductive links.How do you see this technology developing in the future?Wireless link technologies are increasing, in particular in implantable medical devices, where very low-power circuits and systems are necessary. Nowadays, a typical wireless link may occupy up to 90% of the device's total power consumption. Recent deep sub-micron technologies look promising in allowing the improvement of the speed with much lower power leakage and smaller size, which will help designers to improve the performance of the wireless links of these devices.To help this field progress, we would like to see better connection of academic and industrial researchers, as shared access to various deep sub-micron technologies may widen the window to develop new ideas in circuits and systems designs. 

IBM today introduced the fifth generation of semiconductor technology specialized for high performance communications. The company's latest silicon-germanium (SiGe) chip-making process is designed to enable ever-increasing amounts of data to flow through network backbones in applications such as Wi-Fi, LTE cellular, wireless backhaul and high speed optical communications.Since its introduction in 1995, IBM's SiGe semiconductor technology has helped spur a revolution in radio frequency (RF) performance, enabling engineers to develop breakthrough devices such as satellite global positioning systems, WiFi radios and high speed optical links. IBM's new "9HP" SiGe technology continues to put advanced capability in the hands of engineers who design chips for LTE cellular base stations, millimeter-wave wireless communication links, and next generation short and long-haul optical communications. Outside of communications, 9HP performance will advance the state of the art in other applications such as high-performance test equipment, automotive radar and security imaging."Silicon-germanium is one of the key technologies that have enabled wireless operators to keep up with the explosive growth in data traffic generated from mobile handsets," said David Harame, IBM Fellow. "Before SiGe, the high-performance chips used in base stations and optical links were built using expensive, esoteric processes. SiGe provides the necessary performance as well as integration and cost savings via its CMOS base."Open Collaboration is Key to SuccessOver the years, a number of leading technology companies have come to rely on the benefits and advantages of SiGe, working closely with IBM to develop and refine new versions of the chip-making process. IBM believes that open collaboration among companies will drive future breakthrough innovation in semiconductors."As early adopters of IBM's SiGe technology, Semtech has consistently pushed the envelope on what can be achieved in high-speed wired and wireless communications systems and in high performance analog devices," said Charles Harper, Senior Vice President of Semtech's Systems Innovation Group. "With today's technology, Semtech is a leader in 40Gbps and 100Gbps Communications Systems and with IBM's latest SiGe technology we believe we can emerge as a leader in several new analog segments where performance, integration and power are critical requirements.""Our long collaboration with IBM on SiGe technology has enabled Tektronix to break new barriers on what can be achieved in high-fidelity, high-bandwidth oscilloscopes," said Kevin Ilcisin, chief technology officer, Tektronix. "We utilized IBM's SiGe 9HP for our patent-pending asynchronous interleaving approach, and expect to break new ground by providing customers bandwidth capabilities of 70 GHz and beyond while significantly improving our signal-to-noise ratio."Key Technology Details, Specs9HP will be the first SiGe technology in the industry featuring the density of 90nm CMOS which will enable the highest level of integration in a fully production qualified SiGe BiCMOS technology. IBM's new SiGe BiCMOS technology delivers higher performance, lower power and higher levels of integration than current 180nm or 130nm SiGe offerings.The technology maintains compatibility with IBM's 90nm low power CMOS technology platform, enabling foundry clients to port a wide range of intellectual property circuit blocks and standard cell library elements. The 90nm foundry platform also includes an RF CMOS technology option, giving IBM foundry customers a broad range of technology choices for RF and mixed-signal applications.Additional technical specifics include:90nm Lithography based SiGe BiCMOSAdvanced SiGe HBT NPNs, Ft = 300GHz, Fmax > 350GHz90nm CMOS FETs, 1.5, 2.5v/3.3vThick Dielectric Add-On Modules – Low-K, Cu, AlFull Suite of Passives-Resistors, Varactors, MOS and MIM Capacitors, High Q Inductors, mmWave elementsPIN and THz Schottky Barrier DiodesProcess Design Kits featuring precision RF device models 

One of the greatest challenges in the evolution of electronics has been to reduce power consumption during transistor switching operation. In a study recently reported in Nature, engineers at University of California, Santa Barbara, in collaboration with Rice University, have demonstrated a new transistor that switches at only 0.1 volts and reduces power dissipation by over 90% compared to state-of-the-art silicon transistors (MOSFETs).     MOSFETs have been the building blocks of everyday electronic products since the 1970s. However, to sustain the ever-growing need for increased transistor densities, miniaturization of MOSFETs has given rise to a power dissipation challenge due to the fundamental limitations of their turn-on characteristics. "The steepness of a transistor's turn-on is characterized by a parameter known as the subthreshold swing, which cannot be lowered below a certain level in MOSFETs," explained Kaustav Banerjee, Professor of Electrical and Computer Engineering at UC Santa Barbara. A minimum gate voltage change of 60 millivolts at room temperature is required to change the current by a factor of ten in MOSFETs. In essence, the existing state of transistor technology limits the energy efficiency potential of digital circuits in general. The research group of Professor Kaustav Banerjee at UC Santa Barbara took a new approach to subverting this fundamental limitation. They employed the quantum mechanical phenomenon of band-to-band tunneling to design a tunnel field effect transistor (TFET) with sub-60mV per decade of subthreshold swing. "We restructured the transistor's source to channel junction to filter out high energy electrons that can diffuse over the source/channel barrier even in the off state, thereby making the off state current negligibly small," explained Banerjee. At UCSB, Banerjee's Nanoelectronics Research Lab includes Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, and Stephan Kraemer, as well as Yongji Gong and Pulickel Ajayan of Rice University. Banerjee and his colleagues are motivated by a global electronics industry that loses billions of dollars each year to the impact of power dissipation on chip cost and reliability. "This translates into lower battery lifetime in personal devices like cell phones and laptops, and massive power consumption of servers in large data centers," adds Banerjee, pointing out the global scale of this energy demand. An industry that relies on conventional semiconductors such as silicon or III-V compound semiconductors as the channel material for TFETs, Banerjee explains, "faces limitations because these materials have high density of surface states, which increase leakage current and degrade the subthreshold swing." The TFET designed by the UCSB team overcame this challenge in a few ways, most significant being the use of a layered two-dimensional (2D) material called molybdenum disulphide (MoS¬2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3nm. The resulting vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS¬2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area. "The crux of our idea is to combine 3D and 2D materials in a unique heterostructure, to achieve the best of both worlds. The matured doping technology of 3D structures is married to the ultra-thin nature and pristine interfaces of 2D layers to obtain an efficient quantum-mechanical tunneling barrier, which can be easily tuned by the gate," commented Deblina Sarkar, lead author of the paper and PhD student in Banerjee's lab. "We have engineered what is, at present, the thinnest-channel subthermionic transistor ever made," said Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve subthermionic subthreshold swing (~30 millivolts/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1V. Ajayan, co-author and professor of chemical and biomolecular engineering at Rice University, commented, "This is a remarkable example showing the uniqueness of 2D atomic layered materials that enables device performance which conventional materials will not be able to achieve. This is perhaps the first breakthrough in a series of novel devices that people will now aspire to build using 2D materials." "The work is a significant step forward in the search for a low voltage logic transistor. The demonstration of sub-thermal operation over four orders of magnitude is impressive, and the on-current also advances the state-of-the-art. There is still a long ways to go, but this work demonstrates the potential of 2D materials to realize the long-sought, low-voltage device," commented Mark Lundstrom, professor of electrical and computer engineering at Purdue University. "We have demonstrated how to achieve the most important metric of steep subthreshold swing that meets ITRS requirements. Our transistor can be utilized for a number of low-power applications including arenas where the steep subthreshold swing is the main requirement, such as biosensors or gas sensors. With improved performance, the range of applications of this transistor can be further expanded," explained Wei Cao, a PhD student in Banerjee's group and a co-author of the article. "This work represents an important step of bringing 2D materials closer to real applications in electronics. The use of 2D materials in tunneling transistors started only recently, and this paper gives the whole field yet another strong boost in improving the characteristics of such devices even further," commented Dr. Konstantin Novoselov, a professor of physics at University of Manchester. Novoselov was co-recipient of the 2010 Nobel Prize in Physics, awarded for the discovery of graphene. "When I first heard Banerjee's idea of using 2D materials for designing inter-band tunneling transistors in 2012, I recognized its merit and immense potential for ultra-low power electronics. I am pleased to see that his vision has been realized," commented James Hwang, professor of electrical engineering at Lehigh University, who was then the AFOSR program manager responsible for funding this research.    

A new compact transistor model was developed and the framework for realizing a faster design support process and product development for integrated circuits in the ultra-low voltage category was established. The new compact model, HiSIM-SOTB (Hiroshima University STARC IGFET Model Silicon-on-Thin BOX), was developed by Hiroshima University's HiSIM Research Center in collaboration with its partners in the industry and government institutions, including the National Institute of Advanced Industrial Science and Technology (AIST) of Japan. On June 20, 2014, after a two-year-long effort by the industry/government/academia research team, this new model was selected as an international industry standard during a meeting in Washington D.C., which was held by the Compact Modeling Coalition (CMC) of the Silicon Integration Initiative (Si2).HiSIM-SOTB accurately replicates the characteristics of the SOTB-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is expected to become a practical transistor structure for super-low-power-consumption by lowering the operating voltage of integrated circuits. The research team, which was led by Prof. Mitiko Miura-Mattausch, HiSIM Research Center of Hiroshima University (headed by Prof. Hans Jurgen Mattausch) and Dr. Hanpei Koike, Leader, Electroinformatics Group, Nanoelectronics Research Institute (headed by Dr. Tetsuji Yasuda) of AIST, successfully implemented the loop between Hiroshima University's development of the transistor model and AIST's reproduction tests of measured data. The results verify that HiSIM-SOTB enables the accurate simulation of circuit operations in the case of substantially lowered supply voltages for transistor operation, ranging from 1 V to 0.4 V.By solving the Poisson equation, HiSIM-SOTB accurately finds the surface potentials at three required positions: the upper and lower sides of the ultrathin SOI (Silicon-on-insulator as a silicon channel layer) film, and the upper side of the substrate. For this purpose, the device physics was represented using three basic equations. To solve these equations including the three surface potentials, it was necessary to address the challenge of stably solving the third-order Newton equation in order to obtain their numerical solutions. However, by developing an appropriate algorithm, the research group has enabled HiSIM-SOTB to accurately reproduce the changes in the substrate-carrier concentration and in the carrier distribution as a function of the applied substrate bias voltage. In parallel, HiSIM-SOTB includes a variety of ingenious twists to shorten the calculation time. HiSIM-SOTB has subsequently been completed as an ultimate compact model that is applicable to any device structure.During the early stages of the development of HiSIM-SOTB, the cooperation that leveraged the strengths of each of our partners in industry, government, and academia was beneficial. This collaboration was carried out based on each partner's previous attempts to realize a standardized compact transistor model. The realization of this effective and rapid cooperation was one of the major reasons why the research team could solve the problems related to the perfection of a compact model for the standardization within the limited time available. Indeed, this collaboration has enabled the ideal scenario to be realized, in that before finalizing the device's design, the evaluation of the circuit characteristics was completed, and an environment for large-scale circuit design was already established.