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Warm hints: The word in this article is about 4000 words and  reading time is about 20 minutes.SummaryThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of system clock and the delay of clock to ensure the stability of design. CoreClock in FPGA designPurposeDetermining the influencing factors of clock to ensure the stability of designEnglish nameField Programmable Gate ArrayCategoryDigital electronic circuitFunctionCreating digital circuitsFeatureTotally up to the designer to create a bit fileCatalogsCatalogsⅠ. What is Setup time and Hold timeⅢ. Analyzing with the help of timing diagram3. The composition of the state machine1. Synchronization between single bits and each pulse transmitted has at least 1 cycle width1. Setup timeⅣ. How to increase the clock working frequencyⅤ. An example showing a good method for state machine design2. The input pulse could be less than a synchronous circuit under a clock cycle width 2. Hold time1. Changing the line type for circuit wiringⅥ. The introduction of state machine Ⅱ. A basic model of synchronous design using a single clock2. Splitting the combinational logicⅦ. What we should pay attention when designing the clock in FPGA  IntroductionⅠ. What is Setup time and Hold timeThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of the system clock and the delay of the clock to ensure the stability of the design.Learn how a clock drives all sequential logic in FPGA, from Flip-Flops to Block RAMs; The clock tells you how fast you can run your FPGA;This video demonstrates how to properly deal with multiple clock domains inside your design.1. Setup timeSetup time(Tsu) is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.2. Hold timeHold time(Thd) is defined as the minimum amount of time after the clock's active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.Figure 1 Shows setup time and hold timeFigure 2 If data will change in tsu then it will cause setup violation and if data will change in thd then it will cause hold violation  DtailⅡ. A basic model of synchronous design using a single clockIn the same module of FPGA design, it often contains the combinational logic and the sequential logic. In order to guarantee the data in this logic interface can be processed steadily, then figuring out the concept of setup time and hold time is very important. Then we could be able to think about this following question:Figure 3 Shows a basic model of synchronous design using a single clockTco: Delay of the data output of the trigger;Tdelay: Delay of the combinational logic;Tsetup: The trigger's setup time;Tpd: Delay of the clock (negligible).T: clock cycleT3: D2 setup timeT4: D2 hold timeIf the first trigger D1 has a maximum setup time of T1max and a minimum of T1min, the combinational logic has a maximum delay of T2max and a minimum of T2min. The question is what conditions setup time T3 and hold time T4 of the second trigger D2 should be met, or what the maximum clock cycle given T3 and T4. This is the thing must be carefully considered in the process of design, because only by clarifying this issue can we ensure that the delay of the  combinational logic designed meets the requirements.Ⅲ. Analyzing with the help of timing diagramNow let us analyze this question with the help of timing diagram: let the input of the first flip-flop be D1, the output be Q1; the input of the second flip-flop be D2, the output be Q2;Given the clock is uniformly sampled on the rising edge, for ease of analysis we would discuss two cases, the first one: Assume that the delay of the clock Tpd is zero, which in fact, is often met in the FPGA design where the unified system clock it is generally adopted and the clock be input through the global clock pin, therefore the internal clock delay can be completely ignored. In this case, it is not necessary to consider the hold time, because each data maintains one clock tick while there is also delay line, that is, the delay based on CLOCK is much smaller than the delay based on data, so the hold time can meet the requirement. The setup time is what we should care about. If the setup time D2 meets the requirement, the timing diagram should be as shown as Figure 4.Figure 4 Shows the timing chart that meets the requirementsFrom the figure 4 we can see:T-Tco-Tdelay>T3That is Tdelay< T-Tco-T3During the setup time D2, the signal can reach D2 through the combinational logic D1, i.e. the data is already in Tsup before the second CLK arrive.Then it meets the requirement of setup time, where T as the clock period, the second flip-flop can pick up D2 on the rising edge of the second clock in this case. {D1 => setup time => hold time => trigger data output delay => combinational logic delay => D2 => ...}If the delay time of the combinational logic is too largeT-Tco-Tdelay < T3 (Tcox<D2 setup time)Then it will not meet the requirements. The second trigger will pick up an unstable state on the rising edge of the second clock, as shown in Figure 5, then the circuit will not work properly.Figure 5 The delay time of the combinational logic is too large to meet the requirementsSo you can deriveT - the Tco - T2max > = T3This is the setup time for D2.From the timing diagram above, it also can be seen that the setup time and hold time of D2 are not related to the setup and hold time of D1, except the combinational logic in front of D2 and the data transmission delay of D1. This is also a Very important conclusion, which shows that the delay has no additive effect.However, if there is a delay in the clock instead, the hold time must be considered in this case, together with the setup time. Most clocks with large delays are designed using asynchronous clocks, which is difficult to guarantee the data synchronization, so it is rarely used in actual designs. At this point, if the setup time and hold time all meet the requirements, you will see the output timing as shown in Figure 6.Figure 6. Clock has a delay but meets the timingIt can be easily seen from figure 5 that the Tpd is relaxed for the setup time, so the setup time of D2 must meet the requirements:Tpd+T-Tco-T2max>=T3 (T3 is the setup time of D2, T2max is the maximum delay of  combinatorial logic, Tpd is the clock delay)As shown in the FIG. 6, since the sum of setup time and hold time is a stable clock period (T), if the clock has a delay and the data delay is small, then the setup time will increase inevitably,  and the decrease of hold time goes with it. If it is reduced to not meet the requirement of hold time D2 , the correct data cannot be collected.That is T-(Tpd-Tco-T2min)T-(Tpd+T-Tco-T2min)>=T4 i.e. Tco+T2min-Tpd>=T4 (D2 hold time )From the formula above we could also figure out that if Tpd = 0, that is to say the delay of the clock is 0, then the same requirements goes with Tco + T2min> T4, however in practical applications the delay of T2 i.e. the delay of line is much larger than the trigger's hold time T4, it becomes not necessary to take the hold time into consideration.Figure 7 The clock has a delay and the hold time does not meet requirementsIn summary, if you do not consider the delay of the clock, the only thing you need to care about is the setup time, or the hold time instead. Then let us think about in FPGA design, how to increase the working clock in the synchronous system. AnalysisⅣ. How to increase the clock working frequencyFrom the above analysis, we can see that the requirements of setup time T3 for the D2 in the synchronization system is as follows:T-Tco-T2max>=T3So it is easy to derive:T>=T3+Tco+T2maxwhere T3 is the setup time Tset of D2, and T2 is the delay time of the combinational logic. In a design, T3 and Tco are both fixed values determined by the device, the only factor that we could control is the input delay of the combination logic T2. Therefore, by reducing T2 as much as possible, the clock working frequency can be increased. In order to achieve the reduction of T2 in the design, there are different comprehensive methods we can use.1. Changing the line type for circuit wiringAltera devices, for example, there are many bars in the quartus timing closure floorplan, so we can slice and dice them into rows and columns: Each bar represents 1 LAB, each LAB has 8 or 10 LEs in. The relationship of their routing delay is as follows: the same LAB (fastest) < the same row and column < different row and column. We could add appropriate constraints to the synthesizer (this should be given appropriate, generally 5% margin adding, for example, if the circuit works at 100Mhz, then adding constraints to 105Mhz is sufficient, because the excessive constraint could do a bad effect instead, and greatly increases the integration time) to make the relevant logic circuit wiring be placed as close as possible, thereby reducing the routing delay.2. Splitting the combinational logicSince the general synchronous circuits are more than a?single?stage latch (as shown in Figure 9), and to make the circuit stable, the clock period must meet the maximum delay requirement, and the maximum?delay of the longest path can be shortened before the operating frequency of the circuit be increased.As shown in Figure 8, we can decompose the larger combinatorial logic into smaller blocks and insert flip-flops in the middle, which can increase the operating frequency of the circuit. This is also the basic principle of the so-called "pipelining" technology.For the upper part of Figure 9, its clock frequency is subject to the delay of the second larger combinational logic. By appropriately distributing the combinational logic, excessive delay between the two flip-flops can be avoided and speed bottlenecks can be eliminated.Figure 8 Splitting combination logicFigure 9 Transferring Combination LogicHow to split the combinatorial logic in design, the better method should be accumulated in practice, but some good design ideas and methods also need to be mastered. We know that at present most of the FPGAs based on 4-input LUTs, if an output criteria corresponding is more than four inputs, then the multiple LUT cascade will be needed, thus introducing the delay of one-stage combinational logic. That is we want to reduce the number of combinational logic, the logic is nothing more than to make the input conditions as few as possible, so that less multiple LUT cascade need to be use, thereby reducing the time delay caused by combinational logic.The pipelining that we usually hear is a way to increase the operating frequency by splitting a large combinational logic (in the middle of which a singer or multiple stages of D flip-flops are inserted, thereby reducing the number of combinatorial logic between registers) to a smaller one. For example, a 32-bit counter, with a very long carry chain, will inevitably reduce the operating frequency, so we can split it into a 4-bit and a 8-bit one, whenever the 4-bit counter counts to 15 and triggers an 8-bit one, which enable the counter to be split and increases the operating frequency.Just as the same, large counters are generally moved out of the state machine, because if they, with usually more than 4 inputs, are used as state transition criteria with other conditions, they will increase the multiple LUT cascade, and then increasing the combination logic.Taking a 6-input counter as an example, we wanted to make a state transition after the counter counted to 111100, now because we put the counter out of the state machine, when it counts to 111011, a signal of "enable" is generated and then trigger the state transition, which obviously reduces the combinatorial logic.3. The composition of the state machineThe state machine generally contains three modules:An output moduleA module that determines what the next state isA module that saves the current stateThe logic used to form these three modules is also different. The output module usually contains both combinatorial logic and sequential logic; the module that determines the next state is usually composed of combinatorial logic; and the module that saves the current state is usually composed of sequential logic. The relationship between these three modules is shown in Figure 10.Figure 10 The composition of the state machineⅤ. An example showing a good method for state machine designThat is why when writing the state machine, the state machine is always divided into three parts according to these three modules. The following example shows a good method of state machine design: -----------------------------------------------------*/module arbiter2 (                    clock , // clock                    reset , // Active high, syn reset                    req_0 , // Request 0                    req_1 , // Request 1                    gnt_0 ,                    gnt_1                );//-------------Input Ports-----------------------------input    clock ;input    reset ;input    req_0 ;input    req_1 ;//-------------Output Ports----------------------------output    gnt_0 ;output    gnt_1 ;//-------------Input ports Data Type-------------------wire    clock ;wire    reset ;wire    req_0 ;wire    req_1 ;//-------------Output Ports Data Type------------------reg        gnt_0 ;reg        gnt_1 ;//-------------Internal Constants--------------------------parameter     SIZE = 3 ;parameter     IDLE = 3'b001 ,            GNT0 = 3'b010 ,            GNT1 = 3'b100 ;//-------------Internal Variables---------------------------reg        [SIZE-1:0] state ;        // Seq part of the FSMwire    [SIZE-1:0] next_state ;    // combo part of FSM //----------Code startes Here------------------------assign    next_state = fsm_function(req_0, req_1);//------------fsm_function--------------//function [SIZE-1:0] fsm_function;input     req_0;    //parameterinput     req_1;    //parameterbegin    case(state)        IDLE :                if (req_0 == 1'b1)                    fsm_function = GNT0;            else if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function = IDLE;        GNT0 :             if (req_0 == 1'b1)                fsm_function = GNT0;            else                fsm_function = IDLE;        GNT1 :            if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function =IDLE;        default : fsm_function = IDLE;        endcaseendendfunction always@(posedge clock)begin    if (reset == 1'b1)        state <= IDLE;    else        state <= next_state;end//----------Output Logic-----------------------------always @ (posedge clock)begin    if (reset == 1'b1)         begin        gnt_0 <= #1 1'b0;        gnt_1 <= #1 1'b0;        end    else         begin        case(state)            IDLE :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end            GNT0 :                 begin                gnt_0 <= #1 1'b1;                gnt_1 <= #1 1'b0;                end            GNT1 :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b1;                end            default :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end        endcase        endend // End Of Block OUTPUT_Endmodule Ⅵ. The introduction of state machineState machines are usually written in three segments to avoid excessive combinational logic.All we mentioned above shows how we could use the way of pipelining to split the combinational logic, but in some cases it is difficult for us to do that, and then what should we do?The state machine is such an example that we cannot add assembly line in the state decoding combinational logic. If there is a design of state machine with dozens of states, there is no doubt that its state decoding logic will be very large and this will be the critical path in the design. So what should we do?Just the same way, reducing the combinatorial logic. We can analyze the output of the state, reclassify and redefine them into a group of small state machines. By selecting the input (case statement) and triggering the corresponding small state machine, we can achieve a large state machine splitting into several small state machines. In the ATA6 specification (hard disk standard), there are about 20 kinds of input commands, and each piece of command corresponds to a variety of states. It is unthinkable to do it with a large state machine (nesting), however in the contrary, if you use the case statement to decode the command and trigger the corresponding state machine, in this way the module can run very fast.The key to increasing the operating frequency is to reduce the time delay from register to register, and the most effective method for reduction is to avoid large combinational logic, that is, to try to meet the four-input condition, reducing the number of LUT cascades, that’s mean that we could increase the working frequency by adding constraints, using a way of pipelining and splitting states.Ⅶ. What we should pay attention when designing the clock in FPGA1.Try to use only one clock in a module, and a module here means a module or an entity. In the design of multi-clock domain, it is better to have an extra special module for the isolation of clock domain. This allows the synthesizer to get a better results.2. Unless it is a low-power design, otherwise do not use the gated clock (gllobal Clock buffer such as IBUFG within FPGA) to control the input of clock edge of flip-flop, but use combinational logic and other timing logic (such as frequency divider) to generate signals used as the input of clock edge of flip-flop---all this is to reduce the instability of the design.3. Do not use the signals divided by counter as the clock of other modules, but  with the help of clock enable(CE). Otherwise, this clock-like manner is extremely unfavorable to the reliability of the design, and greatly increases the complexity of the static timing analysis .Ⅷ. Synchronization Between Different Clock DomainsIf two modules in a design using two respective operating clock, then at their interfaces there would emerge a phenomenon which called as Asynchronous Patterns. In order to ensure data correct processed, the two modules must be synchronized.There are usually two cases of different clock domains here (discrete clock source):1. the frequency of two clocks is different;2. the two clocks share a same frequency, but they are actually two separate clocks with no relation to the phase.Just as shown in the following two figures:Figure 11 The frequencies of two clocks are completely differentFigure 12 The frequencies of the two clocks are the same, but the phases are irrelevantThe data transmission between two clock domains usually adopts different synchronization methods according to different bit widths.1. Synchronization between single bits and each pulse transmitted has at least 1 cycle widthThis kind of synchronization is mainly used for the synchronization of some control signals. As shown in Figure 13 below:Figure 13 One bit synchronizer designThe following points are required to be explained for this synchronization:(1) synchronous circuit of figure 12 is actually called "one bit synchronizer", it can only be used for one bit asynchronous signal which must be wider than that of the Current stage’s clock, otherwise it may be unable to adopt this asynchronous signal.(2) why is the circuit in figure 13 can only be used in one bit asynchronous signals?When two or more asynchronous signals (control or address) simultaneously get into the current time domain and take control the circuit of current time domain, problems arise if these signals are all synchronized using the same circuit in FIG. 13. Skews has arisen between two or more asynchronous signals (control or address) due to connection delays or other delays, and then the skew is greatly enlarged via the synchronizer in Figure 13 when getting into the current time domain, or competition may caused and finally leading to an error in the time domain circuit.Figure 14 Problem-passing multiple control signals between clock domainsIf the asynchronous data bus is to enter the current time domain, the circuit in Figure 13 cannot be used either, because data change very randomly and the width of 0 or 1 has nothing to do with the clock pulse of the current time domain, so the circuit in Figure 13 may be unable to adopt the correct data.(3) Please note that the second trigger is not used for avoiding the occurrence of "metastable state", on the contrary, it can prevent the transmission of metastable state. In other words, once the first flip-flop becomes metastable (possibly), due to the second flip-flop, the metastability will not be transmitted to the circuit following.(4) The first-stage trigger has a metastable state, which means it will require a recovery time to stabilize again, or it is also called Withdrawal from metastable state. The recovery time plus the establishment time of the second-stage flip-flop (say more precisely, maybe also minus the clock skew) is less than or equal to the clock period, which can be easily satisfied. This is means thees two stages of flip-flop should be put together as close as possible, without any combinatorial logic between them or excessive skews to the clock, and then the second-stage flip-flop can adopt data stably and preventing the transmission of metastable state.(5) FF1 is the sampling output of FF2, so of course, what is output by FF1 is  what output by FF2, everything is the same except one cycle of delay. Note that “meta-stableit” means that once the data of FF1 enters, its electrical level would be indefinite and maybe incorrect. So although this method can prevent transmission of metastable state, it does not guarantee the data after the two-stage flip-flop is correct. Therefore, this kind of circuit always has a certain amount of fault-tolerance. This applies only to a some error-insensitive cases, but for other sensitive circuits, dual-port RAM or FIFO are better choices.2. The input pulse could be less than a synchronous circuit under a clock cycle width How is that possible? Has it not less than the original clock? For this case, the Feedback shown in Figure 15 below may usually be taken into consideration. The analysis of this circuit is as follows: Assume that the input data is high level, because the first flip-flop FF1 is high-level cleared, then all outputs should also be high and correctly adopted. On the other hand, if the input is low-level, data of FF1 would be forced to clear and the output level is zero, which ensures the correctness of the output.Figure 15 Synchronous circuit--input pulse may be less than one clock cycle width  Book SuggestionBuilding Embedded Systems: Programmable Hardware 1st ed. EditionThis is a book for embedded-system engineers and intermediate electronics enthusiasts who are seeking tighter integration between software and hardware. Those who favor the System on a Programmable Chip (SOPC) approach will in particular benefit from this book. Students in both Electrical Engineering and Computer Science can also benefit from this book and the real-life industry practice it provides.--Changyi GuDigital Integrated Circuit Design Using Verilog and Systemverilog 1st Edition, Kindle EditionFor those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. --Ronald W. MehlerPower Converters with Digital Filter Feedback Control 1st Edition, Kindle EditionThis book builds a bridge for moving a power converter with conventional analog feedback to one with modern digital filter control and enlists the state space averaging technique to identify the core control function in analytical, close form in s-domain (Laplace). It is a useful reference for all professionals and electrical engineers engaged in electrical power equipment/systems design, integration, and management.--Keng C. Wu Relevant information "Discussion on the influencing factors of clock in FPGA design"About the article "Discussion on the influencing factors of clock in FPGA design", If you have better ideas, don't hesitate to  write your thoughts in the following comment area. You also can find more articles about electronic semiconductor through Google search engine, or refer to the following related articles.To Solve the Problems of Cloud Skyrocket--Edge ProcessingFPGAs Power Facial Recognition Technology Was Issued by NECNew Software for C2000 MCUs Eliminates the FPGA in industrial designsCustomisable Ethernet switch designed for embedded applicationsMouser signs Intel FPGA board firm ReFLEX CES

Warm hints: The word in this article is about 3000 words and  reading time is about 15 minutes.   This paper is mainly about how to learn analog circuit design. An analog circuit is a circuit used to transmit, transform, process, amplify, measure, and display analog signals. Analog signals refer to continuously changing electrical signals. Analog circuit is the basis of the electronic circuit, which mainly includes amplifier circuit, signal processing, and processing circuit, oscillation circuit, modulation and demodulation circuit, and power supply.    Analog circuit   Catalogs   I. What’s the Engineering Thinking in Analog Circuit II. Commonly Used Semiconductor Devices III. Negative Feedback Basic Concepts IV. Operational Amplifier Development V. Conclusion FAQ I. What’s the Engineering Thinking in Analog Circuit   Analog circuit is a very important profession, and difficult for people to learn. Now, let me talk about my understanding of the analog circuit. When it comes to the understanding and application of analog circuits, I’ve done some projects and participated in competitions. The analog circuit is an engineering course, and the earning focus is to master the engineering ideas. It’s better to put it into practice, instead of only doing the exams. What is the engineering idea? Encyclopedia +explains as this: "Engineering is the application of science and mathematics. Through this, natural material and energy characteristics can be made into efficient, reliable, and human-friendly products flow through a variety of structures, machines, products, systems, and processes, with the shortest Time, and less refined manpower, so the concept of engineering comes out and it has evolved into an independent discipline and skill. "For example, in analog circuits, there is a very Important engineering thinking - approximation.   In high school physics class, we learn a lot of circuits are ideal circuits. The wire resistance is always 0, the transformer efficiency is 100%, the ideal voltmeter resistance is infinite, the ideal ammeter resistance is 0, and so on. You can see that many times the calculation in an analog circuit will often omit one or two smaller items and use the equal sign instead of the equal sign directly.   Why use an approximation? To put it plainly, people’s understanding of nature in human science is not comprehensive enough to describe the natural phenomenon with absolute precision. Or human’s understanding is limited. By the means of approximation, people have not only achieved an obvious effect on solving the problem but also greatly simplifies the procedure and saves time and effort. With this thought, many achievements have been made in human science, which has also proved its reliability.    Summary Mold itself is a very complex subject, and the molding course is just one of the most basic things. Analog Circuit Meaning is the electronic circuit that processes analog signals. Most of the signals in nature are analog signals, and they have continuous amplitude values, such as the sound signal when speaking. Analog circuits can be such signal processing (of course, need to be converted into electrical signals), such as amplifier to amplify the sound signal, the radio can send analog sound signals, image signals. It can even be assumed that all circuits are based on analog circuits (even for digital circuits, the underlying principle is based on analog circuits). Its importance is self-evident.    Due to the rapid development of digital circuits and programmable devices, many superior features are demonstrated. Many electronic devices are slowly digital but still can not do without analog circuits. The most important analog circuit devices, non-semiconductor devices are none other than. The most basic and commonly used semiconductor devices are diodes, transistors, FETs, and operational amplifiers. II. Commonly Used Semiconductor Devices   The diodes have many roles. Ordinary diodes can be used for rectification, light-emitting diodes can be used for indicator and lighting, regulators can be regulated, varactor diodes can be used for signal modulation. The mold course related to the part of the diode is relatively simple. And many characteristics of the FET are similar to the transistor, so we often explain transistor or amplifier instead.    The basic function of the transistor is to enlarge. The transistor constitutes a variety of circuits because of its features, reflecting a lot of engineering ideas. The transistor-based circuit is the amplifier whose input sound is small, the output sound is great. Amplifier output and the input voltage (or current) ratio is called magnification, also known as gain. For a voltage, if the time for the horizontal axis, voltage vertical axis for mapping, the graph is the voltage waveform. If an amplifier with a gain of 5 inputs a constant voltage of 1V (the waveform on the left is shown below), the output should always be 5V (the waveform is shown in the middle figure below), neither changing with time nor changing with temperature And the input voltage exactly the same shape. However, if the magnification is unstable and constantly changing, the original input signal will be distorted (as shown on the right), and the signal may change from a horizontal straight line to a curved line. This waveform change is called distortion. Voltage waveform   III. Negative Feedback Basic Concepts   The basic concept of negative feedback makes some very powerful people find a good way: negative feedback. What is negative feedback? "Feedback refers to the output of the system is returned to the input and affect the input, thus affecting the overall system output Feedback can be divided into positive feedback and negative feedback is to make the output and input the opposite effect, the system Output tends to be stable. "The above explanation is hard to make sense. I have two examples. When playing the inverted pendulum, we propped up an inverted wooden stick by hand. When the wooden stick was tilted in one direction, we offset the change by moving the hand to the direction of the stick so that the stick could be in our hand's balance.    When I was in high school, I often had a monthly test. I found that some of my classmates had a habit of starting a good study when a test score was poor and going up next time. When the test was better, the next month will be relaxed, so results will come down again, so again and again. Both of these examples illustrate that negative feedback can make the system more stable. We ignore the specific circuit, only draw a simple diagram to illustrate how the transistor amplifier uses the negative feedback. The triangle below shows a transistor consisting of an amplifier, the magnification is A, the input is I, the output O = I * A, because the magnification A instability, so the output waveform will be distorted.  Negative feedback   Some devices have been added to the circuit as follows. The purple circle is the adder, combined with the purple "+", "-" symbol that its output Y = (+ I) + (- X) = I-X, in the actual circuit with the resistance can be achieved; Block F is the feedback device, which means that the signal is taken out from the output O and multiplied by F to get X, so X = O * F, where F <1 (this part can be realized by resistance in the actual circuit). Triangle refers to the amplifier A, mainly composed of transistors, meeting O = A * Y, and A magnification is unstable, easy to be disturbed. Add a feedback device   You can list the equations: Y = I-XO = Y * AX = O * F to calculate the gain of the entire circuit: Formula   If the magnification A is very large, while F is not small, A * F 》》1 symbol "》》" suggests far greater than the approximate idea. The entire circuit magnification: Formula   IV. Operational Amplifier Development   1.Working principle of operational amplifier Because the feedback device can be realized by the resistance, the resistance value of the ordinary resistance is not easily disturbed by the outside world, so the value of F is very steady, so the magnification of the whole circuit is very steady. We succeeded in solving the stability problem of the transistor by negative feedback. We can see here that the feedback part and the amplification part form a ring, so the amplification of the whole circuit is called the loop gain or the closed-loop gain. Before adding the feedback, the amplification of circuit A is called the open-loop gain. Due to the negative feedback, the stability of the circuit is improved, but there is also a cost: Because the AF 》》1, then "A》》1 / F" open-loop gain is much larger than the closed-loop gain, which means the amplifier gain is greatly reduced. But in general, this is worth it for stability. Operational amplifier In the above circuit, in order to actually create a large open-loop amplifier gain A, often with multi-stage transistor amplifier in series design.   Because the high demand for such high-gain amplifiers is very common, so some people in history put them into a finished circuit board module. This is used directly as a component on the line when needed because it’s very convenient. This is the original op-amp, which is referred to as op-amp. The development of integrated circuits makes a large number of transistor components integrated into a small chip possible, so the common integrated operational amplifier turns up today.    The "op-amp" is named for its mathematical operation originally used to simulate computers. Although now widely used digital computer is no longer used to calculate the operational amplifier, but the name still retained. Today, op-amps play an important role in analog circuits and have also become one of the focuses of the analog circuit. The op-amp has virtual short and virtual interrupt characteristics. Usually, op-amp has two inputs U + and U-, an output Uo, between them to meet Uo = A * (U + -U-) op-amp open-loop gain A often up to dozens Million ~ millions, but the op-amp output voltage limited by the supply voltage can not exceed the supply voltage. So the op-amp input-output relationship similar to the shape below. In the figure, the horizontal axis is (U + -U-) and the vertical axis is Uo. Op amp input - output In the middle of a straight line, the op-amp is in the normal state of amplification, called the linear region, meeting Uo = A * (U + -U-). When the absolute value of the input becomes slightly larger, the output will be power limited, no longer satisfying the above relationship. The value of Uo is usually slightly smaller than the supply voltage range (note that the op-amp can be dual supply, that is the supply voltage range can be afloat between a negative value and a positive value), which is called the non-linear region. Rail-to-rail op-amp output can reach the power supply voltage.   When the operational amplifier in the linear region, the Uo value is very limited, but A large. So U + -U- = UoA ≈ 0 or U + ≈ U-. At this time, the positive and negative op-amp input voltage is almost equal, like a short circuit similarly, which is called a short circuit. So only when the operational amplifier in the enlarged area will have "virtual short" characteristics, rather than the inherent properties of the op-amp. On the other hand, due to the internal structure of the op-amp, its input impedance is large.    The input impedance can be simply understood as: the input impedance = input voltage/input current input impedance, which means that the op-amp input with only a small current can work properly. Because of this, an op-amp can be used for some weak current detection, such as the human brain, myoelectric wave, whose maximum voltage is only a few mV, the current value is very small. This feature of the op-amp is called a virtual interrupt, meaning that there is almost no current flowing into the input like the open circuit. Different from the short circuit, a virtual interrupt is the inherent properties of the op-amp, which will not change with the circuit.   2.Op amp non-ideal characteristics   The op amp's non-ideal characteristics of the op-amp by the transistor composition. Obviously, like the transistor, there will be many undesirable characteristics. The actual operational amplifier will not fully meet the short virtual fault characteristics. Its normal work needs input current input, which is called the input bias current.    The same op-amp input offset voltage, input offset voltage, input offset current, and other non-ideal parameters. These non-ideal characteristics, such as the input bias current is small, sometimes will have a great impact on the circuit, resulting in the circuit does not work. Therefore, there are some ways to reduce the impact of these factors. In practical applications, the non-ideal characteristics of the op-amp are a very important issue. There are many ways to eliminate the non-ideal characteristics of the op-amp, but not introduced here.    Other cores of the molding course are the transistor and op-amp. Around these devices, the molding course will explain a variety of circuits, including the calculation of the amplifier circuit analysis, multi-stage amplifier circuit, the amplifier frequency characteristics, the idea of feedback, power amplifier circuit, comparator, oscillator, integrator, differentiator, waveform generation, Signal processing, filter, integrated power supply circuit and so on. When comparing op-amp and transistor In the actual design of the circuit, the op-amp will be more than the transistor. Because many of the features of op-amps are better than triodes, the circuit design is simple, and the cost of op-amps is often not too high.   Many times you can achieve the same effect with the transistor and op-amp and lower cost of each op-amp. Because op-amps integrate a large number of transistors, the average cost per transistor is very low. For example, a conventional audio pre-amplifier can be handled with a universal op-amp. and if you use the transistor, you may need more transistors, and the human cost during design is far higher than the op-amp program. Of course, the transistor has its advantages.    In some very simple circuits, the stability of the magnification is not strictly required, one or two transistors can accomplish. And triodes are often used to save costs. In addition, in some extreme conditions, such as working in high-frequency and high-power environments (such as RF signal transmitting circuits), a well-designed triode circuit will perform much better than an op-amp, or at a much lower cost. Even in some conditions, only the transistors can be completed, then you need to choose the transistor to build the circuit.   This video give a detailed explanation about analog circuit: Analog Circuits Lecture V. Conclusion   Analog circuits are a very complex discipline that involves more than knowledge written in books. Books are generally introduced in accordance with the principle of work, simplifying a lot of difficulties to understand, but in reality, more factors must be considered. So the gap between the actual circuit and the book is very large. Such as triangular wave generator built with an op-amp introduced in analog circuit books usually can not work in all likelihood. However, the main principle of the actual circuit is the same as the book description. Therefore, the design of analog circuits often requires a lot of experience, for there are many things that can not be explained and even difficult to calculate. I hope this article can help you learn more about analog circuits. FAQ   1. What is meant by analog circuit? The Analog electronic circuit includes an analog signal with any continuously changeable signal. While working on an analog signal, an analog circuit alters the signal in some manner. Analog circuit can be used to convert the original signal into some other format such as a digital signal.   2. What is the difference between digital and analog circuits? Analog Circuits and Digital Circuits is a classic way of differentiating between two types of electronic circuits based on the signals they process. To put it in simple words, Analog Circuits deals with continuous analog signals whereas Digital Circuits deals with discrete digital signals.   3. Where are analog circuits used? Analog circuits represent key components of communications and other systems in widespread, growing commercial use. High-speed transistors are essential to the operation of such circuits.   4. Is digital cheaper than analog? If you are looking at the straight-up module cost an analog vs. a digital version, then yes, the analog module will likely be a cheaper solution. However, if you look at the total cost, or the “value” of the digital module versus an analog solution, then digital will in fact be “cheaper”.   5. What is analog design? Analog design is part of integrated circuit design and focuses on signal fidelity, amplification and filtering. Those who perform the function of analog design are qualified electrical engineers.   6. Why is analog design difficult? Ask most engineers and they would tell you why: analog design is harder than digital, and requires more knowledge and more factors to consider such as a deep understanding of efficient power, precision measurement, wireless connectivity, and reliable circuit protection.   7. Which is better analog or digital design? Analog circuits can be precise, elegant design with various components with very simple. For example, two resistors joining to make a voltage divider. Generally, Analog circuits are much more complex to design compared to which complete the same task as digitally.   8. What is the tool used for analog circuit design? A suite of web tools to help you design signal conditioning circuits faster: Analog Filter Wizard, Precision ADC Driver Tool, Photodiode Wizard, In Amp Diamond Plot, Direct Digital Synthesis Simulator, and Virtual Eval.   9. How hard is circuit design? Circuit design is a lot like any other learned skill, you start with the basics. These basic circuits can be learned in a few days. ... So yes, it can be very difficult to reach a high level of design expertise and you never really master it because the art continues to evolve.   10. How does circuit design work? Digital electronic circuit design takes the electrical signals in the form of discrete values. The data are represented in the form of zeros and ones. Digital circuits extensively use transistors, interconnected to give create logic gates that provide the function of Boolean logic.   You May Also Like:   Look Forward to the Future of Semiconductor GaN High-Electron Mobility Transistor Power Amplifier Trojans are everywhere even the hardware Remote Electronic Transport Promote Organic Photovaltaic Power Generation Make Next-Gen of Computer Be Faster,Better, More efficient Some suggestions about protecting transformers  

Summary As is listed in the market,there is a little of small,inexpensive switch for latching power to a load unless you buy low-current,momentary action pushbotton switches like PCB-mount‘tactile types'. However, we can get a suitable latching power switch passing by converting a pushbutton's momentary action into a latching function.   New Design Idea Previous Design Ideas have proposed solutions based on discrete components  and IC-based circuits . The circuit outlined below, however, requires just two transistors and a handful of passive components to achieve the same result.   Circuit One The circuit in Figu1(a) is configured to latch power to a low-side (ground-referred) load. It works in 'toggle' mode; that is, the first switch closure applies power to the load, the second removes power, and so on. fig1  Circuit converts momentary action push switch into latching power switch     To understand how the circuit operates, assume that the DC power supply, +VS, has just been applied, capacitor C1 is initially uncharged, and Q1 is off. The P-channel MOSFET, Q2, is held in its off state by R1 and R3, which work in series to pull the gate up to +VS, such that VGS is zero. The circuit is now in its 'unlatched' state, where the load voltage, VL, at the OUT (+) terminal is zero.   If the normally-open push switch is momentarily closed, C1 – being uncharged – pulls Q2's gate to 0V, thus turning on the MOSFET. The load voltage at OUT (+) now rises immediately toward +VS , and Q1 receives base bias via R4 and turns on. Under these conditions, Q1 saturates and pulls Q2's gate low via R3, thus holding the MOSFET on when the switch has opened. The circuit is now in its 'latched' state, where both transistors are on, the load is energized, and C1 charges up to +VS via R2.   When the switch is momentarily closed for a second time, the voltage on C1 (by now approximately equal to +VS) is transferred to Q2's gate. Since Q2's gate-source voltage is now roughly zero, the MOSFET turns off and the load voltage falls to zero. Q1's base-emitter voltage also falls to zero and the transistor turns off. Therefore, when the switch is released, there is nothing to hold Q2 on, and the circuit reverts to its 'unlatched' state, where both transistors are off, the load is de-energized, and C1 discharges via R2. Resistor R5 across the output terminals is an optional component that acts as a pull-down. When the switch is released, C1 discharges via R2 into the load. If the load impedance is very high (i.e., similar in magnitude to R2), or if it contains active devices such as LEDs, the load voltage at the instant Q2 turns off may be large enough to bias Q1 on via R4, thereby preventing the circuit from turning off properly. The presence of R5 pulls the OUT (+) terminal down to 0V when Q2 turns off, thus ensuring that Q1 turns off rapidly, and allowing the circuit to revert to its unlatched state in a proper manner.   Provided the transistors are correctly rated, the circuit will work over a wide voltage range and is well suited to driving loads such as relays, solenoids, LEDs, and so on. However, beware that certain DC fans and motors continue to rotate when their drive power is removed. This rotation can generate an EMF large enough to bias Q1 on, thereby preventing the circuit from switching off. You can eliminate this problem by inserting a blocking diode in series with the output, as shown in Fig1(b). You must also include R5 to ensure Q1 turns off properly.   Ciruit Two The complementary circuit outlined in Fig2 is intended for 'high-side' loads connected to the positive supply rail such as the relay shown in this example. fig2 Complementary circuit intended for high-side loads   Note that Q1 has been replaced with a PNP transistor, and Q2 is now an N-channel MOSFET. The circuit operates in a similar way to the one described above. Here, R5 acts as a pull-up resistor which pulls the OUT (-) terminal up to +VS when Q2 turns off, thus ensuring that Q1 turns off quickly. As in the previous circuit, R5 is optional and only necessary for the types of load mentioned previously.   Note that in both circuits, the time constant produced by C1-R2 provides for debouncing of the push switch contacts. Normally, a value of 0.25s to 0.5s should be adequate. Smaller time constants may lead to erratic behaviour, whereas a larger time constant increases the waiting time between switch closures necessary to ensure that C1 charges and discharges properly. With C1 = 330nF and R2 = 1MΩ as shown, the time constant is nominally 0.33s. This is usually sufficient to debounce the contacts and to allow the load power to be toggled after a couple of seconds or so.   Both circuits are intended to latch and unlatch in response to brief, momentary switch closures. However, they have each been designed to ensure correct operation even if the push switch is held closed for any length of time. Consider the circuit in Fig2 when Q2 is on. When the switch is pressed to unlatch the circuit, the gate is pulled down toward 0V (since C1 is uncharged) and the MOSFET switches off, allowing  the junction of R1-R2 to rise toward +VS via R5 and the load impedance. At the same time, Q1 also switches off, such that Q2's gate is pulled to 0V via the series combination of R3 & R4. If the switch is released immediately, C1 will simply charge up toward +VS via R2. However, if the switch is kept closed, Q2's gate voltage will be defined by the potential divider formed mainly by R2 and R3+R4. If we assume that the OUT (-) terminal is roughly equal to +VS when the circuit is unlatched, Q2's gate-source voltage is given by: VGS = (+VS) × (R3 + R4)/(R2 + R3 + R4) = 0.02(+VS). Even if +VS is as high as 30V, the resulting gate-source voltage of around 0.6V will be too low to switch the MOSFET on again. Consequently, both transistors remain off until the switch contacts open.   The circuit in Fig2 is latched on by momentarily closing the push switch when C1 has charged up to +VS , which causes OUT (-) to drop to 0V as Q2 immediately turns on, rapidly followed by Q1. A momentary switch closure would allow C1 to discharge to zero via R2 after the contacts open. However, if the switch is held closed, Q2's gate voltage will be defined by the potential divider formed by R2 and R3. Since Q1 is saturated, the junction of R3-R4 at Q1's collector will be pulled up to +VS, and the junction of R1-R2 will be pulled down to 0V via Q2. Therefore, with the switch held closed, Q2's gate-source voltage is given by: VGS = (+VS) × R2/(R2 + R3) = 0.99(+VS). Consequently, provided the supply voltage is at least equal to Q2's gate-source threshold voltage, both Q2 and Q1 will remain on until the switch contacts open.   Both circuits provide an inexpensive way of deriving a latching function from a momentary switch and, just like a mechanical latching switch, the quiescent (unlatched) power dissipation is zero.

Two new 0°to 360°angle sensor ICs which can provide contactless high-resolution angular position information based on magnetic Circular Vertical Hall(CVH) technology has been introduced by Allegro MicroSystems, a leader in developing, manufacturing and marketing high-performance semiconductors.Called A1333 and A12339, the devices include a system-on-chip (SoC) architecture the involves: digital signal processing,CVH front end and supports multiple digital output formats as well as the first moto commutation ouputs (UVW) and encoder output(A,B,I) for angle sensor ICs which operate at either 3.3V~5.5V.CatalogI What is A1333?II Why A1333 be designed?III What is A1339?IV Why A1339 be designed?V The 0° to 360° Angle Sensor ICs I What is A1333? The A1333 is a 360° angle sensor IC based on magnetic Circular Vertical Hall (CVH) technology that provides non-contact, low-latency, high-resolution angular position information. It has a system-on-chip (SoC) architecture that includes: CVH front-end, digital signal processing and motor commutation (UVW) or encoder outputs (A, B, I). It also includes on-chip EEPROM technology, capable of supporting up to 100 read/write cycles for flexible end-of-line programming of calibration parameters.The A1333 is ideal for automotive applications requiring 0° to 360° angle measurements, such as electronic power steering (EPS), rotary PRNDL, and throttle systems. - The A1333 supports customer integration into safety-critical applications. - The A1333 is available in a two-chip 24-pin eTSSOP and a single 14-pin TSSOP package. These packages are lead (Pb)-free and feature a 100% matte tin-lead frame plating. - All in all, A1333 is a Precision, High Speed, Hall-Effect Angle Sensor IC with Integrated Diagnostics for Safety-Critical Applications. II Why A1333 be designed?Allegro’s single and dual die A1333 devices were designed in accordance with ISO26262:2011 requirements for hardware product development for use in safety-critical applications(pending assessment). The single die version was designed to meet ASIL B requirements and the dual die was designed to meet ASIL D requirements when integrated and used in conjunction with the appropriate system level control, in the manner proscribed in the A1333 Safety Manual.Please click here to download a copy of the A1333 high speed, Hall-effect angle sensor IC data sheet.III What is A1339?  The A1339 is a 360° angle sensor IC based on magnetic Circular Vertical Hall (CVH) technology that provides non-contact, low-latency, high-resolution angular position information. It has a system-on-chip (SoC) architecture that includes: CVH front-end, digital signal processing and motor commutation (UVW) or encoder outputs (A, B, I). It also includes on-chip EEPROM technology capable of supporting up to 100 read/write cycles for flexible end-of-line programming of calibration parameters. the A1339 is ideal for automotive applications requiring 0° to 360° angle measurements, such as electronic power steering (EPS), rotary PRNDL and throttle systems. - The A1339 supports customer integration into safety-critical applications. - The A1339 is available in a two-chip 24-pin eTSSOP and a single 14-pin TSSOP package. These packages are lead (Pb)-free and feature a 100% matte tin-lead frame plating.All in all, A1339 is a Precision, High Speed, Hall-Effect Angle Sensor IC with Integrated Diagnostics for Safety-Critical Applications. IV Why A1339 be designed?Allegro’s single and dual die A1339 devices were designed in accordance with ISO26262:2011 requirements for hardware product development for use in safety-critical applications(pending assessment). The single die version was designed to meet ASIL B requirements and the dual die was designed to meet ASIL D requirements when integrated and used in conjunction with the appropriate system level control, in the manner proscribed in the A1339 Safety Manual.Please click here to download a copy of the A1339 high speed, Hall-effect angle sensor IC data sheet.  V The 0° to 360° Angle Sensor ICsThe A1333 and A1339 are available in single- and dual-mode versions for systems requiring redundant sensors. They both include on-chip EEPROM technology, capable of supporting up to 100 read/write cycles for flexible end-of-line programming of calibration parameters. Both devices are ideal for automotive applications requiring angular measurements from 0° to 360°, such as motor position measurements for steering and braking systems and other high-speed actuators for pumps and transmissions that require low latency and high resolution. a1339 alsoThe A1339 also includes an integrated turns counter and a low power mode feature that allows it to track changes in the target magnetic field in automotive applications, even when the vehicle is in a "key off" state.Both the single-mode and dual-mode A1333 and A1339 devices are designed to meet the hardware development requirements of ISO 26262:2011 (to be evaluated). The single-chip version is targeted to meet ASIL B requirements, while the dual-chip product is designed to meet ASIL D requirements when used in conjunction with appropriate system-level controls. The stacked nature of the dual-chip assembly provides better channel-to-channel matching than traditional side-by-side assembly techniques. This is a key parameter in safety critical applications where the outputs of two sensors are compared to ensure safe system operation.  

Every time you want to create a printed circuit board (PCB), you need to design holes, pads, and traces for your circuit. Then you send this design to a manufacturer or etch it yourself. What if you want to create a circuit board by yourself but it sounds hard? Don't worry, there are many free and affordable tools available that will help you do this. There are just a few steps you need to go through, and anyone can do it – even if you have no prior experience.I What is a PCB?According to Wikipedia, a printed circuit board (PCB) mechanically supports and electrically connects electronic components using conductive tracks, pads, and other features etched from copper sheets laminated onto a non-conductive substrate. Components (e.g., capacitors, resistors, or active devices) are generally soldered onto the PCB. Advanced PCBs may contain components embedded in the substrate, and modern designs can include multiple layers (from single-layer to 50+ layers for complex applications).Printed circuit boardWould you like to make your own smart device? Or IoT controller? Or robot? Or drone? Well, then you would want to make a printed circuit board. PCBs are the foundation of virtually all modern electronics!A printed circuit board is typically made from FR-4 (Flame Retardant 4), a composite material made of woven fiberglass cloth with an epoxy resin binder that is flame resistant. While green is the traditional and most common color due to the green solder mask, PCBs now come in various colors including blue, red, black, white, yellow, and even matte black for aesthetic purposes. The solder mask protects the copper traces from oxidation and prevents solder bridges during assembly.On the board, there are components. Initially, the PCB is bare, but you solder the components onto the board following your design. Modern PCBs can use through-hole technology (THT) or surface-mount technology (SMT), with SMT being more common in contemporary designs due to its compact size and automated assembly capabilities.II How to Make a Printed Circuit Board?To make a printed circuit board you need to:1. Design schematics2. Create the PCB layout3. Generate manufacturing files (Gerber files)4. Get the board manufactured and assembled2.1 Design SchematicsThe first and most important step in PCB design is to start with your schematics. This is the blueprint of your circuit that shows how all components connect electrically.Before you start drawing traces and placing components, you need to know what circuit you want to build. You need to find or design schematics for your circuit and choose appropriate PCB design software. Popular options in 2025 include:KiCad - Free, open-source, and very powerfulEasyEDA - Free, web-based with integrated manufacturingAltium Designer - Professional-grade (paid)Eagle (Autodesk) - Popular hobbyist choice with free tierFusion 360 Electronics - Integrated with 3D CAD (paid)CircuitMaker - Free community-driven platform2.2 Create the PCB LayoutStart by drawing your schematic diagram into the software you have chosen. You need to define the connections (nets) between different components.This process involves placing component symbols and connecting them with wires that represent electrical connections. Modern PCB software will check for electrical rule violations (ERC - Electrical Rule Check) to catch errors early.Schematic design exampleNext, you transfer your schematic into a physical PCB layout. This involves:Component placement - Arranging components efficiently on the boardRouting traces - Drawing copper connections between padsPower and ground planes - Creating solid copper areas for power distributionDesign rule checking (DRC) - Ensuring your design meets manufacturing constraintsDrawing PCBs is both technical and artistic. Take your time and follow PCB design best practices:Keep traces as short as possible, especially for high-frequency signalsMaintain proper trace width for current requirements (use trace width calculators)Provide adequate spacing between traces (typically 6-8 mils minimum)Use ground planes to reduce noise and improve signal integrityConsider thermal management for power componentsPlace decoupling capacitors close to IC power pinsPCB layout exampleWill you put the circuit board in an enclosure? Consider the mechanical constraints: tall components might need specific placement, mounting holes must align with your enclosure, and connectors should be accessible. Print out your board design at 1:1 scale to verify physical fit before manufacturing.2.3 Manufacturing Your PCBWhen you finish your layout, it's time to prepare your design for manufacturing. You'll need to generate Gerber files (the industry standard format) and a drill file. Most PCB software can export these automatically.Home Etching vs. Professional Manufacturing:Home Etching:Pros: Immediate results, good for learning, no minimum order quantityCons: Limited to single or double-layer boards, requires chemicals (ferric chloride or cupric chloride), lower precision, manual drilling required, no solder mask or silkscreen, time-consumingProfessional Manufacturing (Recommended for 2025):Pros: High quality, multi-layer capability, solder mask and silkscreen included, plated through-holes, very affordable (as low as $2-5 for small boards), quick turnaround (2-7 days)Cons: Requires waiting for shipping, minimum order quantities (though often just 5 pieces)Popular PCB Manufacturers in 2025:JLCPCB - Very affordable, fast turnaround, assembly services availablePCBWay - Good quality, competitive pricing, excellent customer serviceOSH Park - USA-based, high quality, purple PCBsALLPCB - Budget-friendly optionEurocircuits - European manufacturer, excellent qualitySeeed Studio - Fusion PCB service, good for prototypesMany manufacturers now offer PCB assembly services (PCBA), where they'll solder the components for you. This is increasingly affordable and saves significant time, especially for SMT components.Frequently Asked Questions (FAQ)1. How much does it cost to make your own circuit board?As of 2025, PCB manufacturing costs have decreased significantly. For prototypes, you can get simple PCBs manufactured for as little as $2-5 for 5 pieces (100mm x 100mm or smaller). More complex boards with multiple layers, special materials, or larger sizes will cost more. PCB assembly costs typically range from $0.50 to $5 per component placement, depending on component type and quantity. For a complete assembled board, expect to pay $20-100 for small quantities, with costs decreasing significantly for larger production runs (hundreds or thousands of units).2. How do you design and specify printed circuits?The PCB design process follows these steps:Schematic capture - Create the electrical circuit diagramSimulation - Verify circuit functionality (optional but recommended)Component selection - Choose specific parts with appropriate footprintsBoard setup - Define board dimensions, layers, and design rulesComponent placement - Position components strategicallyRouting - Connect components with copper tracesPower plane design - Create ground and power distribution layersDesign rule check (DRC) - Verify manufacturabilityGenerate manufacturing files - Export Gerber and drill filesCreate BOM - Bill of Materials for component procurementAssembly documentation - Create assembly drawings and pick-and-place files3. What does a printed circuit board do?A printed circuit board serves two primary functions: it provides mechanical support for electronic components and creates electrical connections between them using conductive copper pathways. The PCB eliminates the need for point-to-point wiring, making electronic devices more reliable, compact, and manufacturable at scale. Modern PCBs also provide electromagnetic shielding, heat dissipation, and can integrate additional features like impedance-controlled traces for high-speed signals, embedded components, and flexible or rigid-flex sections.4. What is a printed circuit board called?Printed circuit boards are known by several names:PCB - Most common abbreviationPrinted Wiring Board (PWB) - Emphasizes the wiring aspectPrinted Circuit Assembly (PCA) - When components are already mountedPrinted Circuit Board Assembly (PCBA) - Fully assembled boardCircuit Board - General termThe term "printed" refers to the manufacturing process where the circuit pattern is printed onto the board, though modern manufacturing uses photolithography rather than literal printing.5. What is the difference between PCB and PWB?The terms PCB (Printed Circuit Board) and PWB (Printed Wiring Board) are often used interchangeably, but there's a subtle distinction:PWB typically refers to the bare board with only copper traces, pads, and holes - no components mountedPCB can refer to either the bare board or the assembled board with componentsPCBA or PCA specifically refers to the assembled board with all components solderedIn practice, most people use "PCB" to refer to both bare and assembled boards, with context determining the meaning.6. What is a printed circuit board made of?PCBs consist of several layers:Substrate - Usually FR-4 (fiberglass-reinforced epoxy), but can be FR-1, FR-2, CEM-1, CEM-3, polyimide (for flexible PCBs), aluminum (for LED boards), or Rogers material (for high-frequency applications)Copper layers - Typically 1 oz/ft² (35 μm) or 2 oz/ft² (70 μm) thickness, laminated to the substrateSolder mask - Protective polymer layer (usually green, but available in other colors) that prevents solder bridges and protects copper from oxidationSilkscreen - White (or other color) ink layer showing component designators, logos, and other markingsSurface finish - Protects exposed copper pads; options include HASL (Hot Air Solder Leveling), ENIG (Electroless Nickel Immersion Gold), OSP (Organic Solderability Preservative), or immersion silver/tin7. What does PCB stand for?PCB stands for Printed Circuit Board. It's the foundation of modern electronics, providing both mechanical support and electrical connections for electronic components. PCBs replaced earlier point-to-point wiring and wire-wrap construction methods, enabling the mass production of reliable, compact electronic devices. The "printed" aspect refers to the manufacturing process where circuit patterns are created using photolithographic techniques, similar to how photographs are developed.8. Why are PCBs green?PCBs are traditionally green due to the color of the solder mask - a protective coating applied over the copper traces. The green color became standard for several reasons:Historical - Early solder mask materials naturally produced a green colorVisibility - Green provides good contrast for inspection, making it easier to see traces and identify defectsEye strain - Green is easier on the eyes during prolonged inspection and assembly workCost - Green solder mask is the most common and therefore least expensiveHowever, modern PCBs come in many colors: blue, red, black, white, yellow, purple, and even matte black. Color choice is now often aesthetic, though some colors (like black) can make inspection more difficult. High-end products often use black PCBs for a premium appearance, while purple has become popular in the maker community.9. How do you choose a PCB material?PCB material selection depends on your application requirements:By Application Type:Standard/General Purpose - FR-4 (most common, good for frequencies up to 1-2 GHz)High Frequency/High Speed (>2 GHz) - Rogers RO4003C, RO4350B, or Isola materials with controlled dielectric constantFlexible Circuits - Polyimide (Kapton) or polyesterRigid-Flex - Combination of FR-4 and polyimideLED/High Power - Aluminum or copper core for better heat dissipation (Metal Core PCB - MCPCB)High Temperature - Polyimide or high-Tg FR-4 (Tg > 170°C)Low Cost - FR-1, FR-2, or CEM-1 (phenolic paper-based)Key Material Properties to Consider:Dielectric constant (Dk) - Affects signal speed and impedanceLoss tangent (Df) - Signal loss at high frequenciesGlass transition temperature (Tg) - Maximum operating temperatureThermal conductivity - Heat dissipation capabilityCoefficient of thermal expansion (CTE) - Dimensional stability with temperature changesMoisture absorption - Affects reliability in humid environments10. Why do we use PCB instead of breadboard circuits?While breadboards are excellent for prototyping, PCBs offer significant advantages for final products:Advantages of PCBs over Breadboards:Reliability - Permanent solder connections vs. friction contacts that can loosenDurability - Resistant to vibration, shock, and environmental factorsCompactness - Much smaller footprint, especially with SMT componentsPerformance - Lower parasitic capacitance and inductance, better for high-frequency circuitsCurrent capacity - Wider traces can handle more current safelyReproducibility - Identical boards can be manufactured consistentlyProfessional appearance - Clean, polished look for commercial productsCost-effective at scale - Very cheap per unit in production quantitiesHeat management - Can integrate heat sinks, thermal vias, and metal coresEMI/EMC compliance - Better electromagnetic compatibility through proper grounding and shieldingWhen to Use Each:Breadboard - Initial prototyping, learning, testing concepts, temporary circuitsPCB - Final products, permanent installations, high-frequency circuits, production quantities, professional projectsConclusionCreating your own PCB has never been more accessible. With free or affordable design software, online tutorials, and inexpensive manufacturing services, anyone can bring their electronic projects to life. Whether you're a hobbyist building your first LED blinker or an engineer developing a complex IoT device, the PCB design and manufacturing process follows the same fundamental steps.Start with simple projects to learn the basics, and gradually tackle more complex designs as your skills improve. The maker community is vibrant and supportive, with countless resources, forums, and tutorials available online. Don't be intimidated - your first PCB might not be perfect, but each project will teach you valuable lessons.Remember: every expert PCB designer started exactly where you are now. The key is to start designing, learn from mistakes, and keep improving. Happy designing!

Washington State University physicists have found a way to write an electrical circuit into a crystal, opening up the possibility of transparent, three-dimensional electronics that, like an Etch A Sketch, can be erased and reconfigured. The work, to appear in the on-line journal Scientific Reports, serves as a proof of concept for a phenomenon that WSU researchers first discovered by accident four years ago. At the time, a doctoral student found a 400-fold increase in the electrical conductivity of a crystal simply by leaving it exposed to light. Matt McCluskey, a WSU professor of physics and materials science, has now used a laser to etch a line in the crystal. With electrical contacts at each end of the line, it carried a current. "It opens up a new type of electronics where you can define a circuit optically and then erase it and define a new one," said McCluskey. "It's exciting that it's reconfigurable. It's also transparent. There are certain applications where it would be neat to have a circuit that is on a window or something like that, where it actually is invisible electronics." Ordinarily, a crystal does not conduct electricity. But when the crystal strontium titanate is heated under the right conductions, it is altered so light will make it conductive. The phenomenon, called "persistent photoconductivity," also occurs at room temperature, an improvement over materials that require cooling with liquid nitrogen. "We're still trying to figure out exactly what happens," said McCluskey. He surmises that heat forces strontium atoms to leave the material, creating light-sensitive defects responsible for the persistent photoconductivity. McCluskey's recent work increased the crystal's conductivity 1,000-fold. The phenomenon can last up to a year. "We look at samples that we exposed to light a year ago and they're still conducting," said McCluskey. "It may not retain 100 percent of its conductivity, but it's pretty big." Moreover, the circuit can be by erased by heating it on a hot plate and recast with an optical pen. "It's an Etch A Sketch," said McCluskey. "We've done it a few cycles. Another engineering challenge would be to do that thousands of times." The research was funded by the National Science Foundation. Co-authors on the paper are former students Violet Poole and Slade Jokela. The work is in keeping with WSU's Grand Challenges, a suite of initiatives aimed at addressing large societal problems. It is particularly relevant to the challenge of Smart Systems and its theme of foundational and emergent materials. Ref.KY163-NX1255GBKY163-TSX-3225