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Introduction to Amplifier GainSummary (2026 Update): From 5G RF front-ends to precision IoT sensors—Gain remains the fundamental metric of signal amplification. It quantifies the ratio of output to input for voltage, current, or power, typically expressed in decibels (dB). This guide covers the essential physics, calculation methods, and frequency response analysis required for high-performance circuit design in 2026.In electrical circuits, Gain generally refers to the degree of increase in current, voltage, or power of components, circuits, equipment, or systems. It is specified in decibels (dB), meaning the unit of gain is generally dB, which represents a relative value rather than an absolute unit like Volts or Amps. In short, its general meaning is the magnification factor. In electronics, it is strictly the ratio of the signal output to the signal input of a system. For example, antenna gain is a parameter that represents the radiation concentration of a directional antenna. But what exactly is amplifier gain in the context of modern semiconductors? How do you calculate it using 2026 industry standards? Read the following technical notes for a deep dive.Ⅰ Amplifier Gain Fundamentals1.1 Definition and ContextAmplifier gain is the logarithm of the ratio of output power to input power, used to express the magnitude of power amplification. It also refers to the magnification of voltage or current. The decibel (dB) is the standard unit. The total magnification of an electronic system is often several thousand (e.g., Low Noise Amplifiers) to millions (e.g., Operational Amplifiers). For example, a modern digital radio receiver might need to amplify a signal 20,000 times or more from the antenna to the DSP or speaker. Using linear numbers makes calculations unwieldy. In decibels, we take a logarithm, making the numbers manageable. Crucially, when amplifiers are cascaded (connected in series), the total linear magnification is multiplied, but the total gain in dB is additive, simplifying system design.1.2 Gain Representation in Decibels (dB)Voltage gain Av(dB) = 20log(|Av|)The voltage gain in decibels is 20 times the base-10 logarithm of the voltage ratio (Output Voltage / Input Voltage).Current gain Ai(dB) = 20log(|Ai|)The current gain in decibels is 20 times the base-10 logarithm of the current ratio.Power gain Ap(dB) = 10log(Ap). Note the factor is 10, not 20. Power gain = Output Power / Input Power.Why use decibels? Beyond simple convenience, human perception (like hearing) is logarithmic. A gain of 100,000,000 times (linear) is awkward to document. Converted to dB, it becomes 160dB, which is standard engineering notation. This principle mirrors why computing uses binary or hexadecimal. Engineers can easily convert between linear magnification and decibels depending on the simulation or datasheet requirement.Ⅱ Types of Amplifier Gain2.1 Voltage Gain (Av)Av = Vo / Vi means that voltage gain equals the amplifier's output voltage divided by the input voltage. This is the primary metric for Voltage Amplifiers.🔺 Open Loop Voltage Gain (AVOL)In the absence of negative feedback, the amplification factor of an operational amplifier (Op-Amp) is called Open-Loop Gain. Ideally, this is infinite. In practice, modern precision Op-Amps (like the OPA series replacing legacy chips) feature gains between $10^5$ to $10^7$. Representations include dB (e.g., 106dB) or V/mV. While legacy chips like the μA741C or LM318 had typical values around 200V/mV, 2026-era rail-to-rail amplifiers offer significantly higher linearity. We use the "virtual ground" assumption in calculations because the immense AVOL forces the differential input voltage to near zero.The Ideal Op Amp Characteristics:1) Open loop gain is infinite.2) Input impedance is infinite (no loading effect), and output impedance is 0.3) Bandwidth is infinite (instantaneous response).Video: How To Calculate the Voltage Gain of a Transistor Amplifier🔺 Closed Loop Voltage GainThis refers to the gain of the entire circuit after a negative feedback loop is applied. Feedback stabilizes the gain and widens bandwidth. The formula is: voltage gain = 20log(Vo / Vi).🔺 IF (Intermediate Frequency) Voltage GainThe IF voltage gain (Avm) refers to the maximum voltage gain within the passband—specifically the frequency range where the voltage amplitude remains above 0.707 of the maximum (the -3dB points).2.2 Current Gain (Ai)Ai = Io / Ii defines current gain as the output current divided by the input current. These circuits are known as Current Amplifiers (or Current Mirrors in IC design).2.3 Transimpedance Gain (Rm)Ar = Vo / Ii. Here, the gain represents Output Voltage / Input Current. This topology is called a Transimpedance Amplifier (TIA), critical in 2026 for photodiode sensors and fiber optic receivers.2.4 Transconductance Gain (gm)A = Io / Vi. Transconductance gain is the ratio of Output Current to Input Voltage. These are Transconductance Amplifiers (OTAs), often used as the input stage in modern Op-Amps. Ⅲ Fully Differential Amplifier GainA fully differential amplifier (FDA) is standard in modern high-speed ADC drivers. It features four distinct gain metrics based on Common Mode (CM) and Differential Mode (DM) signals.Adm (Differential Gain): The gain from differential input to differential output. This is the desired signal amplification.Acm (Common Mode Gain): The gain from common-mode input to common-mode output. Ideally, this should be zero to reject noise.Adcm (Mode Conversion - Diff to CM): Gain from differential input to common-mode output.Acdm (Mode Conversion - CM to Diff): Gain from common-mode input to differential output.Design Goal: Maximize Adm while minimizing Acm, Adcm, and Acdm. A high Adm ensures strong signal integrity. A low Acm is crucial; if Acm is non-zero in cascaded stages, common-mode noise (like 60Hz hum or EMI) amplifies, causing "rail saturation." Adcm and Acdm must be minimized to prevent signal distortion and feedback loops that can destabilize the amplifier. In 2026 designs, Common-Mode Rejection Ratio (CMRR) is the key spec that aggregates these parameters. Ⅳ Frequency Response and Gain CalculationCapacitors in an amplifier circuit dictate the frequency response. We analyze gain across three bands: Low Frequency (LF), Intermediate Frequency (IF), and High Frequency (HF).Figure: The Relationship between Gain and Frequency (Bode Plot)1) Intermediate Frequency (IF):Coupling/Bypass Capacitors → Short Circuit.Transistor Parasitic Capacitance → Open Circuit.The gain expression is frequency-independent (flat). This is the nominal gain of the amplifier.2) Low Frequency (LF):Coupling and bypass capacitors are significant here. Their impedance rises as frequency drops, reducing gain. The circuit acts as a High-Pass Filter.3) High Frequency (HF):Internal transistor capacitances (Cpi, Cmu) and stray load capacitances dominate. As frequency rises, these act as short circuits, shunting the signal to ground. The circuit acts as a Low-Pass Filter.Gain Function and Corner Frequencies (S-Domain Analysis)In the complex frequency domain (s-domain), Capacitance = 1/sC and Inductance = sL. The system function A(s) is a ratio of polynomials:Factoring the numerator and denominator reveals the zeros and poles:Key Characteristics:1) For physical stability, the number of zeros (m) must be ≤ poles (n).2) In low-frequency amps, poles are real numbers corresponding to RC time constants.The gain function is split into three bands:Determining the Lower Corner Frequency (fL):At low frequencies, s → ∞ relative to the low poles. The response is governed by coupling capacitors. If one pole is significantly larger (closer to the passband) than the others, it is the Dominant Pole (p1).Approximation using the Dominant Pole concept:......(a)Determining the Upper Corner Frequency (fH):At high frequencies, transistor internal capacitances dominate. Here, we look for the smallest pole (closest to the passband) which acts as the dominant high-frequency pole.The simplified derivation for bandwidth (fBW) typically relies on identifying these dominant poles in the transfer function. Ⅴ FAQ: Common Questions on Amplifier Gain1. How is gain strictly defined in electronics?Gain is the dimensionless ratio of Output / Input. While it has no physical units (Volts/Volts cancel out), it is almost always expressed in Decibels (dB) to handle large magnitudes comfortably. The symbol is "A" (e.g., Av for Voltage Gain).2. What is the difference between Voltage, Current, and Power Gain?Voltage Gain (Av) is Vout/Vin. Current Gain (Ai) is Iout/Iin. Power Gain (Ap) is Pout/Pin. Note that Power Gain is the product of Voltage and Current Gain. In dB: Power Gain uses 10log, while Voltage/Current uses 20log.3. What is the typical current gain (Alpha) of a Common-Base amplifier?In a Common-Base (CB) configuration, the current gain is called Alpha (α). Since the emitter current is the sum of base and collector current (IE = IB + IC), and the output is taken from the collector, the output is always slightly less than the input. Thus, α is always < 1 (typically 0.95 to 0.99).4. How do you calculate the gain of a Differential Amplifier?For a standard differential amp with balanced resistors (R1=R2=R3=R4), it is a Unity Gain device where Vout = V2 - V1. If resistors differ, the gain is determined by the ratio of the feedback resistor to the input resistor.5. What defines an "Ideal" Op-Amp in 2026 theory?An ideal op-amp is a theoretical construct with: Infinite Open Loop Gain, Infinite Input Impedance (draws no current), Zero Output Impedance (drives any load), and Infinite Bandwidth. Real-world components strive to approach these limits using advanced CMOS or BiCMOS processes.6. Why is Op-Amp gain so high?Op-Amps are designed as multi-stage differential amplifiers. They utilize active loads (current mirrors) rather than passive resistors internally, allowing them to achieve massive Open Loop Gains (often >100,000x) to ensure precise performance when closed-loop feedback is applied.7. How do I find the gain of an Inverting Op-Amp?The formula is straightforward: Gain (Av) = - (Rf / Rin). Rf is the feedback resistor, and Rin is the input resistor. The negative sign indicates a 180-degree phase shift.{ "@context": "https://schema.org", "@type": "TechArticle", "headline": "Comprehensive Guide to Amplifier Gain: Formulas, Types, and Calculation (2026 Edition)", "description": "A deep dive into Amplifier Gain in electronics. Learn about Voltage, Current, and Power gain, decibel conversion, frequency response analysis, and modern fully differential amplifier theories.", "datePublished": "2019-01-01", "dateModified": "2026-01-05", "author": { "@type": "Organization", "name": "Kynix Semiconductor" }, "mainEntity": { "@type": "FAQPage", "mainEntity": [ { "@type": "Question", "name": "How is gain strictly defined in electronics?", "acceptedAnswer": { "@type": "Answer", "text": "Gain is the dimensionless ratio of Output divided by Input. While it has no physical units, it is almost always expressed in Decibels (dB). The symbol is usually A." } }, { "@type": "Question", "name": "What is the formula for Voltage Gain in dB?", "acceptedAnswer": { "@type": "Answer", "text": "Voltage Gain in dB is calculated as 20 * log10(Vout / Vin)." } }, { "@type": "Question", "name": "What is the difference between Voltage, Current, and Power Gain?", "acceptedAnswer": { "@type": "Answer", "text": "Voltage Gain (Av) is Vout/Vin. Current Gain (Ai) is Iout/Iin. Power Gain (Ap) is Pout/Pin. In dB conversion, Voltage and Current use 20log, while Power uses 10log." } }, { "@type": "Question", "name": "What is the current gain (Alpha) of a Common-Base amplifier?", "acceptedAnswer": { "@type": "Answer", "text": "In a Common-Base configuration, the current gain (Alpha) is always less than 1 (unity), typically between 0.95 and 0.99." } }, { "@type": "Question", "name": "How do you calculate the gain of an Inverting Op-Amp?", "acceptedAnswer": { "@type": "Answer", "text": "The gain is calculated using the formula: Gain = - (Rf / Rin), where Rf is the feedback resistor and Rin is the input resistor." } } ] }}

Introduction Everyone has heard of FPGA more or less, such as Bitcoin mining, or Microsoft said before that it will use FPGA instead of CPU in the data center. So what exactly is it? Why use it? Compared with CPU, GPU, and ASIC, what are the characteristics of FPGA? FPGA is a chip that can reconfigure circuits and is a hardware reconfigurable architecture. Through programming, users can change its application scenarios at any time, and it can simulate various parallel operations of hardware such as CPU and GPU. By interconnecting with the high-speed interface of the target hardware, the FPGA can complete the low-efficiency part of the target hardware, thereby achieving acceleration at the system level. What Is an FPGA? Catalog Introduction Ⅰ FPGA vs CPU vs GPU vs ASIC Ⅱ Five Advantages of FPGA 2.1 Performance 2.2 Time-to-Market 2.3 Cost 2.4 Stability 2.5 Long-Term Maintenance Ⅲ New Applications of FPGA Ⅳ Development Trend of FPGA Ⅴ FAQ Ⅰ FPGA vs CPU vs GPU vs ASIC The core difference between FPGA and CPU, GPU, ASIC chips, etc. is that the connection and logic layout of the underlying operation unit are not solidified. Users can program the logic unit and switch array through EDA software to configure the function, so as to realize the integration of specific functions.FPGA appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also improves the limited number of original programmable device gate circuits. Compared with ASIC chips, an important feature of FPGA is its programmable characteristics, that is, the user can specify the FPGA to realize a specific digital circuit through the program. Furthermore, FPGA chips are one of the best choices for small batch systems to improve system integration and reliability. Figure 1. FPGA Basic Structure So why is FPGA so fast? This is all because the computer's CPU(central processing unit) and GPU(graphics processing unit) belong to the von Neumann structure, with instruction decoding and execution, and shared memory. FPGAs, on the other hand, are instruction-free and memory-free architectures that make FPGA chips much more energy-efficient than CPUs or even GPUs. Figure 2. Von Neumann Structure In the von Neumann architecture, since the execution unit (such as the CPU core) may execute any instruction, so an instruction memory, a decoder, an operator of various instructions, and branch and jump processing logic are required. Due to the complex control logic of the instruction stream, it is impossible to have too many independent instruction streams. Therefore, the GPU uses SIMD (single instruction, multiple data) to allow multiple execution units to process different data at the same pace, and the CPU also supports SIMD instruction. The function of each logic unit of the FPGA has been determined during reprogramming, and no instructions are required. Figure 3. Computer CPU If the GPU is used for acceleration, in order to fully utilize the GPU computing, the batch size cannot be too small, and the delay will be on the order of milliseconds. Using FPGA to accelerate, only microsecond-level PCle delay is required. Why is FPGA so much lower latency than GPU? This is basically an architectural difference. FPGAs have both pipeline parallelism and data parallelism, while GPUs have almost only data parallelism (with limited pipeline depth).For example, FPGA chips can change the running hardware design on the chip every few seconds, while chips such as CPU and ASIC are already solidified when they leave the factory and cannot be changed. If ASIC, CPU, GPU, etc. are built buildings, and the routes of rooms, corridors, and stairs in the building have been fixed, while the interior of FPGA is similar to the magic staircase in Hogwarts, which can change the route of room to room at any time. In addition, FPGA does not need to compile the instruction system at the software application level like CPU and GPU. To program FPGA, use hardware description language, and directly compile and burn it into a combination of transistor circuits, that is, directly use transistor circuits to implement user algorithms.The biggest feature of FPGA is its flexibility. It can realize any digital circuit you want and can customize various circuits. Reduce the shackles of special chips, truly tailor-made for your own products, you can flexibly change the design during the design process, and have field programmability, so it is especially suitable for applications that require continuous changes in physical operation logic, such as AI algorithm optimization, data center applications, etc. Architecture Throughput（int ops） Delay Flexibility CPU ~1T N/A Very High GPU ~10T ~1ms High FPGA(Stratix V) ~1T ~1us High FPGA(Stratix 10) ~10T ~1us High ASIC ~10T ~1us Low The FPGA is set up by the RAM stored on the chip to reset its working state, so the on-chip RAM needs to be programmed when working. Users can use different programming methods according to different configuration modes, which can be said to be very flexible and convenient. The FPGA has the following configuration modes:🔺Parallel Mode: Parallel PROM, Flash configures FPGA.🔺Master-Slave Mode: One PROM configures multiple FPGAs.🔺Serial Mode: Serial PROM configures FPGA.🔺Peripheral Mode: The FPGA is used as a peripheral of the microprocessor and programmed by the microprocessor. Computational performance compared with CPU: For example, Stratix series FPGAs perform integer multiplication operations, and their performance is equivalent to that of a 20-core CPU, and for floating-point multiplication operations, their performance is equivalent to an 8-core CPU.Computational performance compared with GPU: FPGA performs integer multiplication and floating-point multiplication operations. There is an order of magnitude difference in performance compared to GPU. The computing performance of GPU can be approached by configuring multipliers and floating-point operation components. Figure 4. CPU and GPU Architecture Diagram The core advantage of FPGA for performing computation-intensive tasks: tasks such as search engine sorting and image processing have strict requirements on the return time limit of results, and it is necessary to reduce the delay of computing steps. Under the traditional GPU acceleration scheme, the data packet size is large, and the delay can reach the millisecond level. Under the FPGA acceleration scheme, the PCIe latency can be reduced to the microsecond level. Driven by long-term technology, the data transmission delay between CPU and FPGA can be reduced to less than 100 nanoseconds.The FPGA can build the same number of pipelines (pipeline parallel structure) for the number of data packet steps, and the data packets can be output immediately after being processed by multiple pipelines. The GPU data parallel mode relies on different data units to process different data packets, and the data units need to be input and output consistently. For stream computing tasks, the FPGA pipeline parallel structure has a natural advantage in latency. FPGA is used to process communication-intensive tasks and is not limited by network cards. It outperforms CPU solutions in terms of packet throughput and delay, and has strong delay stability. Therefore, FPGAs have obvious advantages over CPUs when performing large data processing tasks with high repetition rates.By programming the FPGA, the user can change the internal connection structure of the chip at any time to realize any logic function. Especially in industries with immature technical standards or rapid development and change, FPGA can effectively help enterprises reduce investment risks and sunk costs, and is a functional and economical choice. Figure 5. Computer GPU With the evolution of intelligent market demand, highly customized chips (ASIC SoC) have led to a sharp increase in market risks due to the large scale of non-repetitive investment and long R&D cycle. Relatively speaking, FPGA has advantages in the field of parallel computing tasks, and can replace some ASICs in the field of high performance and multi-channel. The demand for multi-channel computing tasks in the field of artificial intelligence (AI) drives the evolution of FPGA technology to the mainstream. Figure 6. ASIC SoC Ⅱ Five Advantages of FPGA 2.1 Performance Taking advantage of hardware parallelism, FPGAs break the sequential execution model and complete more processing tasks per clock cycle, surpassing the computing power of digital signal processors (DSPs). BDTI(Big Data Test Infrastructure), a well-known analysis and benchmarking company, has published benchmarks that show that in some applications, FPGAs can handle many times more processing power per dollar than DSP solutions. Controlling input and output (I/O) at the hardware level provides faster response times and specialized functionality to meet application needs. 2.2 Time-to-Market Despite increasing time-to-market constraints, FPGA technology offers flexibility and the ability to rapidly prototype. Users can test an idea or concept and complete verification in hardware without going through the lengthy manufacturing process of custom ASIC design. This allows users to make incremental modifications and iterate FPGA designs in hours, saving weeks. Commercial off-the-shelf (COTS) hardware provides different types of I/O connected to user-programmable FPGA chips. The increasing popularity of high-level software tools reduces the learning curve and abstraction layers, and often provides useful IP cores (pre-built functions) for advanced control and signal processing. 2.3 Cost The non-recurring engineering (NRE) cost of custom ASIC design far exceeds the cost of FPGA-based hardware solutions. The huge initial investment in ASIC design shows that OEMs need to ship thousands of chips each year, but more end users need custom hardware capabilities that enable the development of tens to hundreds of systems. The nature of programmable chips means that users can save on manufacturing costs as well as long lead times for assembly. System requirements change from time to time, but the cost of changing the FPGA design is negligible compared to ASCI's huge expense. 2.4 Stability Software tools provide the programming environment, and FPGA circuits are the real "hard" implementation of programming. Processor-based systems often contain multiple layers of abstraction that can schedule tasks and share resources among multiple processes. The driver layer controls hardware resources, while the operating system manages memory and processor bandwidth. For any given processor core, only one instruction can be executed at a time, and processor-based systems face the risk of tightly time-bound tasks taking over each other at all times. FPGAs, on the other hand, do not use an operating system, and have true parallel execution and deterministic hardware that focuses on each task, reducing the chance of stability issues. 2.5 Long-Term Maintenance As mentioned above, FPGA chips are field-upgradable without the time and expense involved in redesigning ASICs. For example, digital communication protocols contain specifications that can change over time, and ASIC-based interfaces can create maintenance and forward compatibility difficulties. Reconfigurable FPGA chips can accommodate future modifications. As a product or system matures, users can enhance functionality without spending time redesigning hardware or modifying board layouts.   Ⅲ New Applications of FPGA At present, the FPGAs mainly produced by Xilinx and Altera with the highest market share, which are all based on SRAM technology, and need to be connected to an external memory to save the program when in use. When powered on, the FPGA reads the data in the external memory into the on-chip RAM, and after completing the configuration, it enters the working state. When power off, the FPGA returns to a white chip, and the internal logic disappears. In this way, the FPGA can not only be used repeatedly, but also does not require a special programmer, but only a general EPROM and PROM programmer. So Actel, QuickLogic and other companies also provide FPGAs with anti-fuse technology, which can only be downloaded once. They have the advantages of anti-radiation, high & low temperature resistance, low power consumption and fast speed. They are widely used in military and aerospace fields. FPGA cannot be erased and written repeatedly, which is troublesome and expensive in the early stage of development. Lattice is the inventor of ISP technology, which has certain characteristics in small-scale PLD applications. Early Xilinx products generally did not involve military and aerospace markets, but now a number of products such as Q Pro-R have entered such fields.In the industrial field, FPGA chips are widely used in the industrial field, and are widely used in video processing, image processing, CNC machine tools and other fields to realize signal control and operation acceleration functions. With the development of intelligence and automation technology, the industrial field is gradually shifting from human resources as the core element to intelligent unmanned factories with automation as the core element.Smart electric vehicles will be the mainstream development direction of the automotive industry in the future. At present, the application of FPGA in automotive cameras and sensors is relatively mature. In the artificial intelligence system of automatic/intelligent driving vehicles, the applicability of FPGA will be the most suitable for processing sophisticated ADAS and autonomous driving. Figure 7. FPGA for Auto In the field of automotive electronic system interface and control, FPGA chips are used to control and drive electric vehicle motor control systems, connect various in-vehicle equipment such as driving systems, instrument panels, radar, ultrasonic sensors, etc. control. In the field of video bridging and fusion, FPGA chips can be used to realize functions such as signal bridging of multiple image sensors, 3D surround view video fusion, reversing auxiliary video, and assisted driving video.In the field of communication, the number of 5G base stations has increased, and the FPGA usage of a single base station has increased, driving the increase in FPGA demand. According to estimates, the FPGA consumption of a 5G single base station is expected to increase from 1-3 blocks in the 4G period to 4-5 blocks in the 5G period. Figure 8. RFSoC FPGA Board Target 5G eFPGA technology is superior to traditional FPGA solutions in terms of performance, cost, power consumption, profitability, etc., and can provide flexible solutions for different application scenarios and different market segments. The economic trend of increasing design complexity and falling equipment costs has stimulated the market demand for eFPGA technology.   Ⅳ Development Trend of FPGA First of all, with the commercialization of the new generation of communication technology, the demand for products such as communication base stations, servers, and intelligent terminals will further expand, thereby driving the increase in the market demand for FPGA chips. At the same time, smart cities, smart factories, and consumer electronics pay more attention to the functionality of various smart IoT devices, which will drive the wide application of FPGA chips in smart IoT devices. With the development of the Internet of Vehicles technology, the scale of the use of FPGA chips in the automotive industry will increase day by day to build a more complete Internet of Vehicles and realize smarter autonomous driving functions. Therefore, with the rapid penetration of 5G, the vigorous development of AI and the increasing trend of automotive intelligence, it is expected that the demand for FPGAs in the three fields of communication, AI and automotive electronics will continue to increase in the future, which will also promote The FPGA industry continues to grow.   Ⅴ FAQ 1. What is FPGA and why it is used?The acronym FPGA stands for Field Programmable Gate Array. It is an integrated circuit that can be programmed by a user for a specific use after it has been manufactured. ... These blocks create a physical array of logic gates that can be customized to perform specific computing tasks. 2. Is FPGA faster than GPU?The difference between GPU and FPGA performance is not a static factor, but it does depend on the size of the data set. A study by Sanaullah and Herbordt [7] revealed that FPGA can compute small samples of 3D FFT tens of times faster than GPU. The difference is less clear when the data set gets bigger. 3. Is FPGA faster than CPU?A FPGA can hit the data cell faster and more often than a CPU can do it meaning the FPGA causes more results to occur during an attack. It all goes faster when an FPGA is used. And as a side benefit, no trace of all this is left on the CPU because it's never touched when an FPGA is used. 4. Are FPGAs efficient?Efficiency and Power: FPGAs are well-known for their power efficiency. A research project done by Microsoft on an image classification project showed that Arria 10 FPGA performs almost 10 times better in power consumption. 5. Is FPGA programming hard?FPGA vendors have touted their wares as ideal replacements for DSPs, CPUs, and GPUs – even for all of them in a single device – but they are notoriously difficult for software engineers to program as they are not anything like a conventional processor. 6. What can you do with FPGAs?Uses for FPGAs cover a wide range of areas—from equipment for video and imaging, to circuitry for computer, auto, aerospace, and military applications, in addition to electronics for specialized processing and more. 7. What is the difference between processor and FPGA?Microprocessor vs FPGA: A microprocessor is a simplified CPU or Central Processing Unit. ... An FPGA doesn't have any hardwired logic blocks because that would defeat the field programmable aspect of it. An FPGA is laid out like a net with each junction containing a switch that the user can make or break. 8. What language is used to program FPGA?VerilogTraditionally, FPGAs are programmed using pro-level hardware-description languages such as Verilog or VHDL. 9. How many times can you program an FPGA?There is effectively no limit to the number of times a device can be reconfigured; the configuration is stored in SRAM, which has no write limit. most Fpgas can be passively loaded from a processor, one word at a time. That processor can get the FPGA image from anywhere. 10. What are the advantages of FPGA?FPGA advantagesLong-term availabilityUpdating and adaptation at the customerVery short time-to-marketFast and efficient systemsAcceleration of softwareReal-time applicationsMassively parallel data processing 11. How do you make an FPGA?FPGA design checklistMake sure you have plenty of time to spare.Find a decent computer.If you can afford it, add a big display.Decide which operating system to use.Consider using a virtual machine (VM).Select an FPGA vendor.Pick out a suitable development board.Select an embedded processor to use. 12. What is FPGA for beginners?FPGA stands for Field Programmable Gate Array. As you may already know, FPGA essentially is a huge array of gates that can be programmed and reconfigured any time anywhere. Huge array of gates is an oversimplified description of FPGA. FPGA is indeed much more complex than a simple array of gates. 13. What is FPGA in Verilog?FPGAs are nothing, but reconfigurable logic blocks and interconnects can be programmed by Hardware Description Language like Verilog/ VHDL to perform a specific functionality. 14. Do we need to program the FPGA once powered off?If you have a SRAM-based FPGA, like the Spartan 3, then you have to program it each time it is powered up. The reason for this is that the SRAM which stores the configuration is volatile and loses the programmed configuration after power is switched off. 15. How is FPGA different from microcontroller?One of the main differences between a microcontroller and an FPGA is that an FPGA doesn't have a fixed hardware structure, while a microcontroller does. While FPGAs include fixed logic cells, these, along with the interconnects, can be programmed in parallel by using HDL coding language.

Ⅰ IntroductionA computer  whether it is a laptop  or a desktop has a Motherboard where a small amount of memory known as  CMOS  (complementary metal-oxide-semiconductor) stores the BIOS  settings. Hardware settings, system time, and date are the parts of BIOS  settings. BIOS  protects the data each time the computer  turns off. If  CMOS loses its power the system clock resets.CatalogⅠ IntroductionⅡ CMOS Battery Related VideoⅢ Computer BIOS Ⅳ What is a CMOS Battery ?Ⅴ What is the Lifeline of CMOS Battery?Ⅵ How do I Know My CMOS Battery Failed? Ⅶ How to Replace A CMOS Battery?7.1 Step 1: Remove the Previous CMOS Battery7.2 Step 2：What To Do After Taking Out The Battery？Ⅷ FAQ Ⅱ CMOS Battery Related VideoHow to remove cmos battery in your pc? Cmos reset / hard reset on biosCMOS Battery Video Description:In this video I will teach you how to remove your cmos battery  in your pc whether be in  ATX  or  mATX  or mini ITX motherboard  . Removing the cmos battery  for 5 minutes will give a hard reset on your motherboard  and this will clear unnecessary issues like wrong overclock, no video signal and seeing the "reboot and select proper boot drive" in your display Ⅲ Computer BIOS To comprehend the significance of a CMOS battery  , you must first comprehend what your computer  's BIOS  is.BIOS is pre-programmed into the hardware of every computer,  It is not the same as an operating system. Operating systems  can be installed, uninstalled, and updated long after the computer  has been purchased. BIOS  is something that is built into the computer  during the manufacturing process.BIOS is an abbreviation for "Basic Input/Output System." What exactly does it accomplish? Essentially, it manages your computer  's essential functions.All computer  s operate based on inputs and outputs. Assume you're launching a software application:An input is when your CPU  sends an instruction to your hard disk to retrieve the software program from storage.Your hard disk retrieves the data from the software program and sends it back to your CPU  ; this is output.The program is executed by your CPU,  It sends instructions to your graphics processor, instructing it on what image to create; an input.Your graphics processor then sends instructions to your monitor on how to arrange the pixels on the screen to create the image; this is output.Everything your computer  does can be reduced to an input or an output. The BIOS  is in charge  of managing your computer's exchange of inputs and outputs, mostly when you boot it up. BIOS  instructs your computer on how to boot up the operating system and also controls peripherals (such as the mouse and keyboard). To turn on your laptop  , you press the power button, correct? So, how is your laptop  supposed to process the power button when it is off? That is what the BIOS operated. While your computer is still waking up, it performs basic functions for it. The basic input is to press the power button. The basic output is that your operating system boots up. Next We will look at CMOS battery,  Ⅳ What is a CMOS Battery ?On your motherboard.  the motherboard  battery, also known as the CMOS (Complementary Metal-Oxide Semiconductor), functions as an RTC (Real-Time-Clock). Inside your computer.  the CMOS acts as a battery-powered semiconductor chip that stores important data. This information includes the system time, date, and system hardware settings, which are required for your computer to boot and load properly. All of this data is kept safe by a near-quarter-sized lithium battery located directly on the computer's motherboard, Figure1:CMOS battery Ⅴ What is the Lifeline of CMOS Battery?CMOS is also referred to as CMOS RAM, Non-Volatile RAM (NVRAM), or a real-time clock (RTC). The lifespan of a CMOS battery  is nearly ten years. It will differ depending on the computer's usage and environment. CMOS is used in devices such as static RAM (SRAM), microcontrollers, digital logic circuits, and microprocessors.When the computer is unable to display the correct date and time, the CMOS battery  has failed. The original button does not appear on all motherboard  s. Some of the most basic types of customization features are expansion port speed configuration, boot device order, memory handling, and power control.As we all know from personal experience, batteries do not last forever. Batteries will cease to function after a certain time. This could happen anywhere between two and ten years after the device is manufactured. If your computer is turned on, its battery will last longer than if it is turned off. Unlike other types of batteries, these are not rechargeable, and doing so may result in an explosion. Ⅵ How do I Know My CMOS Battery Failed?The following are the symptoms of CMOS battery  failure:The laptop  is having trouble booting up.The motherboard  emits a constant beeping noise.The date and time have been reset.Peripherals are not responsive or respond incorrectlyHardware drivers have vanishedYou are unable to connect to the internet.When your CMOS battery  dies, your BIOS firmware will shut down and reset to factory setting. Problems with booting up and constant beepingAs previously stated, BIOS is primarily responsible for booting up your  computer ,  Your laptop  may have a difficult time booting up without the battery, or it may not boot up at all. You may also hear a constant beeping noise from the motherboard.  which is another sign of a battery failure.Date and time from a long, long time agoIf your laptop  boots, you may notice that the date and time have been reset. They've most likely reset to a date in the distant past. Even when your computer is turned off, BIOS keeps a real-time clock that keeps track of the date and time. That procedure is maintained by CMOS (which is sometimes referred to as a real-time clock in and of itself). If the date and time have mysteriously reset, it's a good indication that the CMOS battery  has died.Keyboard performance is erratic.It's possible that your peripherals aren't responding; for example, you can't move your cursor or click on any icons, and the laptop  isn't reading any of your keyboard inputs.Alternatively, your peripherals may be thrown out of whack; your cursor may be inaccurate, and your key inputs may result in strange responses from the operating system.Alternatively, your customized keyboard configuration has been reset to the default. Because BIOS is in charge  of managing peripherals at startup, these are all indications of CMOS failure.Drivers vanishIf you've installed any drivers on your computer.  such as those for your home printer, a CMOS failure may cause those drivers to vanish (you'll need to download and reinstall them).There is no internet connection.You may also be unable to connect to the internet if your battery dies. BIOS is in charge  of keeping hardware and network drivers up to date.One thing you should be relieved about is that CMOS failure usually does not result in the loss of any personal files. Nothing in storage has been harmed. Once you've replaced the battery, you'll still have access to all of your photos, videos, and documents. Failure of ttery  Ⅶ How to Replace A CMOS Battery?Ground yourself before you touch your patient. That means making sure that any static electricity (which can be generated in small charge  s between your body and clothing but is weak enough not to hurt you) does not pass through the delicate computer parts, which may seem insignificant but can seriously damage some of the more delicate components inside your case.Important points include placing your computer case on a non-conductive (non-metallic) table or surface before opening it for treatment and standing on bare feet in contact with the floor. 7.1 Step 1: Remove the Previous CMOS BatteryTo do so, open your computer's case and locate the CMOS battery on the  motherboard ,  If you're treating a laptop.  you'll need to open the laptop  's back panel. Because it resembles a large silver coin sitting on your motherboard  , the CMOS battery is easy to locate. Figure2:motherboard The battery in most systems and laptops is held in place by a small clip next to it. Simply slide the battery out from under the clip like a big round SIM card, and you'll have the troublesome little silver coin in your hand.Also, under no circumstances should the clip be bent.As a result, it will be unable to hold the new battery in place. You're treating your computer.  and as the saying goes, "first not harm."Figure3:new battery And there is one more thing;In some laptops, the CMOS battery may be covered with non-conductive protection and attached to two wires that are connected to the laptop's motherboard  via a connector similar to this:Figure4: laptop's motherboardAnd, you know, it's also possible that you can't find the CMOS battery on your laptop's back panel;Because some manufacturers do not allow battery replacements, and if you are still insistent on removing the battery;In any case, you can look online for a 'how to disassemble your laptop' tutorial video.Like on the YouTube;And this will help you understand how to disassemble your laptop because the CMOS battery may be attached to the other side of your laptop's motherboard, Here's a picture of the laptop without a CMOS battery in the back panel:Figure5: back panel So, whatever battery type your computer is using, simply disconnect or remove it.Even if the CMOS Battery is soldered to the motherboard  in the following manner:Figure6:Battery is soldered 7.2 Step 2：What To Do After Taking Out The Battery？You have to now purchase the same CMOS battery for your laptop or computer that you recently removed from your laptop or computer, So, you'll need to go to a computer store or order the battery online. Whatever you do, make certain that you purchase the same type of battery. Ⅷ FAQ1. How do I get the CMOS out of the motherboard without damaging it?Use a flat head screwdriver, push the metal tab back away from the battery.  It should not take much force, and the battery will just pop out.2. Is the CMOS battery the same battery found in Automotive Key Fobs?Excellent question, YES!  The CR2032 can be found in many devices from calculators, wrist watches, medical devices, toys, and many more.3. Can a motherboard run without a battery?Technically, YES.  Removing the CMOS battery will allow your computer to run however, you will lose the date and time settings, the computer will boot with default BIOS settings or you will have to choose the drive that the OS is installed every time you start your computer.4. Will removing the motherboard battery reset BIOS?This is an excellent question I get asked alot.  The short answer is YES.  If you remove the battery, wait approximately 5 minutes and then reconnect the battery.5. Can a CMOS battery cause a black screen?A faulty battery removes all of your boot settings.  It is very possible to see nothing but a black screen when booting up a computer with a dead CMOS.  For example if you have a secondary video adapter that your monitor is plugged into and your BIOS has reset to default settings, your onboard video would be the new display and not your primary video adapter.

Introduction Latching relay is a new type of relay and also an automatic switch. Like other electromagnetic relays, it turns on and off the circuit automatically. The difference is that the normally closed or normally open state of it is completely dependent on the action of permanent magnets, and the switching state of it is triggered by a pulse electric signal of a certain width. It has the characteristics of power saving, stable performance, small size, large carrying capacity, and superior performance than general relays. Latching Relay Basics in 2 Minutes Catalog Introduction Ⅰ Working Principle 1.1 Action Principle 1.2 Action Process Ⅱ Main Functions and Advantages 2.1 Average View 2.2 Function Lists 2.3 Application Area Lists 2.4 Latching Relay Advantages Ⅲ Tech Parameters Ⅳ Latching Relay Test 4.1 Measuring Contact Resistance 4.2 Measuring Coil Resistance 4.3 Set Voltage and Current 4.4 Reset Voltage and Current Ⅴ Relay Selection 5.1 The Necessary Conditions 5.2 Relevant Information Search 5.3 Installation Layout Consideration Ⅵ FAQ Ⅰ Working Principle 1.1 Action Principle The on and off state of the latching relay is usually held by the magnetic force generated by the permanent magnet. When the contacts of the relay need to be opened or closed, only the positive (reverse) DC pulse voltage is needed to excite the coil, and the relay completes the state transition between opening and closing in an instant. Usually when the contact is in the holding state, the coil does not need to continue to be energized, and the state of the relay can be maintained unchanged only by the permanent magnet force.   1.2 Action Process When the contacts of the relay need to be set, it is only necessary to excite the coil J2 with a positive DC pulse voltage. The magnetic poles generated by the coil J2 after excitation interact with the magnetic poles of the permanent magnet. As we all known, the same polarities repel each other, but the opposite polarities attract each other. The state transition from reset to set is completed in an instant. The following schematic diagrams demonstrates the specific state transition process. The process of the latching relay changing from the set state to the reset state, which are the same. Figure 1. Reset Latching Relay Figure 2. Constant-Current Pulse Monment Figure 3. Constant-Current Pulse Monment Figure 4. Latching Relay Reset   Ⅱ Main Functions and Advantages 2.1 Average View Latching relay is an automatic switching element with isolation function. It is widely used in remote control, telemetry, communication, automatic control, mechatronics and power electronic equipment. It is one of the most important control elements in electricity.Magnetic latching relays generally have an induction mechanism (input part) that can reflect certain input variables (such as current, voltage, power, impedance, frequency, temperature, pressure, speed, light, etc.). It has the ability to turn on/off the controlled circuit. In addition, between the input part and output part of the relay, there is an intermediate mechanism (drive part) for coupling and isolating the input, functional processing and driving the output part. 2.2 Function Lists The latching relay has the following functions:1) ExpansionFor example, when the control signal of a multi-contact relay reaches a certain value, multiple circuits can be switched, disconnected, and connected at the same time according to different forms of contact groups.2) AmplificationFor example, magnetic latching relays can control a large-power circuit with a very small control quantity.3) IntegrationFor example, when a plurality of control signals are input to a multi-winding relay in a prescribed form, they will be compared and integrated to achieve a predetermined control effect.4) Automation, remote control and monitoringFor example, on the automatic device and other electrical appliances, magnetic latching relays can form a program control circuit to realize automatic operation. 2.3 Application Area Lists 1) Smart meters: IC card meters, prepaid meters, single-phase meters, three-phase meters.2) Reactive power compensation: synchronous switch, composite switch, smart capacitor.3) Intelligent control: smart home, solar street light control, automation equipment, etc. 2.4 Latching Relay Advantages 1) They only need pulse excitation, and can work with single and double coils.2) Small size, easy installation.3) Low power consumption and strong load capacity.4) Safe and reliable, long service life. Figure 5. General Relay Structure Ⅲ Tech Parameters 1) Rated VoltageIt refers to the voltage required by the coil when the relay is working normally. Depending on the model of the relay, it can be AC voltage or DC voltage.2) DC ResistanceIt refers to the DC resistance of the relay coil, which can be measured by a multimeter.3) Pull-in CurrentIt refers to the minimum current that the relay can produce the pull-in action. In normal use, the given current must be slightly larger than the pull-in current, so that the relay can work stably. As for the working voltage applied to the coil, generally do not exceed 1.5 times the rated working voltage, otherwise it will generate a larger current and burn the coil.4) Release CurrentIt refers to the maximum current that the relay generates to release the action. When the current in the pull-in state of the relay is reduced to a certain level, it will return to the unpowered release state. The current at this time is much smaller than the pull-in current.5) Switch Voltage and CurrentThis refers to the voltage and current that the relay allows to load. It determines the magnitude of the voltage and current that the relay can control, and you cannot be exceeded this value during use, otherwise it is easy to damage the contacts of the relay.6) Coil Resistance RThe resistance produced by winding a T circle with an enameled wire with a diameter of Φ: R=￡*(T/Φ).7) TemperatureThe higher the temperature, the greater the resistance, and the lower the resistance, the smaller the resistance. Generally speaking, the coil resistance refers to the coil resistance at 20°C. When the temperature is higher or lower than 20℃, there is a calculation formula: Rt=R20[1+(T℃-20℃)×0.004].8) Contact Resistance CRIt is the resistance between the contacts of the relay. And it is the sum of the shrinkage resistance Re and the surface film resistance Rf: Rk=Re+Rf.Note:🔺The factors that form shrinkage resistance Re:♦️The size of the contact pressure determines the size of the shrink resistance. The relationship between the two is inversely proportional, the greater the contact pressure, the smaller the shrinkage resistance.🔺The factors that form the surface film resistance Rf:♦️Dust in the air.♦️Harmful gases in the air: H2S, SO2, etc.♦️Organic vapor in the air: plastic, glue and rosin.♦️Oil stains on the contact surface during the production process.9) Pull-in VoltageThe minimum voltage required to close the relay contacts.10) Release voltageThe minimum voltage required to open the relay contacts.11) Insulation ResistanceThe resistance value that appears when measured with a specified DC voltage between conductive parts that are insulated from each other.12) Medium Withstand VoltageAlso known as dielectric degree, it refers to the maximum voltage that can withstand between two conductive parts without breakdown.13) Reversing RetentionThe minimum force applied on the armature assembly handle to open or close the contacts.14) Contact PressureThe interaction force generated between the moving and static contacts is equal to the contact pressure equal to the reaction force generated by the over-travel of the reed head. Figure 6. Latching Relay Product Ⅳ Latching Relay Test 4.1 Measuring Contact Resistance Use the resistance profile of the universal meter to measure the resistance of the normally closed contact and the moving point, which should be 0. The contact resistance can be measured in a more accurate way within 100 milliohms, while the resistances of the normally-open contact and the moving point should infinite. From this, it can be distinguished which is a normally-closed contact or a normally-open contact.   4.2 Measuring Coil Resistance The resistance value of the relay coil can be measured with the universal meter R×10Ω, so as to judge whether there is an open circuit phenomenon in the coil.   4.3 Set Voltage and Current Get an adjustable regulated power supply and an ammeter, input the set voltage to the relay, and insert an ammeter in the power supply loop for monitoring. Slowly increase the power supply voltage, and when you hear the sound of the relay picking up, write down the set voltage and set current. In order to be accurate, you can try several times. Pay attention to, the setting current should be the average value, and the setting voltage should be the maximum value.   4.4 Reset Voltage and Current Repeat the above operation. But there is a little difference that the reset current is the average value, and the reset voltage is the maximum value.   Ⅴ Relay Selection 5.1 The Necessary Conditions ① The power supply voltage of the control circuit, the maximum current that can be provided.② The voltage and current in the controlled circuit.③ How many sets and types of contacts are needed for the controlled circuit. When selecting a relay, the power supply voltage of the general control circuit can be used as the basis for selection. The control circuit should be able to provide enough working current to the relay, otherwise the relay will be unstable when it is closed.   5.2 Relevant Information Search After consulting the relevant information to determine the conditions of use, you can search for the relevant information to find out the model and specification number of the required relay. If you already have a relay on hand, you can check whether it can be used based on the data. Finally, consider whether the size is appropriate.   5.3 Installation Layout Consideration If it is used for general electrical appliances, in addition to considering the volume of the case, it is necessary to consider the installation layout of the circuit board. For small electrical appliances, such as toys and remote control devices, ultra-small relay products should be used.   Ⅵ FAQ 1. What is magnetic latching?The design of a Magnetic Latching Relay is such that when a short pulse of electrical energy is applied to the solenoid coil, sufficient magnetic force is generated to over-come the force of the relay' return mechanism. 2. How does a latching relay work?One latching type has two opposing coils with an over-center spring or permanent magnet hold the contacts in position after the coil is de-energized. A pulse to one coil turns the relay on and a pulse to the opposite coil turns the relay off. 3. Where is latching relay used?This type of relay is most suitable in applications like ON/OFF devices from multiple places with push-button or momentary switch. For example, it is used in a lighting circuit or conveyer to control from different locations. 4. What is a magnetic latching relay used for?A magnetic latching relay is a device in which the solenoid principle is applied to open and close light-current electrical circuits. The same device applied in heavy-current circuits is called a contactor, or circuit breaker. 5. How does a latching relay reset?Resetting is very simple. The coil circuit needs to be opened and shortened to the coils ground potential. The capacitor will be discharged through the coil and drives a current pulse with opposite polarity through the coil.

Introduction Radio Frequency Identification (RFID) is a type of automatic identification technology that uses radio frequency to carry out wireless non-contact two-way data communication, with recording media (electronic tags or radio frequency cards) to read and write. The purpose is identifying the target and making data exchange. This is an extremely complex system, so it involves many parameters. Next, we will introduce several important parameters in detail. What is RFID? How RFID works? Catalog Introduction Ⅰ RFID Parameters Explained 1.1 Rx Sensitivity 1.2 SNR (Signal-to-Noise Ratio) 1.3 Tx Power 1.4 ACLR/ACPR 1.5 Modulation Spectrum/Switching Spectrum 1.6 SEM (Spectrum Emission Mask) 1.7 EVM (Error Vector Magnitude) 1.8 Interference Indicators 1.9 Dynamic Range, Temperature Compensation and Power Control Ⅱ FAQ Ⅰ RFID Parameters Explained Radio frequency identification involves many settings, that is, parameter selections. What are they? Here gives you the detailed descriptions as following mentioned. 1.1 Rx Sensitivity Receiving sensitivity is one of the most basic concepts, characterizes the lowest signal strength that the receiver can recognize without exceeding a certain bit error rate (BER), which is a general term that follows the definition of the circuit switched (CS) era. In most cases, BER or  Packet Error Rate (PER) will be used to examine the sensitivity. In the Long Term Evolution (LTE) era,  use throughput to define simply. LTE does not have a circuit-switched voice channel, but this is also a real evolution. Because for the first time we no longer use "standardization" such as 12.2kbps RMC (voice coding at 12.2kbps) to measure sensitivity, but the throughput that users can really feel.   1.2 SNR (Signal-to-Noise Ratio) When talking about sensitivity, we often refer to SNR (signal-to-noise ratio), we generally talk about the demodulation SNR of the receiver. We define it as the ability of the demodulator to not exceed a certain bit error rate, that is, SNR threshold for demodulation.So where do S and N come from? S means Signal, or useful signal; N means Noise. The useful signal is generally emitted by the communication system transmitter, and the source of noise is very wide. The most typical one is the famous -174dBm/Hz (natural noise). It is a quantity that has nothing to do with the type of communication system. In a sense, it is actually a noise power density related to temperature. In addition, how much bandwidth do we receive determine the noise, that is, the final noise power is integrated on the bandwidth by the noise power density. 1.3 Tx Power The importance of the transmission power is that the signal from the transmitter needs to pass through the fading of space to reach the receiver. So the higher the transmission power means the longer the communication distance.So should we consider SNR for our transmitted signal? For example, if the SNR of our transmitted signal is very poor, do we receive the same bad?This involves the concept just mentioned, the natural noise we assume that spatial fading has the same effect on both signal and noise (in fact, it is not, the signal can resist fading through coding but noise not) and it acts like an attenuator. For example, we assume spatial fading is -200dB, the transmitted signal bandwidth is 1Hz, the power is 50dBm, and the SNR is 50dB, then what is the SNR received by the receiver?The power of the signal received by the receiver is 50-200=-150Bm (bandwidth 1Hz), and the noise of the transmitter 50-50=0dBm through spatial fading, and the power reaching the receiver is 0-200=-200dBm (bandwidth 1Hz)? At this time, this part of the noise has already been "submerged" under the natural noise -174dBm/Hz. At this time, we only need to consider the "basic component" of -174dBm/Hz to calculate the noise to the receiver. Actually, this is applicable in most cases of communication systems.   1.4 ACLR/ACPR These parameters are explained together because they actually represent part of the "transmitter noise", but these noises are not in the transmitting channel, but the part that the transmitter leaks into the adjacent channels, which can be collectively referred to as "Leakage in the adjacent channel".ACLR and ACPR (actually one thing, but one is called in the terminal test, the other is called in the base station test), both are named after "Adjacent Channel". They both describe the machine pair interference from other equipment. And their power calculation of the interference signal is also based on a channel bandwidth. This measurement method considers the signal leaked by the transmitter and the interference to the equipment receiver of the same or similar standard-the interference signal falls into the receiver band with the same frequency and the same bandwidth. That is, form the same frequency interference to the signal received by the receiver.In LTE, the ACLR test has two settings: EUTRA and UTRA. The former describes the interference among the LTE systems, and the latter considers the interference of the LTE system to the UMTS system. So we can see that the measurement bandwidth of EUTRAACLR is the occupied bandwidth of LTE RB, and the measurement bandwidth of UTRA ACLR is the occupied bandwidth of UMTS signals (FDD system 3.84MHz, TDD system 1.28MHz). In other words, ACLR/ACPR describes a kind of "peer-to-peer" interference: the leakage of the transmitted signal interferes with the same or similar communication system.This definition is significant. For example, in the actual network, there are often signal leakage from neighboring cells from other or in the same region. In other words, the adjacent channel leakage of the system itself is typical for neighboring cells. Therefore, the process of network planning and optimization is actually the process of capacity maximization and interference minimization. In addition, from the other side of the system, the mobile phones of users in crowded people may also become a source of mutual interference.Similarly, in the evolution of communication systems, the goal has always been to "smooth transition", that is, to upgrade and transform existing networks into next-generation networks. Therefore, the coexistence of two or even three generations of systems should consider the interference between different systems. So the introduction of UTRA in LTE is to consider the radio frequency interference to the previous generation system UMTS.   1.5 Modulation Spectrum/Switching Spectrum In the GSM system, Modulation Spectrum and Switching Spectrum also play a similar role to adjacent channel leakage. The difference is that their measurement bandwidth is not the occupied bandwidth of the GSM signal. From a definition point of view, it can be considered that the modulation spectrum is a measure of the interference between synchronous systems, and the switching spectrum is a measure of the interference between asynchronous systems. In fact, if the signal is not gating, the switching spectrum will definitely cover the modulation spectrum.This involves another concept: in the GSM system, the cells are not synchronized, although it uses TDMA. In contrast, TD-SCDMA and later TD-LTE, the cells are synchronized.Because the cells are not synchronized, the power leakage of the rising edge/falling edge of the A cell may fall to the payload part of the B cell, so we use the handover spectrum to measure the interference of the transmitter to the adjacent channel in this state. And in the entire 577us GSM timeslot, the proportion of rising edge/falling edge is very small after all. What’s more, most of the time, the payload of two adjacent cells will overlap in time. In this case, the interference of the transmitter to the adjacent channel can be evaluated by referring to the modulation spectrum. Figure 1. RFID Chip 1.6 SEM (Spectrum Emission Mask) SEM is an in-band indicator, which is distinguished from spurious emission. The latter includes SEM, but the focus is on the spectrum leakage outside the working frequency band of the transmitter. In addition, its introduction is more based on the perspective of EMC (Electromagnetic Compatibility).SEM provides a spectrum template. When measuring the spectrum leakage in the transmitter band, see if there are any points that exceed the template limit. It can be said that it is related to ACLR, but it is not the same. ACLR considers the average power leaked into the adjacent channel, so it uses the channel bandwidth as the measurement bandwidth, and it reflects the "critical noise point" of the transmitter in the adjacent channel. Where SEM reflects the capture of over-standard points in adjacent frequency bands with a smaller measurement bandwidth (usually 100kHz to 1MHz), which reflects the noise-based spurious emission.If you scan the SEM with a spectrum analyzer, you can see that the spurious points on the adjacent channel will generally be larger than the ACLR average. Therefore, if the ACLR indicator itself has no margin, the SEM will easily exceed it. On the other hand, if the SEM exceeds the ACLR, it does not necessarily mean bad. For example, a common phenomenon is that there is LO spurious or a certain clock and LO modulation component (often very narrow bandwidth, similar to dot frequency) in the transmitter link, although ACLR is good, the SEM may exceed the standard.   1.7 EVM (Error Vector Magnitude) EVM is a vector, which means it has amplitude and angle. It measures the error between the actual signal and the ideal signal. This measurement can effectively express the "quality" of the transmitted signal. That is, the farther the point distance of the actual signal to the ideal signal, the greater the error and the greater the modulus of the EVM.Why is the SNR of the transmitted signal not so important? There are two reasons: the first is that it is often much higher than the SNR required for demodulation of the receiver. The second is the condition, that is, the worst case. The transmitter noise has already been submerged under the natural noise after a large spatial fading, and the useful signal is also attenuated to near the demodulation threshold of the receiver.But the "intrinsic SNR" of the transmitter needs to be considered in some cases, such as short-range wireless communication. Even without considering the spatial fading, demodulation of such high-order quadrature modulated signals alone already requires a high SNR. The worse the EVM, the worse the SNR and the higher the difficulty of demodulation. Engineers working on 802.11 systems often use EVM to measure Tx linearity. While engineers working on 3GPP systems, they like to use ACLR/ACPR/Spectrum to measure it.From the origin, 3GPP is the evolutionary path of cellular communication, and from the very beginning it has to pay attention to adjacent channel and alternative channel interference. In other words, interference is the number one obstacle that affects cellular communication rates. Therefore, 3GPP always aims at "minimizing interference" during its evolution, such as frequency hopping in the GSM era, spread spectrum in the UMTS era, and the RB concept in LTE era.The 802.11 system is an evolution of fixed wireless access. It follows the spirit of the TCP/IP protocol and aims at "service first". In 802.11, there use often time division or frequency hopping methods to achieve multi-user coexistence. The network layout is more flexible, and the channel width is also flexible and variable. In general, it is not sensitive to interference (or rather high tolerance).In layman's terms, the origin of cellular communication is to make phone calls, and users who cannot get through the phone will go to the telecommunications; while the origin of 802.11 is the local area network, you just wait at first when the network is not good.So this determines that the 3GPP series must take ACLR/ACPR and other "spectrum regeneration" performance as indicators, while the 802.11 series can adapt to the network environment at the expense of speed.Specifically, "Adapt to the network environment at the expense of speed" means that in the 802.11 series, different modulation orders are used to cope with the propagation conditions. When the receiver finds a signal difference, it immediately informs the opposite transmitter to reduce the modulation order. As mentioned earlier, SNR and EVM in an 802.11 system are highly correlated. To a large extent, a reduction in EVM can improve SNR. In this way, we have two ways to improve the receiving performance: one is to reduce the modulation order, thereby reducing the demodulation threshold; the other is to reduce the transmitter EVM, so that the signal SNR is improved.Because EVM is closely related to the demodulation effect of the receiver, EVM is used to measure the performance of the transmitter in the 802.11 system (similarly, in 3GPP, ACPR/ACLR is the index that mainly affects the network performance). In addition, the deterioration of EVM is mainly caused by non-linearity (for example, AM-AM distortion of PA), so EVM is usually used as a sign to measure the linear performance of the transmitter. Figure 2. RFID 1.7.1 Relations of EVM to ACPR / ACLR It is difficult to define the quantitative relationship between EVM and ACPR/ACLR. From the non-linearity of the amplifier, EVM and ACPR/ACLR should be positively correlated. That is, the AM-AM and AM-PM distortion of the amplifier will amplify the EVM, and also the ACPR/ACLR.However, EVM and ACPR/ACLR are not always positively correlated. For example, Clipping is commonly used in digital IF. It is to reduce the peak-to-average ratio (PAR) of the transmitted signal. The reduction of peak power can help reduce the ACPR/ACLR after passing through the PA. However, clipping will also damage the EVM. Because whether it is clipping (windowing) or using a filter, they all cause damage to the signal waveform, affecting the EVM. 1.7.2 Source Flow of PAR PAR (Peak-to-Average Ratio) is usually represented by a statistical function such as CCDF, and its curve represents the power (amplitude) value of the signal and its corresponding probability of occurrence. For example, if the average power of a certain signal is 10dBm, the statistical probability that it has a power exceeding 15dBm is 0.01%, and we can consider its PAR is 5dB.PAR is an important factor affecting transmitter spectrum regeneration (such as ACLP/ACPR/Modulation Spectrum) in modern communication systems. The peak power will push the amplifier into the nonlinear region and produce distortion. And the higher the peak power, the stronger the nonlinearity.In the GSM era, because of the constant envelope characteristic of GMSK modulation, PAR is 0. When designing GSM power amplifiers, we often push it to P1dB to get the maximum efficiency. After the introduction of EDGE, 8PSK modulation is no longer a constant envelope, so we tend to push the average output power of the amplifier to about 3dB below P1dB, because the PAR of the 8PSK signal is 3.21dB.In the UMTS era, whether WCDMA or CDMA, the PAR is much larger than that of EDGE. The reason is the correlation of the signals in the code division multiple access system. In other words,  when the signals of multiple code channels are superimposed in the time domain, the same phase may occur, and the power will show a peak at this time.The PNR of LTE is derived from the burstiness of the RB. OFDM modulation is based on the principle of dividing multi-user/multi-service data into blocks in both the time domain and the frequency domain, so that high power may appear in a certain "time block". LTE uplink transmission uses SC-FDMA. First, DFT extends the time domain signal to the frequency domain, which is equivalent to "smoothing" the burstiness in the time domain, thereby reducing PAR. Figure 3. RFID Applications 1.8 Interference Indicators The "interference index" here refers to the sensitivity test under various applied interferences in addition to the static sensitivity of the receiver. In fact, it is very interesting to study the origin of these test items.Our common interference indicators include Blocking, Desense, Channel Selectivity, etc. 1.8.1 Blocking Blocking is actually a very old RF indicator, as early as the invention of radar. The principle is to pour a large signal into the receiver (usually the first LNA that suffers the most), making the amplifier enter the nonlinear region or even saturate. At this time, on the one hand, the amplifier gain suddenly becomes smaller, and on the other hand, extremely strong nonlinearity occurs, so the function of amplifying useful signals cannot work normally.Another possible Blocking is actually done through the receiver's AGC. Large signals enter the receiver link, and the receiver AGC will reduce the gain to ensure dynamic range, but the useful signal level entering the receiver is very low. At this time, the gain is insufficient, and the amplitude of the useful signal entering the demodulator is insufficient.Blocking indicators are divided into in-band and out-of-band, mainly because the RF front-end generally has a band filter, which has an inhibitory effect on out-of-band blocking. However, the blocking signal is generally point frequency without modulation. In fact, point-frequency signals without modulation at all are rare in practice. In engineering, it is approximately point-frequency to replace various narrow-band interference signals.For solving Blocking, the key is RF. In other words, it is to expand the dynamic range of receiver. For out-of-band blocking, the rejection of the filter is also very important. 1.8.2 AM Suppression AM Suppression is a unique indicator of the GSM system. From the description point of view, the interference signal is a TDMA signal similar to the GSM signal, synchronized with the useful signal and has delay.This scenario simulates the signal of the neighboring cell in the GSM system. From the point of view that the frequency offset of the interference signal is greater than 6MHz (GSM bandwidth is 200kHz), this is a very typical neighboring cell signal configuration. So we can think that AM suppression is a reflection of the receiver's interference tolerance to neighboring cells in the actual work of the GSM system.Adjacent (Alternative) Channel Suppression (Selectivity)Here we collectively refer to it as "adjacent channel suppression". In the cellular system, in addition to the same-frequency cells, we must also consider adjacent-frequency cells in our networking. The reason can be found in the transmitter index ACLR/ACPR/Modulation Spectrum that we discussed before. Because of the transmitter's spectrum regeneration, there will be strong signals falling into adjacent frequencies (generally, the farther the frequency offset, the lower the level, so the adjacent channel is generally the most affected), and this kind of spectrum regeneration is actually related to the transmitted signal. That is, receivers of the same standard are likely to mistake this part of the regenerated spectrum as a useful signal for demodulation.For example, if two neighboring cells A and B happen to be neighboring frequency cells (such networking methods are generally avoided, here is just a assumption), when a terminal registered in cell A swims to the campus junction of two, but the signal strength of the two cells has not reached the handover threshold, the terminal still maintains cell connection with A, and the ACPR of the B cell base station transmitter is higher. So the terminal’s receiving frequency band has a higher ACPR component of B cell, which overlaps with the useful signal of cell A in frequency. Because the terminal is far away from the base station of cell A at this time, the received signal is weak. At this time, when the ACPR component of cell B enters the terminal receiver, it causes co-channel interference to the original useful signal.If we pay attention to the definition of the frequency offset of the adjacent channel selectivity, we will find that there is a difference between Adjacent and Alternative, which corresponds to the first and second adjacent channels of ACLR/ACPR. It can be seen that the "transmitter spectrum leakage (regeneration)" in the communication protocol and the "receiver adjacent channel selectivity" are actually defined in pairs. 1.8.3 Co-Channel Suppression (Selectivity) Co-frequency interference generally refers to the interference pattern between two cells.According to the networking principles we described earlier, the distance between two cells with the same frequency should be as far as possible. In addition, even if they are farther away, there will be signals leaking to each other, but the difference is in intensity. For the terminal, the signals of the two campuses can be regarded as "correct and useful signals" (of course, there is a set of access specifications on the protocol layer to prevent such false access). Frequency strength of both depends on its co-frequency selectivity. 1.8.4 Summery Blocking is big signal interferes with small signal, but the AM Suppression is small signal interferes with large signal.Single-tone Desense is a unique indicator of the CDMA system. It has a feature: the single-tone is an in-band signal and is very close to the useful signal. In this way, it is possible to generate two kinds of signals falling into the receiving frequency domain: First is due to near-end phase noise of the LO, the baseband signal formed by the mixing of the LO and the useful signal, and the signal formed by the mixing of the LO phase noise and the interference signal. Both will fall within the range of the receiver baseband filter, the former is a useful signal and the latter is interference. Second is due to the nonlinearity in the receiver system. The useful signal (with a certain bandwidth, such as 1.2288MHz CDMA signal) may produce intermodulation with the interference signal on the nonlinear device, falling in the receiving frequency domain and becoming interference.The origin of single-tone desense is that the CDMA system uses the same frequency band as the original analog communication system AMPS, and the two networks coexisted for a long time. So the CDMA system must consider the AMPS system's interference to itself.The explanation of Blocking in theory: the large signal entering the receiver causes the amplifier to enter the nonlinear region, and the actual gain becomes smaller (for useful signals).But it is difficult to explain two scenarios:Scenario 1: The pre-stage LNA has a linear gain of 18dB. When a large signal is injected to make it reach P1dB, the gain is 17dB. If no other influence is introduced (the default LNA NF, etc. have not changed), then the noise figure of the entire system is actually very limited. It is nothing more than the fact that the denominator of the latter-stage NF becomes a little smaller when it is included in the total NF, which has little effect on the sensitivity of the entire system.Scenario 2: The IIP3 of the previous LNA is very high, so it is not affected. The second level gain block is affected (the interference signal makes it reach near P1dB). In this case, the impact of the entire system NF is even smaller.Here is a point of view: the influence of Blocking may be divided into two parts. One part is that the gain mentioned in the textbook is compressed, and the other part is actually that after the amplifier enters the nonlinear region, the useful signal is distorted in this region. This kind of distortion may include two parts, one part is the spectrum regeneration (harmonic component) of the useful signal caused by pure amplifier nonlinearity, and the other part is the Cross Modulation of the large signal modulating the small signal.From this we also put forward another idea: if we want to simplify the Blocking test (3GPP requires frequency sweeping, which is very time-consuming), we may be able to select certain frequency points, which have the greatest impact on useful signal distortion when the Blocking signal appears.From an intuitive point of view, these frequency points may have: f0/N and f0*N (f0 is the useful signal frequency, and N is a natural number). The former is because the N-th harmonic component generated by the large signal in the nonlinear region is just superimposed on the useful signal frequency f0 to form direct interference, and the latter is superimposed on the N-th harmonic of the useful signal f0 and affects the output signal f0.According to Pascal's law, the waveform of the time domain signal is actually the sum of the domain fundamental frequency signal and each harmonic. When the power of the Nth harmonic in the frequency domain changes, the corresponding in the domain is the envelope change of the time domain signal (have distortion). Figure 4. RFID Readers   1.9 Dynamic Range, Temperature Compensation and Power Control These three indicators will only be shown when certain extreme tests are performed, but they themselves represent the most significant part of RF design. 1.9.1 Dynamic Range of the Transmitter The dynamic range of the transmitter characterizes the maximum and minimum transmission power without damaging other transmission indicators. This concept is very broad. If you look at the main effects, you can understand that the linearity of the transmitter is not compromised at the maximum transmission power, and the SNR of output signal is maintained at the minimum transmission power.Under the maximum transmit power, the output is often close to the nonlinear region of active devices at all levels (especially the final amplifier), and the nonlinearity that often occurs is spectral leakage and regeneration (ACLR/ACPR/SEM), modulation error (PhaseError/EVM). The most susceptible at this time is basically the linearity of the transmitter.Under the minimum transmit power, the useful signal output by the transmitter is close to the natural noise of the transmitter, and may even be submerged in the transmitter noise. At this time, what needs to be guaranteed is the SNR of the output signal. In other words, the lower the transmitter noise at the minimum transmit power, the better. 1.9.2 Dynamic Range of the Receiver The dynamic range of the receiver is actually related to the two indicators we talked about before, the first is the reference sensitivity, and the second is the receiver IIP3 (interference indicator).The reference sensitivity actually characterizes the minimum signal strength that the receiver can recognize. We mainly talk about the maximum receiving level of the receiver.It refers to the maximum signal that the receiver can receive without distortion. This distortion may occur at any stage of the receiver, from the previous LNA to the receiver ADC. For the front-level LNA, the only thing we can do is to increase IIP3 as much as possible so that it can withstand higher input power. For the subsequent step-by-step devices, the receiver uses AGC (automatic gain control) to ensure that the useful signal falls on the device within the input dynamic range. Simply put, there is a negative feedback loop: detect the received signal strength (too low/too high)-adjust the amplifier gain (up/down)-the amplifier output signal to ensure that it falls within the input dynamic range of the next stage device.Here we talk about an exception: the front-end LNA of most mobile phone receivers has AGC function. If you study their datasheet carefully, you will find that the front-end LNA provides several variable gain sections, and each gain section has its corresponding noise factor. Generally speaking, the higher the gain, the lower the noise factor. This is a simplified design. The design goal of the receiver RF link is to keep the useful signal input to the receiver ADC within the dynamic range and keep the SNR higher than the demodulation threshold (the SNR is not critical,  but "just enough"). Therefore, when the input signal is large, the front-stage LNA reduces gain, loss NF, and increases IIP3 at the same time. When the input signal is small, the front-stage LNA increases gain, reduces NF, and meanwhile reduces IIP3. Figure 5. RFID Discover 1.9.3 Temperature Compensation Generally speaking, we only have temperature compensation in the transmitter. Of course, the receiver performance is also affected by temperature. On the one hand, the receiver link gain decreases at high temperatures, and NF increases. On the other hand, at low temperatures, receiver link gain increases, and NF decreases. However, due to the small signal characteristics of the receiver, both gain and NF are within the range of system redundancy.It can also be subdivided into two parts: one part is the compensation for the power accuracy of the transmitted signal, and the other part is the compensation for the change in the transmitter gain with temperature.Transmitters of modern communication systems generally perform closed-loop power control (except for the slightly "old" GSM system and Bluetooth system). Therefore, the power accuracy of transmitters calibrated through production procedures actually depends on the accuracy of the power control loop. Generally speaking, the power control loop is a small signal loop, and the temperature stability is very high, so the demand for temperature compensation is not high, unless there are temperature-sensitive devices (such as amplifiers) on the power control loop.Temperature compensation for transmitter gain is more common, which has two common purposes:One is "visible", usually for systems without closed-loop power control (such as the aforementioned GSM and Bluetooth), this type of system usually does not require high output power accuracy, so the system can apply a temperature compensation curve (function) to keep the RF link gain within an interval. So that when the baseband IQ power is fixed and the temperature changes, the RF power output by the system can also be kept within a certain range.The other is "invisible", usually in a system with closed-loop power control. Although the RF output power of the antenna port is precisely controlled by the closed-loop power control, we need to keep the DAC output signal within a certain range (A common example is the need for digital predistortion (DPD) of the base station transmission system), then we need to control the gain of the entire RF link more accurately around a certain value.In the early stage of low accuracy and low cost accuracy requirements, temperature compensation attenuators are more common. Require higher accuracy requirements, the solution generally: temperature sensor + digital attenuator/amplifier + production calibration. 1.9.4 Power Control of the Receiver After talking about dynamic range and temperature compensation, let's talk about a related and very important index: power control.Transmitter power control is a necessary function in most communication systems. Commonly used in 3GPP, such as ILPC, OLPC, and CLPC. In addition, it must be tested in RF design.All transmitter power control purposes include two points: power consumption control and interference suppression.Let’s first talk about power consumption control: In mobile communications, in view of the changes in the distance between the two ends and the different levels of interference, for the transmitter, it is only necessary to maintain the signal strength enough for the receiver of the other party to demodulate accurately. If it is low, the communication quality is impaired, and if it is too high, the empty power consumption is meaningless. This is especially true for battery-powered terminals like mobile phones.Interference suppression is a more advanced requirement. In CDMA-type systems, because different users share the same carrier frequency (differentiated by orthogonal user codes), in the signal arriving at the receiver, user's signal is covered by the same frequency for other users. If the signal power of each user is high or low, the high-power user will drown out the low-power user’s signal. Therefore, the CDMA system adopts a power control method to control the power of different users reaching the receiver, and sends a power control command to each terminal to make the air interface power of each user the same. This kind of power control has two characteristics: the first is that the power control accuracy is very high (the interference tolerance is very low), and the second is that the power control cycle is very short (the channel may change quickly).In the LTE system, uplink power control also has the effect of interference suppression. Because LTE uplink is SC-FDMA, and multiple users also share carrier frequencies, which also interfere with each other, so the same air interface power.The GSM system also has power control. In GSM, we use power level to characterize the power control step length, each level is 1dB. It can be seen that GSM power control is relatively rough.Interference Limited SystemHere is a related concept: interference limited system. The CDMA system is a typical interference limited system. In theory, if each user code is completely orthogonal and can be completely distinguished by interleaving and de-interleaving, then the capacity of the CDMA system can be infinite. Because it can be used on limited frequency resources. The user code extended layer by layer distinguishes an infinite number of users. But in fact, since the user codes cannot be completely orthogonal, noise is inevitably introduced during multi-user signal demodulation. The more users there are, the higher the noise will be, until the noise exceeds the demodulation threshold. In other words, the capacity of the CDMA system is limited by interference (noise).The GSM system is not an interference limited system, but a time-domain and frequency-domain limited system. Its capacity is limited by frequency (a carrier frequency of 200kHz) and time domain resources (8 TDMAs can be shared on each carrier frequency user). Therefore, the power control requirements of the GSM system are not strict. 1.9.5 Transmitter Power Control and Transmitter RF Indicators Next, let's discuss the factors that may affect the transmitter power control in the RF design.For RF, if the power detection (feedback) loop design is correct, then we can do not much for the transmitter closed-loop power control (most of the work is done by the physical layer protocol algorithm), and the most important thing is the flatness in the transmitter band.Because the transmitter calibration can only be carried out on a limited number of frequency points, especially in the production test, the less frequency points the better. However, it is entirely possible for the transmitter to work on any carrier in the frequency band in practice. In a typical production calibration, we will calibrate the transmitter's frequency points to keep accuracy. So the closed-loop power control is correct at the calibrated frequency points. However, if the transmit power is not flat in the entire frequency band, some frequency points deviates greatly from the calibration frequency point. Therefore, the closed-loop power control with the calibration frequency point as a reference will have errors and even mistakes.   Ⅱ FAQ 1. What is RFID and how it works?RFID tags transmit data about an item through radio waves to the antenna/reader combination. ... The energy activates the chip, which modulates the energy with the desired information, and then transmits a signal back toward the antenna/reader. 2. What is RFID used for?RFID tags are a type of tracking system that uses radio frequency to search, identify, track, and communicate with items and people. Essentially, RFID tags are smart labels that can store a range of information from serial numbers, to a short description, and even pages of data. 3. Is RFID harmful to human?Electromagnetic fields generated by RFID devices—touted as a patient-safety technique to keep track of supplies, medical tests and samples, and people—could cause medical equipment to malfunction, according to a recent study of medical devices in Amsterdam published in the June 25 Journal of the American Medical. 4. What is RFID example?For example, an RFID tag attached to an automobile during production can be used to track its progress through the assembly line, RFID-tagged pharmaceuticals can be tracked through warehouses, and implanting RFID microchips in livestock and pets enables positive identification of animals. 5. What are the components of RFID?Every RFID system consists of three components: a scanning antenna, a transceiver and a transponder. When the scanning antenna and transceiver are combined, they are referred to as an RFID reader or interrogator. 6. Who discovered RFID?Charles WaltonRFID was, however, officially invented in 1983 by Charles Walton when he filed the first patent with the word 'RFID'. NFC started making the headlines in 2002 and has since then continued to develop. 7. How is RFID made?The antenna can be made of etched copper, aluminum or conductive ink, while the chip and antenna are typically put on a substrate that is PET or paper. ... Usually, this inlay is inserted into a printable label to create an RFID transponder that can be affixed to a product. 8. Where did RFID come from?The First RFID PatentsMario W. Cardullo claims to have received the first U.S. patent for an active RFID tag with rewritable memory on January 23, 1973. That same year, Charles Walton, a California entrepreneur, received a patent for a passive transponder used to unlock a door without a key. 9. What is a RFID system?Radio Frequency Identification (RFID) refers to a wireless system comprised of two components: tags and readers. ... Passive RFID tags are powered by the reader and do not have a battery. Active RFID tags are powered by batteries. RFID tags can store a range of information from one serial number to several pages of data. 10. What are the three parameters that define an RFID system?Every RFID system consists of three components: a scanning antenna, a transceiver and a transponder. When the scanning antenna and transceiver are combined, they are referred to as an RFID reader or interrogator. 11. What are the basic criteria in RFID?Many large organizations and government agencies have mandated that their suppliers provide goods with RFID tags. These published mandates may specify tag type, frequency, amount of memory, read range, read rate and speed, and protocol. In addition, the mandates may specify how the goods should be tagged. 12. What is the maximum read range of RFID module?Maximum read distance of 1.5 meters (4 foot 11 inches) - usually under 1 meter (3 feet) and you can use a single or multi port reader plus custom antennas to extend the read range to longer tag read distances or a wider RFID read zone. 13. What is RFID in supply chain management?+RFID (Radio Frequency Identification) is a form of extremely low-power data communication between a RFID scanner and an RFID tag. ... The tags are placed on any number of items, ranging from individual parts to shipping labels. 14. How many bits does an RFID tag have?It depends on the vendor, the application and type of tag, but typically a tag carries no more than 2 kilobytes (KB) of data—enough to store some basic information about the item it is on. Simple “license plate” tags contain only a 96-bit or 128-bit serial number. 15. Does RFID reader store data?An RFID tag can store large amounts of data additionally to a unique identifier • Unique item identification is easier to implement with RFID than with barcodes. • Its ability to identify items individually rather than generically.

IntroductionThe 1N4007 is a general-purpose silicon rectifier diode, typically found in a plastic DO-41 axial package. It is widely used in various AC-to-DC rectifier circuits, bridge rectifier circuits, and general-purpose power supply applications. The 1N4007 utilizes the unidirectional conductivity of the P-N junction to convert alternating current into pulsed direct current. Due to its high reverse voltage rating (1000V) and low cost, it is one of the most popular components in electronics.Ⅰ 1N4007 Diode Specifications1.1 Rectifier Diode OverviewThe 1N4007 is a standard recovery rectifier diode. In low-power/low-current scenarios, the forward voltage (Vf) is typically around 0.7V to 0.8V. However, under its full rated load (1A), the forward voltage drop can reach up to 1.1V.Note on Frequency: The reverse recovery time (Trr) of the 1N4007 is in the microsecond (μs) range (typically 2μs to 30μs depending on conditions). This classifies it as a "slow" diode, meaning it is suitable for 50Hz/60Hz mains rectification but not suitable for high-frequency switching circuits (like high-frequency DC-DC converters), where Fast Recovery (FR) or Ultra-Fast (UF) diodes are required.Rectifier diodes make full use of unidirectional conductivity. They block the negative half-cycle of an AC waveform to convert it into a pulsating DC signal. To smooth this output, they are usually used in combination with a capacitor. The diode is connected in series, and the capacitor is connected in parallel to the load.Figure 1. 1N4007 Bridge Rectifier Circuit Example1.2 Nomenclature: What does 1N4007 mean?"1": Represents the number of junctions. In JEDEC nomenclature, "1" stands for a component with one P-N junction (a diode)."N": Stands for semiconductor device, registered with the EIA (Electronic Industries Alliance) / JEDEC."4007": The specific registration number indicating the device's electrical characteristics within the 1N400x series.1.3 1N4007 Pins and SymbolPINDescription1 (Marked with Band)Cathode (-)2 (Unmarked)Anode (+)1.4 1N4007 Basic Parameters (at 25°C)Type: Standard Recovery Silicon RectifierMax Average Forward Rectified Current (Io): 1.0 APeak Forward Surge Current (Ifsm): 30 A (for 8.3ms single half-sine-wave)Max Repetitive Peak Reverse Voltage (Vrrm): 1000 VMax DC Blocking Voltage: 1000 VMax Forward Voltage Drop (Vf): 1.1 V (at 1.0A current)Max Reverse Leakage Current (Ir): 5 μA (at rated DC blocking voltage)Typical Junction Capacitance (Cj): 15 pF (measured at 4V, 1MHz)Typical Thermal Resistance: 65 °C/W (Junction to Ambient)Operating Temperature Range: -55°C to +150°CFigure 2. Forward Current Derating Curve1.5 1N4007 FeaturesLow reverse leakage currentHigh surge current capability (up to 30A non-repetitive)RoHS compliant and available in Pb-Free packagesHigh-temperature soldering guaranteed: 260°C/10 seconds.Mechanical Data:Case: DO-41 Molded PlasticTerminals: Plated axial leads, solderable per MIL-STD-202Polarity: Color band denotes cathode endⅡ 1N4001-1N4007 Series ComparisonThe 1N400x series contains diodes that are physically identical and rated for the same current (1A). The only difference is the Maximum Repetitive Reverse Voltage (Vrrm). Because the 1N4007 has the highest voltage rating (1000V), it can replace any other diode in the series (1N4001 through 1N4006).ModelCurrent (A)Max Peak Reverse Voltage (V)Max RMS Voltage (V)1N4001150351N40021100701N400312001401N400414002801N400516004201N400618005601N400711000700Ⅲ Alternative Models & EquivalentsThe 1N4007 can often be replaced by higher-spec diodes.Higher Current: 1N5399 (1.5A) and 1N5408 (3.0A). Note: The 1N5408 has thicker leads and a larger body (DO-201AD) and may not fit all PCB holes designed for the 1N4007.Fast Recovery: If high-frequency performance is required, FR107 (Fast Recovery) or UF4007 (Ultra Fast) are excellent replacements. They share the same voltage/current ratings but switch off much faster.Schottky Diodes (Caution): While Schottky diodes like 1N5819 or 1N5818 have a lower forward voltage drop (higher efficiency), they usually have much lower reverse voltage ratings (often 20V-40V). Do not replace a 1N4007 with a Schottky diode in high-voltage circuits (like 110V/220V mains) or the diode will fail instantly. However, for low voltage (e.g., 12V) DC inputs, a Schottky like the SB1100 (100V) can be a more efficient substitute.ModelMax Reverse Voltage (V)Avg Rectified Current (A)Max Surge Current (A)Max Reverse Leakage (μA)1N4007100013051N539910001.55051N5408100032005FR10710001305 (Fast Recovery)Ⅳ 1N4007 vs. M7 (SMD Versions)When moving from Through-Hole Technology (THT) to Surface Mount Technology (SMT), the electrical equivalents of the 1N4007 are identified by different package codes.1N4007: This specifically refers to the DO-41 axial lead package (through-hole).M7: This is the SMA (DO-214AC) surface mount version of the 1N4007. It is electrically identical (1A, 1000V).A7: This is the SOD-123 surface mount version. It is smaller than the SMA package but carries similar specs (usually slightly lower thermal dissipation).SM4007: This generally refers to the MELF (DO-213AB) cylindrical surface mount package, though "SM4007" is sometimes used generically for any SMD version.Figure 3. DO-41 Package (1N4007)Summary: If you see a diode marked "M7" on a circuit board, it is a surface-mount 1N4007.Ⅴ 1N4007 Application Examples5.1 Solving Auxiliary Winding OvervoltageThe slow recovery characteristics of the 1N4007 can sometimes be advantageous over faster diodes in specific power supply applications.In Flyback power supplies, multi-output transformers can suffer from poor cross-regulation. A common issue is the VCC auxiliary winding voltage rising too high, triggering the IC's Over-Voltage Protection (OVP). This often happens because a fast diode (like the HER107) rectifies the high-frequency leakage inductance spike (the "ringing") at the leading edge of the waveform, rather than just the plateau voltage.Figure 4. IC Control CircuitSolution: By replacing the fast HER107 with a standard speed 1N4007, the slower turn-on time ignores the initial high-frequency spike. This effectively filters the peak voltage, lowering the average VCC voltage seen by the IC and preventing false OVP triggering.5.2 RCD Snubber EMI SuppressionIn RCD (Resistor-Capacitor-Diode) snubber circuits used to protect MOSFETs in Flyback converters, using a slow diode like the 1N4007 can help improve Electro-Magnetic Interference (EMI).Figure 5. RCD Absorption CircuitHow it works: A "fast" diode snaps off very quickly, which can induce high-frequency ringing. The 1N4007 takes longer to recover (reverse recovery). During this brief recovery period, a small amount of reverse current flows back. This "soft recovery" acts as a dampener, absorbing some of the oscillation energy and reducing the voltage stress and EMI radiation on the MOSFET drain.Trade-off: The downside is that the 1N4007 will generate more heat due to reverse recovery losses. This technique is generally suitable for lower-power adapters (<20W) where EMI is a priority and thermal overhead is available.Ⅵ FAQ1. What is a 1N4007 diode used for?It is a general-purpose rectifier diode used to convert AC to DC, prevent reverse polarity, and protect circuits from voltage spikes (flyback protection).2. What is the difference between 1N4001 and 1N4007?The only difference is the Peak Repetitive Reverse Voltage. The 1N4001 is rated for 50V, while the 1N4007 is rated for 1000V. 1N4007 can replace a 1N4001, but a 1N4001 cannot replace a 1N4007 in high-voltage circuits.3. Can I replace 1N4148 with 1N4007?Generally, No. The 1N4148 is a high-speed signal diode (very fast switching, low current). The 1N4007 is a power rectifier (slow switching, high current). • If you put a 1N4007 in a high-speed data circuit, it will be too slow and fail to work.• If you put a 1N4148 in a power circuit, it will likely burn out due to its lower current limit (200mA vs 1A).4. How much current can a 1N4007 diode handle?It can handle 1 Ampere of continuous rectified current. It can handle a non-repetitive surge of 30 Amperes (for less than 8.3ms), which is useful for inrush current at startup.5. What is the voltage drop of 1N4007?While often cited as 0.6V or 0.7V, under a full 1A load, the voltage drop is typically 0.9V to 1.1V.6. What is M7 diode?M7 is the surface-mount (SMD) code for the 1N4007 diode in an SMA package. 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