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LED

Philips aims LED replacement at high-bat and urban

Philips Lighting has introduced TrueForce LED Urban for replacing high pressure mercury (80W/125W) and sodium ovoid lamps (50W/70W) in streets, residential roads, parks and public squares.  The frosted version of the Urban produces 4,400 lm from a 33W input (133.33 lm/W @ 4,000K 70CRI), while the clear version puts out 4,800 lm. There are also frosted and clear 25W versions (2,900 and 3,200 lm). At the same time, it announced TrueForce LED Industrial and Retail for replacing traditional HID lamps – expected to be available in the second half of this year.The TrueForce LED range is rated at 50,000 hours and comes with a five-year warranty.The third stage of the European Commission Regulation (EC) 245/2009 came into effect on April 13, 2017 – introducing stricter efficiency requirements for HID lamps and requires light sources not meeting the minimum energy efficiency requirements to be phased out, said Philips.Ref:KY59-VC1512135W3DKY59-LE-MG-24W
kynix On 2017-05-11 
Mosfets

Electronics Tutorial: MOSFET Basics

  A MOSFET is a four-terminal device having source(S), gate (G), drain (D), and body (B) terminals. In general, the body of the MOSFET is in connection with the source terminal thus forming a three-terminal device such as a field-effect transistor. MOSFET is generally considered as a transistor and employed in both analog and digital circuits. This is the basic introduction to MOSFET. Let’s step into the world of MOSFET and find out its secret.     Catalog   I. What is MOSFET? 1.1 Brief Introduction 1.2 MOSFET Structure 1.3 Electrical Symbol and Types 1.4 MOSFET Operating Principle II. MOSFET Selection III. MOSFET Gate Material IV. MOSFET Advantage V. MOSFET Technology VI. Common MOSFET Failures VII. MOSFET Well-known Brands FAQ   I. What is MOSFET?   1.1 Brief Introduction     MOSFET(metal-oxide-semiconductor field-effect transistor) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This video will cover the basics of what you need to use it in your circuit, including calculating if you need a heat sink or not.   MOSFET (metal-oxide semiconductor field-effect transistor) is a kind of field effect transistors (FET), that is, the gate of metal layer (M) is separated by oxide layer (O) to control the semiconductors (S) by the field effect transistor.   1.2 MOSFET Structure   Fig. 1 mosfet body structure Fig. 1 is a cross-sectional view of a typical N-channel enhanced NMOSFET diagram. a P-type silicon semiconductor material is used as a substrate, two N-type regions are diffused on the surface of the substrate, a layer of silicon dioxide (SiO2) insulating layer is covered on the substrate, and finally, two holes are formed by using an etching method over the N region. The metallization method is used to make three electrodes: G (gate), S (source), and D (drain) in the insulating layer and the two holes, respectively.   From Fig. 1, we can see that the gate G is insulated from drain D and source S, and there are two PN junctions between D and S. In general, the substrate and the source S are connected internally, in other words, there is a PN junction between D and S.   Fig. 1 is a basic block diagram of a common n-channel enhancement MOSFET. To improve the performance of some parameters, such as improving the working current, increasing the working voltage, reducing the on-resistance, improving the switching characteristic, and so on. With different structures and processes, there are VMOS, DMOS, TMOS, etc. Although their structures are different, the working principle is the same.   1.3 Electrical Symbol and Types Fig. 2 mosfet symbols There are many variations in circuit symbols commonly used in MOSFET. The most common design is to represent the channel in a straight line, two lines perpendicular to the channel to represent the source and drain, and the left and the channel parallel and shorter lines to represent the grid. Sometimes a straight line representing the channel is replaced by a broken line to distinguish between an enhancement mode MOSFET or a depletion mode MOSFET and each mode divided into two types respectively, NMOSFET and PMOSFET. Fig. 3 NMOSFET and PMOSFET     Depletion Mode: the Gate-Source voltage of a transistor switches the device “OFF”. The depletion-mode MOSFET is equivalent to a “Normally Closed” switch.   Fig. 4 structure and electrical symbol  (depletion mode mosfet)   Enhancement Mode: the Gate-Source voltage of a transistor switches the device “ON”. The enhancement-mode MOSFET is equivalent to a “Normally Open” switch.   Fig. 5 enhancement type MOSFET(channel structure) Since the MOSFET on the integrated circuit chip is a four-terminal component, there is a bulk or body except for the gate, source and drain. The arrow extending from the channel to the right can indicate that the component is an NMOSFET or PMOSFET. In addition, the arrow direction is always pointed from the P end to the N end, so the arrow points from the channel to the base is the P-type MOSFET, abbreviated PMOS.   On the contrary, if the arrow points from the base to the channel, the base is P-type, and the channel is N-type, which is the N-type MOSFET. In a typical discrete device, that base and source are typically connected together so that the distributed MOSFET is typically a three-terminal element. Whereas a MOSFET in an integrated circuit, the polarity of the base is not indicated because of the use of the same base, and a circle is added to the gate terminal of the PMOS to distinguish.     P-Channel MOSFET: It has a P-Channel region between source and drain. It is a four-terminal device such as gate, drain, source, body. The drain and source are heavily doped p+ region and the body or substrate is n-type. The flow of current is positively charged holes. When we apply the negative gate voltage, the electrons present under the oxide layer are pushed downward into the substrate with a repulsive force. The depletion region populated by the bound positive charges which are associated with the donor atoms. The negative gate voltage also attracts holes from the p+ source and drain region into the channel region.       N- Channel MOSFET: It has an N-channel region between source and drain. It is a four-terminal device such as gate, drain, source, body. In this type of MOSFET, the drain and source are heavily doped n+ region and the substrate or body is P-type. The current flows due to the negatively charged electrons. When we apply the positive gate voltage the holes present under the oxide layer pushed downward into the substrate with a repulsive force. The depletion region is populated by the bound negative charges which are associated with the acceptor atoms. The electron's reach channel is formed. The positive voltage also attracts electrons from the n+ source and drains regions into the channel. Now, if a voltage is applied between the drain and source the current flows freely between the source and drain and the gate voltage controls the electrons in the channel. Instead of positive voltage if we apply negative voltage a hole channel will be formed under the oxide layer.       Therefore, the MOSFET has 4 modes: P-channel enhancement mode, P-channel depletion mode, N-channel enhancement mode, N-channel depletion mode. Their circuit symbols and application characteristic curves are shown in the following figure.  Fig. 6 circuit symbols and application characteristic curves of MOSFET 1.4 MOSFET Operating Principle The internal structure and electrical symbols of power MOSFET can be divided into NPN type and PNP type. That is, the source and drain poles of the N-channel FET are connected to the N-type semiconductor, and the source and drain of the P-channel FET are connected to the P-type semiconductor. We know that the output current of the general transistor is controlled by the input current. But for field-effect transistors, the output current is controlled by the input voltage (or field voltage), which can be considered to be minimal or no input current, causing the device to have a high input impedance, and it is the reason why we call it a FET.   The working principle of power MOSFET is as follows: adding positive power supply between drain and source, and no voltage between gate and sources. The PN junction J1 formed between drain and source is anti-biased, and there is no current flow between drain-source.    Conductive: adding the positive voltage UGS, the gate is insulated between the gate and source, so there will be no gate current flowing through. However, the positive voltage of the gate pushes the hole in the P region below it and attracts the minority electron in the P region to the surface of the P region below the gate when the UGS is greater than the UT (on voltage or threshold voltage). The electron concentration on the surface of the P region under the gate will exceed the hole concentration, making the P-type semiconductor invert into the N-type. For the inversion layer, the N-channel is formed and the PN junction J1 is disappeared, and meanwhile, the drain electrode and the source electrode are conductive.    Basic static characteristics of power MOSFET: Its transfer and output characteristics are shown in Fig. 7.   Fig. 7 transfer and output characteristics of mosfet The relationship between drain current ID and voltage UGS between gate and source is called the transfer characteristic of MOSFET. When ID is large, the relationship between ID and UGS is approximately linear, and the slope of the curve is defined as grid-anode transconductance Gfs.   The voltage-current characteristic (output characteristics) of drain include the cut-off region (corresponding to the cut-off region of GTR), the saturated region (corresponding to the magnification region of GTR), and the unsaturated region (corresponding to the saturation region of GTR). The MOSFET operates in the on-off state, that is, switching back and forth between the cut-off zone and the unsaturated zone. There are parasitic diodes between the drain and source, and the devices are on when a reverse voltage is added between the drain and source. The on-state resistance of the power MOSFET has a positive temperature coefficient, which is beneficial to the current sharing of the devices in parallel.   1. Cut-off Region: with the transistor acting as an open switch, the gate-source voltage is much lower than the transistor's threshold voltage so the MOSFET transistor is switched off fully.   2. Linear (Ohmic) Region: the transistor is in its constant resistance region behaving as a voltage-controlled resistance whose resistive value is determined by the gate voltage.   3. Saturation Region: the transistor is in its constant current region and is therefore switched on fully. The Drain current is equal to the maximum with the transistor acting as a closed switch.   Dynamic Properties   On-delay time (Td): it is the time experienced when the gate-source voltage rises to 10% of the gate drive voltage to the specified current rises to 10%.   Rise time (Tr): it is the time taken to increase the drain current from 10% to 90%. The ID steady-state value is determined by the drain-source voltage UE and the drain load resistance. The UGSP is related to the steady-state value of the ID, and when the UGS reaches the UGSP, it continued to increase until it reached the steady-state, but the ID did not change.   Turn-on time: the sum of turn-on delay time and rise time.   Turn-off delay time (Td): it refers to the time from when the voltage between gate and source drops to 90% of the gate drive voltage to the leakage current of 90% of the specified current. This shows the delay before the current is transferred to the load.    Drop time: it is the time experienced by the drain current drops from 90% to 10%.    Turn-off time: the sum of the turn-off delay time and drop time.   Understand several commonly used parameters of MOSFET. VDS is the drain-source voltage, which is an absolute parameter rating of MOSFET, which indicates the maximum voltage value that MOSFET can bear between drain and source. It is important to note that this parameter is related to junction temperature, and the higher the junction temperature is, the greater the value is. RDS (on), refers to the leakage source on-resistance, which represents the on-resistance between drain and source when MOSFET is on under certain conditions.    This parameter is related to MOSFET junction temperature and driving voltage Vgs. In a certain range, the higher the junction temperature, the greater the Rds, the higher the driving voltage, the smaller the Rds. Qg is the gate charge, gate charge is the charge required to increase the gate voltage from 0V to the termination voltage (such as 15V) under the action of the driving signal.   That is the charge required by the driving circuit from the cut-off state to the full-on state, which is the main parameter used to evaluate the driving ability of the driving circuit of the MOSFET. Id (drain current), is usually described in several different ways. According to the form of the working current, it divided into the continuous drain current and the pulse drain current.    In addition, it is also an absolute parameter rating of MOSFET, but this maximum current value does not mean that the drain current can reach this value during operation. It means that when the shell temperature is at a certain point if the operating current of MOSFET is the maximum drain current mentioned above, the junction temperature will reach the maximum value. Thus this parameter is also related to device packaging and ambient temperature.   Eoss (output volume energy), representing the output capacitance Coss stored in the MOSFET. Because the output capacitance Coss of MOSFET has very obvious nonlinear characteristics, it varies with the change of Vds voltage. If the datasheet identifies this parameter, it will be helpful to evaluate the switching loss of the MOSFET. The current rate of the body diode di/dt reflects the MOSFET reverse recovery characteristics. Because the diode is a bipolar device, it is affected by the charge storage, when the diode reverses bias, the charge stored in the PN junction must be removed, which is precisely the reaction of the above-mentioned parameters characteristic.   The maximum gate-source driving voltage Vgs, which is also an absolute parameter rating of the MOSFET, represents the maximum driving voltage that the MOSFET can withstand. Once the driving voltage exceeds this limit, permanent damage to the gate oxide can occur even in a very short period of time. Generally speaking, as long as the driving voltage does not exceed the limit, there will be no problem. However, due to the existence of parasitic parameters in some special cases, the Vgs will be affected unpredictably, which needs to be paid more attention to. SOA (safe work area), each MOSFET will give its safe working area. For example, different bipolar transistors, power MOSFET does not show a second breakdown, so the safe operation area is simply defined from the dissipative power that causes the junction temperature to reach the maximum allowable value.      II. MOSFET Selection   After understanding the principle of MOSFET selection, You can select the correct MOSFET with the following four steps.   1) channel selection The first step in choosing the right device for design is to decide whether to use N-channel or P-channel MOSFET. In typical power applications, when a MOSFET is grounded and the load is connected to the trunk voltage, the MOSFET forms a low-voltage side switch. N-channel MOSFET should be used in the low-voltage side switch, which is due to the voltage required by switching on or switching off the device. When the MOSFET is connected to the bus and the load is grounded, the high-voltage side switch is used. P-channel MOSFET is usually used in this case, which is also due to the consideration of driving voltage.   2) selection of voltage and current The higher the rated voltage, the higher the cost of the device. According to practical experience, the rated voltage should be greater than trunk voltage or bus voltage. This will provide sufficient protection so that the MOSFET can work well. As far as MOSFET is concerned, it is necessary to determine the maximum possible voltage between the drain and the source. Other safety factors that design engineers need to consider include voltage transients induced by switchgear, such as motors or transformers. And rated voltages vary from application to application, typically, portable devices are 20V, FPGA power supplies are 20V~30V, and so on.    In the continuous conduction state, the MOSFET is stable and the current passes through the device continuously. A pulse spike refers to a large number of surge current (or peak current) flowing through the device. Once the maximum current is determined under these conditions, simply select the device that can withstand the maximum current.   3) calculating on-loss The power loss of MOSFET devices can be calculated by Iload2×RDS (on). Because the on-resistance varies with temperature, the power loss also varies proportionally. For portable designs, lower voltages are more common, and for industrial designs, higher voltages can be used. Note that the RDS (on) resistance increases slightly with the current. Variations in the electrical parameters of the RDS (on) resistance can be found in the technical datasheet provided by the manufacturer.   4) heat dissipation requirements for a computing system  The designer must consider two different situations, the worst case, and the real situation. It is recommended that the worst-case results be used because the results provide a greater security margin to ensure that the system does not fail. There are also some measurements on the MOSFET table that need to be noticed, such as the thermal resistance between the semiconductor junction and the environment of the packaged device, and the maximum junction temperature.   Switching loss is also a very important indicator. The voltage-current product of the on-off moment is quite large, which determines the switching performance of the device to a certain extent. However, if the system requires high switching performance, you can choose a power MOSFET with a lower gate charge.     III. MOSFET Gate Material   Theoretically, the gate of MOSFET should be chosen as well as possible, and the conductivity of polysilicon doped by heavy can be used on the gate of MOSFET.    The reasons for using polysilicon in MOSFETs are as follows:    1) The threshold voltage of the MOSFET is mainly determined by the difference between the work function of the gate and the channel material, and because the polysilicon is essentially a semiconductor, it is possible to change its work function by doping impurities of different polarities. More importantly, since the gap between the polysilicon and the silicon as the channel is the same, it is possible to achieve the demand by directly adjusting the work function of the polysilicon when the threshold voltage of the PMOS or NMOS is reduced. Conversely, the work function of the metallic material is not like the semiconductor is then easily changed so that it becomes difficult to reduce the critical voltage of the MOSFET. And if the threshold voltage of the PMOS and the NMOS is to be reduced at the same time, two different metals are required to do their gate material, respectively, and a large variable for the producing process.   2) After years of research on the silicon-silica interface, it has been proved that the defect between the two materials is relatively small. On the contrary, there are many defects in the metal-insulator interface, so it is easy to form a lot of surface energy levels between the two, which greatly affects the characteristics of the elements.   3) The melting point of the polycrystalline silicon is higher than most of the metal, while in the modern semiconductor process, the gate material is used to deposit the gate material at high temperatures to improve the efficiency of the element. The low melting point of the metal will affect the upper-temperature limit that can be used by the process.   However, although polysilicon has been the standard material for the manufacture of MOSFET gates, there are also a number of shortcomings of it, which makes it possible for some MOSFET to use metal gates in the future.    These shortcomings are as follows:   (1) Polysilicon is less conductive than metal, limiting the speed of signal transmission. Although doping can be used to improve its conductivity, the effectiveness is still limited. Some metal materials with a high melting point, such as tungsten, titanium, cobalt, or nickel, are used to make alloys with polysilicon. This type of mixture is commonly referred to as metal silicide. The polysilicon gate with metal silicide has good electrical conductivity and can withstand a high-temperature process. In addition, because the position of the metal silicide is on the surface of the grid, therefore, the critical voltage of MOSFET will not be affected much.   The process of plating a metal silicide on the gate, source, and drain is referred to as self-aligned metal, commonly referred to as salicide process.   (2) When the size of the MOSFET is small and the gate oxide layer also becomes very thin, for example, the new process can reduce the oxide layer to a thickness of about one nanometer, and a phenomenon is also generated unprecedentedly, and that is "polysilicon depletion". When the inversion layer of the MOSFET is formed, the MOSFET gate polysilicon depletion phenomenon is occurring close to the oxide layer, and a depletion layer is present to influence the conduction characteristics of the MOSFET. To address this problem, one way is the metal gate. Reasonable materials include tantalum, tungsten, tantalum nitride, or titanlium nitride. The gates made by these metals usually form MOS capacitors along with oxide formed by high permittivity substances. Another solution is the polysilicon alloying, also called FUSI (FUlly-SIlicide polysilicon gate).   IV. MOSFET Advantage   MOSFET was first made successfully in 1960 by D. Kahng and Martin Atalla in Bell Labs, and the operating principle of this element was very different from that of the bipolar junction transistor (BJT) invented by William Shockley in 1947. And because of the low cost and small size, it plays a very important role in large-scale integrated circuits (LSI) and very large-scale integrated circuits (VLSI) than BJT.   1) Field-effect transistor (FET) is a voltage control element, and bipolar junction transistor (BJT) is a current control element. The FET should be selected when only less current is allowed, and the BJT should be chosen when the signal voltage is low and more current is allowed to flow through from the source of the signal.   2) The source and drain poles of some FET can be used interchangeably, the gate voltage can also be positive and negative, and the flexibility is better than the bipolar transistor.   3) FET is called a monopole device because it makes use of majority carriers to conduct electricity, while BJT is conducting by majority carrier or minority carrier, therefore, it is called bipolar device.   4) FET can work under the conditions of very low current and low voltage, and its manufacturing process can easily integrate many FETs on a silicon wafer. Therefore, FET has been widely used in large-scale integrated circuits (LSI).   With the improvement of the performance of MOSFET components, except the traditional applications in digital signal processing such as microprocessors and microcontrollers, more and more integrated circuits for analog signal processing can be implemented by MOSFET.   V. MOSFET Technology   1) Dual-gate MOSFET Dual-gate MOSFET is usually used in radio frequency (RF) integrated circuits. The two gates of the MOSFET can control the current. In RF circuits, the second gate of the dual-gate MOSFET is mostly used for gain, mixer, or frequency conversion control.   2) Depletion Type MOSFET In general, a depletion-mode MOSFET is less common than the enhancement mode MOSFET. The depletion-mode MOSFET changes the impurity concentration of the channel in the doping process so that the channel still exists even if the gate of the MOSFET is not applied voltage. If you want to close the channel, you must apply a negative voltage to the gate. Thus the most application of the depleted MOSFETs is in the "normally-off" switch, while the enhancement-mode MOSFET is usually used in the " normally-on" switch.   3) NMOS Logic The NMOS of the same driving capability is generally smaller than the area occupied by the PMOS, and therefore, if an NMOS is used only on the design of the logic gate, the chip area itself can be reduced. However, although the area of the NMOS logic is small, the static power will be consumed unlike the CMOS logic, so it has gradually exited the market after the mid-1980s.   4) Power MOSFET There is a significant structural difference between the power MOSFET and the above-mentioned MOSFET elements. In general, MOSFET in integrated circuits are planar structures, and the endpoints of transistors are only a few microns away from the surface of the chip. But all the power components are vertical structures, which allows the components to withstand both high voltage and high current working environments. A power MOSFET withstand voltage is a function of the doping concentration and the thickness of the N-type epitaxial layer, and the width of the channel is related to how much the current can pass through, that is, the wider channel can accommodate more current. For a planar MOSFET, the current and the breakdown voltage are dependent on the length and width of the channel. For a vertical MOSFET, the area of the element is approximately proportional to the current it can hold, and the thickness of the epitaxial layer is proportional to its breakdown voltage.   Working principle Due to the positive power supply between the source and the drain, the voltage between them is zero. The PN junction J1 formed between the P base region and the N drift region is anti-biased, and no current flows between the source and the drain.   Conduction: the positive voltage UGS, the gate is insulated between the gate and the source, so there will be no gate current flowing through. However, when the positive voltage of the gate pushes the hole in the P region below it and attracts the minority electron in the P region to the surface of the P region below the gate and the UGS is greater than the UT (on voltage or threshold voltage), the electron concentration on the surface of the P region under the gate will exceed the hole concentration, which causes the P-type semiconductor inversion to become N-type and becomes the inversion layer. The inversion layer forms N-channel and makes the PN junction J1 disappear, and the drain and the source turn to conductive.   It is worth mentioning that power MOSFET with planar structure is not non-existent, and this kind of element is mainly used in advanced sound amplifiers. The characteristics of planar power MOSFET in the saturation region are better than that of vertical structure MOSFET. Vertical power MOSFET takes the advantage of very small turn-on resistance and is mostly used for switches.   5) DMOS DMOS is an abbreviation for a double-diffused MOSFET, which is mainly used for high voltage and belongs to the category of high-voltage MOSFET.   The MOSFET is used to realize the analog switch. The channel resistance of the MOSFET is low when the MOSFET is turned on, and the resistance is almost infinite when the MOSFET is turned off so that the switch which is suitable as a switch of the analog signal (the energy of the signal is not lost due to the resistance of the switch). When the MOSFET is a switch, its source and drain are different from each other, respectively, because the signal can be accessed from any end of the MOSFET. For an NMOS switch, the negative voltage is in the source, it opposite to the PMOS, the positive voltage is in the source. The signal that the MOSFET switch can transmit is subject to its voltage between gate and source, gate and drain, drain and source. If the upper limit of the voltage is exceeded, the MOSFET may burn out.   MOSFET switches have a wide range of applications, such as the need for sampling holding circuit (sample-and-hold circuits) or truncated circuit (chopper circuits) design, For example, MOSFET switch can be seen on the analog-digital converter (A / D converter) or switched capacitor filter (switch-capacitor filter).   6) Single MOSFET Switch When the NMOS is used as a switch, the base is grounded and the gate is the controlling end of the switch. The state of the switch is on when the gate voltage subtracts the source voltage exceeding the critical voltage. If the gate voltage continues to rise, the current through which the NMOS can pass more. NMOs operate in the linear region when the switch is turned on because the voltage of the source and drain tends to be consistent when the switch is on.   When the PMOS is used as a switch, its base is connected to the highest potential in the circuit, usually a power supply. The voltage of the gate is very low than the source. And when the gate exceeds the critical voltage, the PMOS switch will be turned on.   And a single MOSFET switch may reduce the amplitude of the signal and distort the signal.   7) Double MOSFET (CMOS) Switch In order to improve the signal distortion caused by the single MOSFET switch mentioned above, the use of a PMOS plus and an NMOS of CMOS switch has become the most common practice at present. The PMOS switch connects the source and drain of the NMOS separately. The basic joining rule is the same as the traditional connecting method of NMOS and PMOS. When the input voltage is at (VDD-Vthn) and (VSS+Vthp), the PMOS and NMOS are on, but when the input is less than (VSS+Vthp), only NMOS is on and the input is greater than (VDD-Vthn), and only the PMOS turns on. The advantage of this is that under most of the input voltage, both the PMOS and the NMOS are turned on at the same time, and if the on-resistance of either side is increased, the on-resistance on the other side is reduced, so that the resistance of the switch can be kept almost constant, thus the signal distortion is reduced.   Fig. 8 switching process of power MOSFET   VI. Common MOSFET Failures     Overvoltage damage, including gate overvoltage and drain overvoltage, often accompanied by overcurrent. If protection happened in a very short period of time, it may be overvoltage damage. If there is no overvoltage protection and the state turns into overcurrent damage, the chip in the source non-line region will burn out.   A large current, such as severe over-current short-circuit damage, will cause a large amount of heat to burn out the chip.   Overheat damage, if the MOS tube isn’t appearing overcurrent and overvoltage, just because the junction temperature is too high, if the chip is protected, the surface will not see obvious burns, if not, there will be a large amount of burning area.   In general, the mechanism of MOS tube damage is usually thermal damage, local overheating, or overall heating, such as overvoltage, is a crystal package that can’t stand high voltage breakdown causing heating damage.   The fault analysis of the MOS tube should be based on the combination of specific circuit and burning phenomenon to be more accurate. Fig. 9 basic structure of an n-channel mosfet     VII. MOSFET's Well-Known Brands   MOSFETs are mainly divided into several series: American, Japanese, Korean, Taiwan, and so on. The brand's representatives of each system are as follows:   American: IR ST TI PI Fairchild Infineon ON Semiconductor Japanese: TOSHIBA RENESAS SHINDENGEN Taiwan: APEC CET Korean: KEC AUK MagnaChip KIA Truesemi Wisdom   FAQ 1. What is Mosfet and how it works? In general, the MOSFET works as a switch, the MOSFET controls the voltage and current flow between the source and drain. The working of the MOSFET depends on the MOS capacitor, which is the semiconductor surface below the oxide layers between the source and drain terminal.   2. What is Mosfet and its characteristics? MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form an integral part of vast variety of electronic circuits. ... In this region, MOSFET behaves like an open switch and is thus used when they are required to function as electronic switches.   3. How many types of Mosfet are there? Four types. There are two classes of MOSFETs. There is depletion mode and there is enhancement mode. Each class is available as n- or a p-channel, giving a total of four types of MOSFETs.   4. What is an ideal Mosfet? In an ideal MOSFET, setting the gate-source voltage to a value VGS < VTn places the transistor into cutoff with ID = O. Increasing the gate-source voltage to a value VGS > VTn allows the transistor to conduct current ID; this defines the active mode of operation. 5. How do I know if my MosFet is bad? A good MOSFET should have a reading of 0.4V to 0.9V (depends on the MOSFET type). If the reading is zero, the MOSFET is defective and when the reading is “open” or no reading, the MOSFET is also defective. When you reverse the DMM probe connections, the reading should be “open” or no reading for a good MOSFET.   6. What is a Mosfet used for? What is a MOSFET and How does it work? MOSFET, in short, is a metal oxide semiconductor field-effect transistor used to switch or amplify voltages in circuits. Being part of the field-effect transistor family, it is a current-controlled device that is constructed with 3 terminals.   7. Is Mosfet still used? The MOSFET is by far the most widely used transistor in both digital circuits and analog circuits, and it is the backbone of modern electronics. It is the basis for numerous modern technologies, and is commonly used for a wide range of applications.   8. Why is it called Mosfet? The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.   9. What causes a Mosfet to fail? If the maximum operating voltage of a MOSFET is exceeded, it goes into Avalanche breakdown. ... If the energy contained in the transient over-voltage is above the rated Avalanche energy level, then the MOSFET will fail. The device fails short circuit, initially, with no externally visible signs.   10. Why N channel is better than P channel Mosfet? N-Channel MOSFETs are more efficient than P-Channel MOSFETs.It comes down to physics. N-Channel MOSFETs use electron flow as the charge carrier. P-Channel MOSFETs use hole flow as the charge carrier, which has less mobility than electron flow. And therefore, they have higher resistance and are less efficient.   You May Also Like Selection of Drive Resistor: MOSFET | Gate Drive Reference Component KY56-SQ7415AEN-T1_GE3 KY56-STP160N3LL
kynix On 2017-05-10 
FPGA

What is an FPGA? A Basic Introduction [FAQ]

FPGA (Field-Programmable Gate Array), it is the product of further development on the basis of PAL, GAL, CPLD and other programmable devices. It appears as a kind of semi-custom circuit in the field of application specific integrated circuit (ASIC). It not only solves the shortage of custom circuit, but also overcomes the shortcoming of limited number of gates in the original programmable devices.What is an FPGA, and how does it compare to a microcontroller?CatalogI. What is FPGA?II. Principles of FPGAs III. FPGA Pros & ConsIV. FPGA Chip StructureV. FPGA FeaturesFAQI. What is FPGA?FPGA (Field Programmable Gate Array) is a product of further development on the basis of programmable devices such as PAL and GAL. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the deficiencies of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.II. Principles of FPGAs FPGA adopts the concept of Logic Cell Array (LCA), which consists of Configurable Logic Block (CLB), Input Output Block (IOB) and Internal Interconnect. Three parts. FPGAs are programmable devices with a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The logic of the FPGA is implemented by loading programmed data into the internal static memory cell, and the values stored in the memory cell determine the logic function of the logic cell and the connection between the modules or between the modules and the I/O. The value stored in the memory cell determines the logical function of the logic unit and the way the modules are linked to each other or to the I/O, and ultimately determines the functions that the FPGA can achieve.III. FPGA Pros & Cons - The Pros of FPGAs:(1) FPGAs consist of hardware resources such as logic cells, RAM, multipliers, etc. By organizing these hardware resources rationally, hardware circuits such as multipliers, registers, address generators, etc. can be implemented.(2) FPGAs can be designed by using block diagrams or Verilog HDL, from simple gate circuits to FIR or FFT circuits.(3) FPGAs can be infinitely reprogrammed, loading a new design solution in a few hundred milliseconds, reducing hardware overhead with reconfiguration.(4) The operating frequency of the FPGA is determined by the FPGA chip as well as the design, and can be modified by modifying the design or replacing it with a faster chip to meet certain demanding requirements (of course, the operating frequency is not unlimited and can be increased, but is governed by current IC processes and other factors).  - The Cons of FPGAs:(1) All functions of FPGAs rely on hardware implementation and cannot implement operations such as branching conditional jumping.(2) FPGAs can only implement fixed-point operations.To conclude: FPGAs rely on hardware to implement all functions and can be compared to dedicated chips in terms of speed, but there is a big gap in design flexibility compared to general purpose processors.IV. FPGA Chip StructureMainstream FPGA is still based on look up table technology, has far exceeded the basic performance of previous versions, and integrates common features (such as RAM, clock management and DSP). FPGA chips have seven main parts: programmable input/ output unit, basic programmable logic unit, complete clock management, embedded block RAM, rich wiring resources, embedded bottom functional unit and embedded special hardware module.The functions of FPGA chip structure are as follows:1. Programmable Input and Output BlockThe programmable input/ output block is referred to as I/ O port. It is the interface part between the chip and the external circuit, which can drive and match the input/ output signals under different electrical characteristics. I/ O in FPGA is classified by group, and each group can support different I/ O standards independently. With the flexible configuration of the software, different electrical standards and I/ O physical characteristics can be met, the drive current can be adjusted, and the frequency of I/ O port of the and pull-up resistor and pull-down resistor can be changed, so that the frequency of the I/ O port can be higher and higher. Some high-end FPGA can support data rate up to 2Gbps through DDR register.Fig 1. IOB Internal Structure DiagramThe external input signal can be read into the FPGA through the memory cell of the IOB module, or directly written into the inside of the FPGA. When the external input signal passes through the memory cell of the IOB module read into the inside of the FPGA, the requirement of hold time  can be reduced, which usually the windows default is 0.In order to facilitate management and adapt to a variety of electrical standards, FPGA's IOB is divided into several banks, each bank interface standard is determined by its interface voltage VCCO, in addition, a bank can only have one VCCO, but each bank VCCO can be different. Only ports with the same electrical standard can be connected together, and the same VCCO voltage is the basic requirement of the interface standard.2. Configurable Logic Block (CLB)CLB is the basic logical unit within the FPGA. The actual number and characteristics of CLBs vary depending on the device, but each CLB contains a configurable switch matrix that consists of 4 or 6 inputs, some lectotype circuits (multiplexers, etc.) and flip-flops. The switch matrix is highly flexible and can be configured to work with combinational logic, shift registers, or RAM. In Xilinx's FPGA device, the CLB consists of multiple (usually 4 or 2) identical Slices and additional logic. Each CLB module be used to realize combinational logic and sequential logic, and it can also be configured as distributed RAM and distributed ROM.Fig 2. CLB Structure DiagramSlice is a basic logical unit defined by Xilinx. A Slice consists of two 4-input functions, carry logic, arithmetic logic, storage logic and function multiplexer. Arithmetic logic includes a  XORG and a MULTAND. XORG enables a Slice to implement the full operation of 2bit, and MULTAND improves the efficiency of multipliers. Carry logic consists of a dedicated carry signal and a function multiplexer for fast arithmetic addition and subtraction operations; 4-input functions generator is used to implement the 4-input LUT, distributed RAM or 16-bit shift register. Carry logic includes two fast carry chains to improve the processing speed of the CLB module.Fig 3. Inputting Slice Structure Diagram3. Digital Clock Management (DCM)Most of the industry's FPGA offer digital clock management. FPGA offers digital clock management and phase loop locking. Phase loop locking can provide accurate clock synthesis, reduce jitter and achieve filtering.4. Block Random Access Memory (BRAM)Most FPGAs have embedded block RAM, which greatly extends the applications and flexibility of the FPGA. The block RAM may be configured as a single-port RAM, a dual-port RAM, a content address memory (CAM), and a common storage structure such as a FIFO. CAM memory has a comparison logic in each of its internal memory cells, the data written into the CAM will be compared with each of the data in the interior, and the address of all data that is the same as the port data, so that there is a wide range of address switches in the route application. In addition to the block RAM, the LUT in the FPGA can be flexibly configured as a RAM, a ROM, and a FIFO. In practical application, that number of block RAM in the internal block of the chip is also an important factor in the chip selection.The capacity of the monolithic RAM is 18k bits, that is, the bit width is 18 bits and the depth is 1024. It can change the bit width and depth according to the need, but two principles must be satisfied: firstly, the modified capacity (bit width depth) cannot be greater than 18k bits; Second, the maximum bit width cannot exceed 36 bits. Of course, it is possible to concatenate multiple blocks of RAM to form a larger RAM, which is limited only by the number of RAM blocks in the chip and is no longer constrained by the above two principles.5. Wiring SourceAll the parts are connected with wiring resources in the FPGA, and the length and process of the connection determine the driving ability and the transmission speed of the signal on the wire. There are abundant wiring resources in the FPGA chip, according to the process and length, width and distribution position, which are divided into 4 different categories. First is the global routing resource, which is used for the internal global clock and the global reset/ position routing. Second is the long line resource, which is used to complete the wiring of the high-speed signal and the second global clock signal between chip banks. Third is short-line resources, which are used to perform logical interconnection and cabling between basic logical units. Fourth is a distributed wiring resource, which is used as control signal lines for a proprietary clock or a reset.In practice, the designer does not need to select the routing resources directly, and the layout scheduler can automatically select the better routing resources according to the topology of the input logical grid table and constraint conditions to connect each module unit. In essence, the use of routing resource types has a close and direct relationship with the results of the design.6. Underlying Built-in Function The underlying built-in function mainly refers to a DLL (Delay Locked Loop), a PLL (Phase Locked Loop), a DSP, and a CPU, which belong to core softcore. The more and more built-in functional units make the single-chip FPGA a system-level design tool, so that it has the capability of joint design of hardware and software, and gradually turn to the SOC platform.DLL and PLL have similar functions, such as high-precision clock and low jitter frequency doubling and frequency division, duty cycle adjustment and phase shift, etc. Xilinx integrated the DLL, Altera made the PLL, Lattice combined both two, which can be easily managed and configured through IP core-generated tools on Lattice's new chip. Fig 4. Typical DLL module schematics7. Special Built-in Hard CoreThe embedded special hard core is relative to the soft core embedded in the bottom, which means that the hard core with strong processing ability of FPGA is equivalent to the ASIC. To improve FPGA performance, chip manufacturers integrate some dedicated hard cores on the chip. For example, to improve the multiplication speed of FPGA, special multipliers are integrated in the mainstream FPGA, and in order to match the communication bus and interface standard, a lot of high-end FPGA are integrated SERDES, which can achieve the receiving and dispatching speed of  Gbps. V. FPGA Features1) The ASIC circuit is designed by adopting the FPGA, and the user does not need to put the chip into production, so that a shared chip can be obtained.2) FPGA can be used as a trial sample of other fully customized or semi-custom ASIC circuits.3) There are rich flip-flops and I/ O pins within the FPGA.4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the least risk among ASIC circuits.5) FPGA adopts high-speed CMOS process, low power consumption, and can be compatible with CMOS and TTL.It can be said that FPGA chip is one of the best choices for small batch system to improve system integration and reliability.The working state of FPGA is set by the program stored in the on-chip RAM, so it is necessary to program the on-chip RAM when working. Users can use different programming methods according to different configuration modes.When the power is on, the FPGA chip reads the data from the EPROM into the on-chip programming RAM. After the configuration is completed, the FPGA enters the working state. After power off, FPGA internal logic disappears. Therefore, FPGA can be programmed repeatedly. And the programming of FPGA does not require a special programmer, a general-purpose EPROM or PROM programmer can meet the requirement. When you need to modify the FPGA functionality, just replace a piece of EPROM. In this way, the same piece of FPGA, with different programming data, can produce different circuit functions. Therefore, the use of FPGA is very flexible.FAQ 1. What is FPGA and why it is used?FPGA Basics: Architecture, Applications and Uses. The field-programmable gate array (FPGA) is an integrated circuit that consists of internal hardware blocks with user-programmable interconnects to customize operation for a specific application.2. Is FPGA faster than CPU?They also found that using custom FPGAs to implement the Rowhammer exploit would cause far more of the "bit flips" that they wanted to see. A FPGA can hit the data cell faster and more often than a CPU can do it meaning the FPGA causes more results to occur during an attack. It all goes faster when an FPGA is used.3. Are FPGAs dead?Yes, it's a dead end. If you enjoy creating hardware, RTL design targeting FPGAs is still a good choice (although there is a huge amount of effort here to make it more like creating software than hardware).4. What are FPGAs good for?FPGAs are particularly useful for prototyping application-specific integrated circuits (ASICs) or processors. An FPGA can be reprogrammed until the ASIC or processor design is final and bug-free and the actual manufacturing of the final ASIC begins. Intel itself uses FPGAs to prototype new chips.5. Is FPGA a microprocessor?Microprocessors are more complex than FPGAs. Microprocessors have fixed instructions while FPGAs don't. FPGAs and microprocessors are often mixed into a single package.6. What are the advantages of FPGA?FPGA advantages:Long-term availability.Updating and adaptation at the customer.Very short time-to-market.Fast and efficient systems.Acceleration of software.Real-time applications.Massively parallel data processing.7. Why is FPGA slow?FPGAs tend to get faster in max speed, but the limit actually has to do with process variation affecting static timing. The chips have to have a soultion that works on all of them. So you lose performance of the device to make sure any device will work with it. And as your design gets bigger it runs slower.8. What are the disadvantages of FPGA?Drawbacks or disadvantages of FPGA:The programming is not as simple as C programming used in processor based hardware. Moreover engineers need to learn use of simulation tools. ➨The power consumption is more and programmers do not have any control on power optimization in FPGA. No such issues in ASIC.9. Can FPGA replace CPU?There will always be a need for a general purpose CPU to run most things, and while you can implement a CPU on an FPGA, that gives you the worst of both worlds - no improvement from specialised hardware design, and you still need to pay the “FPGA tax”. So no, FPGAs will never replace CPUs.10. Why use an FPGA vs microcontroller?A FPGA can be used if the design requires complex logic and requires high processing ability and if the cost is comparable to the performance achieved. In case of a design that requires limited hardware, and is set to perform only some specific functions, then Microcontroller is preferred.
Kynix On 2025-04-29 
Robots

Lattice uses FPGA to cut image processing power for robots

Lattice Semiconductor has introduced its first embedded vision development kit for mobile designs that require low power image processing.  The low power processing comes from the firm’s ECP5 FPGA, which is combined with an HDMI chip and CrossLink pASSP mobile bridging device.According to Lattice product marketing director, Deepak Boppana, the low power  mobile applications include machine vision, smart surveillance cameras, robotics, AR/VR, drones and Advanced Driver Assistance Systems (ADAS).The CrossLink input board includes dual-camera HD image sensors supporting the MIPI CSI-2 interface, eliminating the need for external video sources.The ECP5 base board enables low-power pre/post processing and includes support for HD image signal processing IP from Helion Vision.Also included is a NanoVesta connector to support external image sensor video inputs. The HDMI output board based on the Sil1136 non-HDCP version enables connectivity to standard HDMI displays.Ref:KY32-LFSCM3GA25EP1-6F900CKY32-ICE65L04F-TCS63I
kynix On 2017-05-08 
IC Chips

Novel technique measures warpage in next-gen integrated circuits

As integrated circuit components are coming up against size limits, manufacturers are turning to new approaches based on stacking extremely thin wafers. However, the thin wafers easily warp under the stresses involved in fabrication, and measuring the stress and warpage has so far proven challenging.In a paper published in the Journal of Applied Crystallography, Professor Patrick McNally's team at Dublin City University, together with collaborators Brian Tanner at Durham University and Andreas Danilewsky at the University of Freiburg, report on a new technique using the Test beamline (B16) at Diamond Light Source to accurately, precisely, and verifiably measure the stress and warpage in individual silicon wafers. The researchers are now cooperating with industry partners to translate their approach into a tool which can be used for quality assurance and to improve fabrication processes. Meanwhile, they continue to work at Diamond to improve the technique and adapt it to different contexts and materials.A stack of measurement troubleIn a 1965 paper, Intel co-founder Gordon Moore observed that the density of transistors in integrated circuits doubled every 18-24 months, a trend which has held well in the decades since. However, manufacturing techniques are nearing the limits of 'Moore's law' as the components printed onto integrated circuits approach atomic dimensions. To continue improving performance, manufacturers are exploring a new direction by combining different chips, each with a specialised function, into a vertical package in a 'more than Moore' approach known as heterogeneous integration.The new technique involves using wafers less than a tenth as thick as those currently in use. Since they are so thin – just 25 to 100 µm – the wafers are extremely flexible, but they are also subjected to extreme stress during the fabrication process. "Imagine you glue together four or five pieces of silicon, each thinner than a human hair, then heat them up to 100-200° C, and then stand on top of them with your boot. Maybe you jump up and down a bit. That's the sort of damage that's done as part of semiconductor processing," explains Professor Patrick McNally of Dublin City University. The stress and resulting warpage of the wafers during manufacturing can lead to malfunctions, altered performance, and silicon 'real estate' lost to stress-related 'keep out zones' on the chip. To avoid these pitfalls, manufacturers are eager to understand how to manage stress and warpage in their design and fabrication processes.So far, measuring the warpage of the individual silicon wafers without damaging them has been impossible, forcing people to use the warpage of the entire package as a proxy. Using the Test beamline (B16) at Diamond, the trio have developed a non-destructive technique to precisely and accurately measure the warpage of each wafer in a package through transmission X-ray diffraction imaging. To confirm their measurement technique, the team included samples with known curvature and displacement from IMEC in Belgium. "We've proven that it can be done reliably and verifiably," said Professor McNally.To industry and beyondWhile the new technique shows great promise, "no one in the semiconductor business is going to back a synchrotron into their fabrication facility," noted Professor McNally. The team has already successfully carried out preliminary trials with a commercial tool as an X-ray source, and work is underway with X-ray metrology companies to bring the technique into industry as a quality assurance tool. Improving the measurement speed of the commercial tools is a major outstanding challenge – measurements done in minutes at Diamond can take hours with commercial tools – but the team is pursuing avenues to improve this.The technique offers an opportunity not only to measure warpage during fabrication but also to improve the design process. Mechanical engineers at a large chip company are working with the team to test the finite element models they use to predict stress and warpage in their designs. "The idea is that we provide a 'sanity check' on their modelling so they can use it to improve their designs," said Professor McNally.Meanwhile, the team is continuing to develop the approach using the facilities at Diamond, which underpins any advancements. The team has recently tested their new technique on chips, which were receiving power to measure how the warpage might change under different usage conditions. "We do our top end development at Diamond," said Professor McNally, explaining that the ability to rapidly test and explore ideas at the synchrotron is crucial before they can be adapted for industry applications.Ref:KY32-MAX1490AEPG+KY32-LMX4169AQFXN      
kynix On 2017-05-05 
IC Chips

Intel launched Ivy Bridge Chips with 3D Transistors and 22nm Process

The giant chip maker Intel has finally released its 3ed generation chips named Ivy Bridge. They says that the new microprocessor chips used fundamentally different technology. These chips comes with 3D Transistors and are manufactured at 22nm process. The new technology will ensure high processing speed along with power saving. The chip makers keep the pace of Moore’s law by making the new chips using 3d transistor technology along with other advanced capabilities. We can hope that, customers will certainly welcome the new chip, because of the competence of it predecessors including the current Sandy Bridge chips. We know that transistors are the heart of processors and a microprocessor contains millions of it. Until today transistors were 2D (planar) devices, but Intel’s new Ivy Bridge chips comes with sophisticated 3D Tri-Gate Transistors. The new Ivy Bridge chips will power Gaming PC’s, Servers, Super Computers and all-in-one PC’s. We can hope that through this new line of chips, Intel will dominate in chip market with its major rival AMD. Now we will discuss some of the important features of the new Ivy Bridge chips. Ivy Bridge chips are relatively smaller and lighter in weight as it utilizes advanced technologies. The 3D Transistors these chips are lighter compared to transistors used in previous chips of Intel, through this Intel delivers the advantages of Moore’s law to its users. Intel has shrunk the Manufacturing technology of Ivy Bridge chips lower to 22nm because Intel notes that smaller chips are better in providing higher performance and higher efficiency. Intel says that in 2007 their CPU manufacturing process has changed to 45nm with high-k/metal gate, in 2009 to 32nm and now to 22nm with the world’s first 3-D transistor in a high volume logic process. Intel has made the new Ivy Bridge transistors in such a way that it can work efficiently even at lower voltages. Thus through this advanced sophisticated Ivy Bridge chips Intel strengthened its domination in global chip market and the company lifts up challenge not only to AMD but also to ARM holding the mobile chip market. Reference: KY32-NU80579EZ600CT KY32-NU80579ED009C
kynix On 2017-05-04 

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