Innovation for Every Engineer.

What is an FPGA? Design and Market Analysis



Basic Knowledge


Operating Principle


Product Comparison


1) Innovation: 1984-1992

2) Expanding age: 1992-1999

3) Optimizing age: 2000-2007

4) 4) System age: 2008-



Power Distribution Structure

Chip Structure

1. Programmable Input and Output Block

2. Configurable Logic Block (CLB)

3. Digital Clock Management (DCM)

4. Block Random Access Memory (BRAM)

5. Wiring Source

6. Underlying Built-in Function 

7. Special Built-in Hard Core

Fundamental Features


1) basic problem

2) Tools

3) Preparation

4) Practice

5) algorithm


World Famous FPGA Manufacturers

Design attention

Three Rules

Exchange of Area and Speed

Synchronous Design Principle

Quiescent Dissipation and Dynamic Power Comsumption


Market Development

Overview of Market

Overview of Development


A basic introduction to what Field Programmable Gate Arrays are and how they work, and the advantages and disadvantages.

FPGA (Field-Programmable Gate Array), it is the product of further development on the basis of PAL, GAL, CPLD and other programmable devices. It appears as a kind of semi-custom circuit in the field of application specific integrated circuit (ASIC). It not only solves the shortage of custom circuit, but also overcomes the shortcoming of limited number of gates in the original programmable devices.


The circuit design completed by hardware description language (Verilog or VHDL) can be tested on FPGA through simple synthesis and layout. It is the mainstream of modern IC design verification technology. These editable elements can be used to implement basic logic gates (such as AND, OR, XOR, NOT) or more complex combinatorial functions such as decoders or mathematical equations. In most FPGA, these editable components also contain memory elements such as flip-flop or other more complete memory blocks.

System designers can connect logic blocks inside the FPGA via editable connections, for example, a circuit test board be placed on a chip. The logical blocks and connections of a finished FPGA can be changed according to the designers, so FPGA can perform the required logical functions.

The FPGA is generally slower than the ASIC and performs the same function with more larger circuit area. But it also has many advantages, including it can be finished quickly with cheaper costs, and be modified to correct errors in the program. But sometimes vendors may also offer cheap but poor editing FPGA. Because these chips have poor editable ability, the development of these designs is done on the ordinary FPGA, and then the design is transferred to a chip similar to ASIC. Another way is to use CPLD (complex programmable logic device) to edit programs.

Operating Principle

FPGA adopts the concept of LCA (logic cell array), which includes three parts: CLB (configurable logic block), IOB (input output block), and interconnect. Field programmable gate array (FPGA) is a programmable device. Compared with traditional logic circuits and gate arrays (such as PAL, GAL and CPLD), FPGA has a different structure. FPGAs use a small look up table (16 × 1RAM) to implement combinatorial logic. Each look up table is connected to the input of a flip-flop D, which then drives other logic circuits or I / O. Thus the basic logic unit module which can realize the combinatorial logic function and the time sequence logic function synchronously. These modules are connected by metal wires to or connected to an I / O module. FPGA logic is achieved by loading programming data into internal static storage cells, therefore the program language stored in the memory cell determines the logical function of the logical unit and the party connected between the modules or between the modules and the I / O, and ultimately determines what FPGA can achieve, in addition, FPGA allows unlimited programming.


The development of FPGA is very different from that of traditional PC and single chip microcomputer. It is mainly based on parallel operation and is realized by hardware description language. There is a big difference between the sequential operation of a PC or a single-chip microcomputer (whether Von Neumann Architecture or Harvard Structure) compared with FPGA, so it is hard to design FPGA for the beginners. The design of FPGA is the process of developing FPGA chip by using EDA software and programming tools. Typical development processes generally include functional definition/device selection, inputting design, functional simulation, synthesis optimization, post-synthesis simulation, implementation, post-wiring simulation, board-level simulation, and chip programming and debugging.

FPGA is a programmable chip, so its design consists of two parts: hardware design and software design. The hardware includes FPGA chip circuit, memory circuit, I/O interface circuit and other equipment; the software is the corresponding HDL program and the embedded C program.

Product Comparison

As early as the mid-1980s, FPGA had taken root in PLD devices, and CPLD and FPGA included a relatively large number of editable logic units. Usually, the density of CPLD logic gates ranged from thousands to tens of thousands of logical units, while FPGA ranged from tens of thousands to millions.

The main difference between CPLD and FPGA is the system structure. CPLD has a somewhat restrictive structure. This structure consists of a logical group column of the sum of one or more editable results and a relatively small number of locked registers. The shortcoming is, it lacks of editing flexibility, but it has the advantages of predictable delay time and a high ratio of logical units to connected units. As for FPGA, however, has a lot of connection units, which makes it more flexible to edit, but much more complex in structure.

Another difference between the CPLD and the FPGA is that most of the FPGAs contain a high-level built-in module(such as an adder and a multiplier) and a built-in memory. Therefore, An important difference is that many new FPGAs support full or partial reconfiguration of the system, allowing their design to change with system upgrades or dynamic reconfiguration. Whta’s more, some FPGAs allow a portion of the device to be reedited and the other parts continue to work properly.

In addition, when the power-off of CPLD, the original written logic structure will not disappear, but it different for FPGA, the logic code in FLASH needs to be reloaded and the load time needs to be fixed when power on.


The original FPGA was used only for glue logic, from it to algorithmic logic to digital signal processing, high-speed serial transceivers and embedded processors. FPGA really changed from a supporting role to a leading role.

1) innovation: 1984-1992

In 1984, Xilinx XC2064, the world's first FPGA product, was born, contained only 64 logical modules, each containing two 3-input look up tables (LUT) and a register. According to current calculations, the device has 64 logic units-less than 1000 logic gates. Despite its small capacity, the size is very large, which larger than the microprocessors at the time. And it is barely able to produce when the device using 2.5-micron technology.

Xilinx XC2064

The chip size and cost is critical. The XC2064 has 64 flip-flops, but it costed hundreds of dollars because of the size of the chip at that time. Large wafers are big challenge for mass production, because a 5 percent increase in wafer size would double the cost, reduce the yield to zero, thus there is no product to sell at early stage of FPGA. To summery, cost control is not only reduce cost, but the optimization problem of products.

To change this situation, FPGA designers seek to maximize FPGA operation efficiency through architecture and process innovation to reduce cost. Although FPGA is programmable, on-chip SRAM accounts for most of the chip area of FPGA, so anti-fuse-based FPGA avoids the problem of large SRAM storage at the expense of reprogramming ability. In 1990, the maximum capacity of FPGA was Actel 1280 based on anti-fuse. After that, Quicklogic and Cross followed the step of Actel to develop an anti-fuse based FPGA. In order to increase efficiency, the architecture experienced the evolution from a complex LUT structure to a NAND gate and to a single transistor.

In this age, the number of FPGA is much smaller than the user's application products. With the time went by, automatic multi-chip partition software has become an important part of FPGA design suite, but automatic layout and routing is not yet available. And a completely different FPGA architecture excludes the possibility of universal design tools, so FPGA vendors have taken on the task of developing electronic design automation (EDA) for their devices. In addition, manual design is acceptable, and optimization is usually necessary because the chip limited wiring resources posed significant design challenges.

2) Expanding age: 1992-1999

FPGA start-up was a company which had no wafer factory, because FPGA was a new thing at that time. As a result of the fact that there was no wafer factory, they were usually unable to get the leading chip technology in the early 1990s. Therefore, the FPGA began the expanding time, which is lagging behind the development of the IC technology. By the late 1990s, the IC foundries realized that the FPGA was the ideal technique to promote factor development, and the FPGA became a sharp weapon to eliminate the technological development obstacles. And the foundries can produce the FPGA based on SRAM as long as the transistor and the electric wire can be produced by the new process. What’s more, the appearance of a new technique doubles the number of transistors, halves the cost per function, and doubles the size of the maximum FPGA. In addition, the chemical-mechanical polishing (CMP) technique allows more metal layers placed on the IC to increase the on-chip interconnect to accommodate a larger LUT capacity.

The footprint is no longer as valuable as in the era of invention. The point is performance and convenience. A larger FPGA design requires an integrated tool with an automatic layout routing function, by the end of the 1990s, automatic synthesis, layout and cabling had become a necessary step in the design process.

Most importantly, the easiest way to achieve capacity doubling and on-chip FPGAs was to use a new generation of process, so it was important to adopt new process as early as possible. The SRAM-based FPGA had a significant product advantage over this period, as they taken the lead in using each new process node: the SRAM-based device can immediately driven a new process with a higher density, while the anti-fuse needed several months or even years. The anti-fuse-based FPGA had lost the competitive advantage. To obtain that advantage of market and cost, process improvement and structural innovation had to be retreated in the second place.

3) Optimizing age: 2000-2007

At the beginning of the new millennium, the FPGA had become a general component in the digital system. With a rapid increase in capacity and design size, the FPGA has opened a huge market in the field of data communications. After the Internet bubble burst in the early 2000s, there is an urgent need to lower costs. And the custom chip is too risky for small R&D teams. When they find that the FPGA can solve their problems, they become FPGA users.

The FPGA issue is not limited to the common problem with a simple increase in capacity to ensure market growth. The FPGA vendor addressed this challenge in two ways: for low-end markets, manufacturers are re-concerned with efficiency to produce low-capacity, low-performance, cheap FPGAs, such as Xilinx Spartan FPGA family; for high-end markets, FPGA vendors try to make more convenient to fill the customer requirements by developing soft logic bases for critical functions. The most notable of it is the memory controller , various communication protocol modules( like Ethernet MAC).

The FPGA performance changed in the 2000s. Large FPGAs can accommodate very large designs (complete subsystems). FPGAs are not only meet the program logic, they also meet the system's standard requirements. These standards mainly refer to the communication standards in terms of signal and protocol, which can be used to connect external components or to implement internal module communication. The processing standard makes the FPGA play a more and more important role in computing-intensive applications. The FPGA is not only a gate array, but also a complex feature set with programmable logic.

4) System age: 2008-

To solve system design problem, the FPGA is increasingly integrate with the system modules (high-speed transceiver, memory, DSP processing unit and complete processor) and further integrates the important control functions(bit stream encryption and verification, mixed signal processing, power and temperature monitoring, and power management.). And these characteristics are fully reflected in the Zynq All-Programmable device. At the same time, the device has also promoted the development of the tool. For example, FPGAs require a high-efficiency system programming language, which is now available in the OpenCL and C languages in a similar software process to program.

FPGA Power

The FPGA power supply requires the output voltage range from 1.2V to 5V and the output current range from milliamps to amps. And three power supplies can be used: low dropout linear regulators (LDO), DC-DC switched regulators, and switched power modules. The final choice  will depend on the system, system budget, and time to market.

If board space is the primary consideration, low output noise is important, or the system requires a quick response to input voltage variations and load transients, the LDO regulator should be used. LDOs are less efficient (because they are linear regulators), only medium and low output current can be provided, and the input capacitor usually reduces the inductance and noise of the LDO input. The output of the LDO also needs the capacitor to address the transient of the system and maintain the stability of the system.

If efficiency is essential in the design, and the system requires high output current, the switched voltage regulator is dominant. The efficiency ratio of the switching power supply is higher than that of the LDO, but its switching circuit will increase the output noise. Different from LDO, switching voltage regulator needs inductor to realize DC-DC conversion.


To ensure proper power up, the slow rise time of the core voltage VCCINT must be within the manufacturer's prescribed range. For some FPGA, because the VCCINT will stay long before the transistor threshold is on, it may lead to a longer start current duration. If the power supply provides a large current to the FPGA, a longer power-up time will cause thermal stress.

Many FPGAs do not require timing control, so both VCCINT,VCCO and VCCAUX can be powered on at the same time. If this is not possible, the current can be slightly larger. Timing requirements vary according to specific FPGA. For some FPGA, both VCCINT and VCCO must be powered synchronously. For other FPGA, these power supplies can be switched on in any order. But in most cases, it is a good practice to supply the VCCINT first and then to the VCCO.

When the VCCINT is in the voltage range of 0.6V to 0.8V, some FPGA series will generate the surge current. During this period, the power converter continues to supply power. In this application, a return current limit is not recommended because devices need to limit current by lowering the output voltage. However, in the current-limiting power solution, once the current of the circuit supplied by the current-limiting power supply exceeds the rated current set, the power supply will limit the current lower than the rating value.

Power Distribution Structure

For high-speed and high-density FPGA devices, maintaining good signal integrity is critical to achieving reliable and repeatable designs. Proper power bypass and decoupling can improve global signal integrity. If decoupling is not sufficient, the logic conversion will affect the power supply and grounding voltage to affect the device work. In addition, the use of distributed power structure is also a major solution, during this process the power supply voltage offset can be can minimized.

In a conventional power supply configuration, the AC/ DC converter or DC/ DC converter is located in one place and provides a multi-output voltage that is distributed throughout the system. This design is known as a centralized power-supply architecture (CPA). When a low voltage is assigned with a high current, the copper wire or PCB track will generate resistance loss of power, affecting CPA.

The CPA's alternative is a distributed power-supply architecture (DPA). When DPA is used, only a semi-regulated DC voltage is allocated throughout the system, and each DC/ DC converter (linear or switched) is close to each load, so that the voltage drop caused by the line resistance and the wiring inductance is reduced. And this method of providing a local power source for a load is referred to as a load point (POL).

Chip Structure

Mainstream FPGA is still based on look up table technology, has far exceeded the basic performance of previous versions, and integrates common features (such as RAM, clock management and DSP). FPGA chips have seven main parts: programmable input/ output unit, basic programmable logic unit, complete clock management, embedded block RAM, rich wiring resources, embedded bottom functional unit and embedded special hardware module.

The functions of each module are as follows:

1. Programmable Input and Output Block

The programmable input/ output block is referred to as I/ O port. It is the interface part between the chip and the external circuit, which can drive and match the input/ output signals under different electrical characteristics. I/ O in FPGA is classified by group, and each group can support different I/ O standards independently. With the flexible configuration of the software, different electrical standards and I/ O physical characteristics can be met, the drive current can be adjusted, and the frequency of I/ O port of the and pull-up resistor and pull-down resistor can be changed, so that the frequency of the I/ O port can be higher and higher. Some high-end FPGA can support data rate up to 2Gbps through DDR register.

IOB Internal Structure Diagram

Fig 1. IOB Internal Structure Diagram

The external input signal can be read into the FPGA through the memory cell of the IOB module, or directly written into the inside of the FPGA. When the external input signal passes through the memory cell of the IOB module read into the inside of the FPGA, the requirement of hold time  can be reduced, which usually the windows default is 0.

In order to facilitate management and adapt to a variety of electrical standards, FPGA's IOB is divided into several banks, each bank interface standard is determined by its interface voltage VCCO, in addition, a bank can only have one VCCO, but each bank VCCO can be different. Only ports with the same electrical standard can be connected together, and the same VCCO voltage is the basic requirement of the interface standard.

2. Configurable Logic Block (CLB)

CLB is the basic logical unit within the FPGA. The actual number and characteristics of CLBs vary depending on the device, but each CLB contains a configurable switch matrix that consists of 4 or 6 inputs, some lectotype circuits (multiplexers, etc.) and flip-flops. The switch matrix is highly flexible and can be configured to work with combinational logic, shift registers, or RAM. In Xilinx's FPGA device, the CLB consists of multiple (usually 4 or 2) identical Slices and additional logic. Each CLB module be used to realize combinational logic and sequential logic, and it can also be configured as distributed RAM and distributed ROM.

Fig 2. CLB Structure Diagram

Slice is a basic logical unit defined by Xilinx. A Slice consists of two 4-input functions, carry logic, arithmetic logic, storage logic and function multiplexer. Arithmetic logic includes a  XORG and a MULTAND. XORG enables a Slice to implement the full operation of 2bit, and MULTAND improves the efficiency of multipliers. Carry logic consists of a dedicated carry signal and a function multiplexer for fast arithmetic addition and subtraction operations; 4-input functions generator is used to implement the 4-input LUT, distributed RAM or 16-bit shift register. Carry logic includes two fast carry chains to improve the processing speed of the CLB module.

Fig 3. Inputting Slice Structure Diagram

Fig 3. Inputting Slice Structure Diagram

3. Digital Clock Management (DCM)

Most of the industry's FPGA offer digital clock management. FPGA offers digital clock management and phase loop locking. Phase loop locking can provide accurate clock synthesis, reduce jitter and achieve filtering.

4. Block Random Access Memory (BRAM)

Most FPGAs have embedded block RAM, which greatly extends the applications and flexibility of the FPGA. The block RAM may be configured as a single-port RAM, a dual-port RAM, a content address memory (CAM), and a common storage structure such as a FIFO. CAM memory has a comparison logic in each of its internal memory cells, the data written into the CAM will be compared with each of the data in the interior, and the address of all data that is the same as the port data, so that there is a wide range of address switches in the route application. In addition to the block RAM, the LUT in the FPGA can be flexibly configured as a RAM, a ROM, and a FIFO. In practical application, that number of block RAM in the internal block of the chip is also an important factor in the chip selection.

The capacity of the monolithic RAM is 18k bits, that is, the bit width is 18 bits and the depth is 1024. It can change the bit width and depth according to the need, but two principles must be satisfied: firstly, the modified capacity (bit width depth) cannot be greater than 18k bits; Second, the maximum bit width cannot exceed 36 bits. Of course, it is possible to concatenate multiple blocks of RAM to form a larger RAM, which is limited only by the number of RAM blocks in the chip and is no longer constrained by the above two principles.

5. Wiring Source

All the parts are connected with wiring resources in the FPGA, and the length and process of the connection determine the driving ability and the transmission speed of the signal on the wire. There are abundant wiring resources in the FPGA chip, according to the process and length, width and distribution position, which are divided into 4 different categories. First is the global routing resource, which is used for the internal global clock and the global reset/ position routing. Second is the long line resource, which is used to complete the wiring of the high-speed signal and the second global clock signal between chip banks. Third is short-line resources, which are used to perform logical interconnection and cabling between basic logical units. Fourth is a distributed wiring resource, which is used as control signal lines for a proprietary clock or a reset.

In practice, the designer does not need to select the routing resources directly, and the layout scheduler can automatically select the better routing resources according to the topology of the input logical grid table and constraint conditions to connect each module unit. In essence, the use of routing resource types has a close and direct relationship with the results of the design.

6. Underlying Built-in Function 

The underlying built-in function mainly refers to a DLL (Delay Locked Loop), a PLL (Phase Locked Loop), a DSP, and a CPU, which belong to core softcore. The more and more built-in functional units make the single-chip FPGA a system-level design tool, so that it has the capability of joint design of hardware and software, and gradually turn to the SOC platform.

DLL and PLL have similar functions, such as high-precision clock and low jitter frequency doubling and frequency division, duty cycle adjustment and phase shift, etc. Xilinx integrated the DLL, Altera made the PLL, Lattice combined both two, which can be easily managed and configured through IP core-generated tools on Lattice's new chip. 

Fig 4. Typical DLL Module Schematics

7. Special Built-in Hard Core

The embedded special hard core is relative to the soft core embedded in the bottom, which means that the hard core with strong processing ability of FPGA is equivalent to the ASIC. To improve FPGA performance, chip manufacturers integrate some dedicated hard cores on the chip. For example, to improve the multiplication speed of FPGA, special multipliers are integrated in the mainstream FPGA, and in order to match the communication bus and interface standard, a lot of high-end FPGA are integrated SERDES, which can achieve the receiving and dispatching speed of  Gbps.

Fundamental Features

1) The ASIC circuit is designed by adopting the FPGA, and the user does not need to put the chip into production, so that a shared chip can be obtained.

2) FPGA can be used as a trial sample of other fully customized or semi-custom ASIC circuits.

3) There are rich flip-flops and I/ O pins within the FPGA.

4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the least risk among ASIC circuits.

5) FPGA adopts high-speed CMOS process, low power consumption, and can be compatible with CMOS and TTL.

It can be said that FPGA chip is one of the best choices for small batch system to improve system integration and reliability.

The working state of FPGA is set by the program stored in the on-chip RAM, so it is necessary to program the on-chip RAM when working. Users can use different programming methods according to different configuration modes.

When the power is on, the FPGA chip reads the data from the EPROM into the on-chip programming RAM. After the configuration is completed, the FPGA enters the working state. After power off, FPGA internal logic disappears. Therefore, FPGA can be programmed repeatedly. And the programming of FPGA does not require a special programmer, a general-purpose EPROM or PROM programmer can meet the requirement. When you need to modify the FPGA functionality, just replace a piece of EPROM. In this way, the same piece of FPGA, with different programming data, can produce different circuit functions. Therefore, the use of FPGA is very flexible.

Design Attention

1) basic problem 

The foundation of FPGA is digital circuit and VHDL language. In terms of language, it is suggested that beginners should learn Verilog language, VHDL language should be strictly regulated, debugging is slow, Verilog language is easy to use, and generally large enterprises use Verilog language. After getting familiar with it, you can study the VHDL language, it has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in tasks.

2) tools

Be familiar with a few commonly used and select the development environment Quartus II or ISE.  Using Modelsim for functional simulation, if you are a chip maker, you can learn from other simulation tools, because Modelsim is enough for FPGA design process. Synthesis tools generally use Synplify, but for beginners, using Quartus is good.

3) preparation

For beginners, especially from the software transfer, the design of the program is both resource-intensive and time-consuming, which requires us to be familiar with some fixed module writing. In learning FPGA development process, first of all, we should be familiar with circuit design and understand the working process of circuit and hardware programs.

4) practice

FPGA learning needs more practice and more simulation. SignaltapII is a good tool, you can see the real value of each signal, it is suggested that beginners must take more practice. As for the English documentation problem, if you want to learn all the functions of Quartus II well, the handbook is better. For the IT industry, most of the knowledge sources are English documents, it is necessary to pay more patience on them.

5) algorithm

The engineers in the field of FPGA, the algorithms is very important, if you are not prepared for the theory, the FPGA design can only stay at the primary stage. For beginners, digital signal processing is the foundation, which should be well understood, according to the direction you are engaged later, such as communication, image processing, radar, sonar, navigation positioning, etc.


FPGA has a variety of configuration modes: parallel master mode is a piece of FPGA plus one piece of EPROM mode; master-slave mode can support one piece of PROM to program multi-chip FPGA; serial mode can program FPGA by serial PROM; the peripheral mode can take FPGA as the peripheral device of microprocessor and be programmed by microprocessor.

How to achieve fast timing convergence, reduce power consumption and cost, optimize clock management and reduce the design complexity has always been a key issue for system engineers using FPGA. Today, as FPGA moves towards higher density, larger capacity, lower power consumption, and integration of more IP, system design engineers benefit from these excellent performance but also have to face the new design challenges brought about by the unprecedented performance and capability level of FPGA.

World Famous FPGA Manufacturers:

1. Altera (based on Quartus II)

2. Xilinx (based on ISE)

3. Actel (based on Libero)

4. Lattice (based on ISPLEVER)

5. Atmel

Design Attention

Whether you are a logic designer, a hardware engineer or a systems engineer, or even have all these titles, as long as you use FPGA, in any high-speed and multi-protocol complex system, you will most likely need to work hard to fix the device configuration, power management, IP integration, signal integrity and other key design issues. However, you don't have to face these challenges alone because application engineers working in the industry's leading FPGA companies can help you. And they have come up with some design guidelines and solutions that will make your design work easier.

Three Rules

Exchange of Area and Speed

The area here refers to the chip resources of FPGA, including logic resources and I/ O resources, etc; the speed here refers to the maximum frequency at which the FPGA works (unlike DSP or ARM, the working frequency of the FPGA design is not fixed, but closely related to the delay of the design itself). In practical design, using the minimum area to design the highest speed is the goal that every developer pursues, but both cannot be realized at the same time, so a reasonable design must be made according to the actual situation.

1) speed→area

Speed advantage can be exchanged for area savings. The smaller the area, the lower the cost of the product. The principle of speed change area is often used in some more complex algorithm design. Pipeline design is often a necessary technique in these algorithms. In pipeline design, these modules, which are reused but have different usage times, will consume a lot of FPGA resources. The design technology of FPGA is modified, and the reuse algorithm module is refined to minimize the reuse unit, and the minimum high speed is used to replace the reuse in the original design, but the number of times is different. Therefore, some other resources will inevitably be added to the process of transformation. However, as long as the speed has the advantage, the increased part of the logic can be able to achieve the purpose of reducing the area and increasing the speed. It can be seen that the key to the speed change area is the multiplexing of the high-speed base unit.

2) area→speed

In this way, the area of replication can be exchanged for a speed increase. The faster the speed, the higher the product performance. Some application fields that pay attention to product performance can use parallel processing technology to realize area conversion speed.

Hardware Realizable Principle

FPGA designs typically use HDL languages such as Verilog HDL or VHDL. When using HDL language to describe the function of a hardware circuit, it is necessary to make sure that the code is hardware-achievable.

The syntax of Verilog HDL language is similar to that of C language, but there are fundamental differences between them. C language is a high-level language based on procedure and can run on CPU after compilation, while Verilog HDL language itself is the hardware structure, after compiled is the hardware circuit. Therefore, there is no problem in the application of some statements in the environment of C language, but in the environment of HDL, the result will be incorrect or unsatisfactory.




There is no running problem in C language, but compiled in Verilog HDL environment will lead to serious waste of integrated resources.

Synchronous design Principle

The synchronous circuit and the asynchronous circuit are the two basic circuit structures of the FPGA design.

The biggest drawback of asynchronous circuits is that they produce burrs. The core circuit of synchronous design is composed of various flip-flops, and any output of this type of circuit is generated on the edge of a clock driven trigger. Therefore, synchronous design can well avoid burrs.

signal distribution

Versatile pins, I/ O standards, termination schemes and differential pair FPGA are the most complex design guidelines in signal distribution. Although Altera's FPGA device does not have design guidelines (because it is easy to implement), the FPGA design guidelines of Xilinx are complex. Whatever, there are some common steps should keep in mind when assigning signals to the I/ O pin:

1) Use a spreadsheet to list all planned signal allocations, as well as their important attributes, such as I/ O standards, voltages, terminating methods, and associated clocks.

2) Check manufacturer's block / zone compatibility standard.

3) Consider using the another spreadsheet to map out the layout of the FPGA to determine which pins are generic, which are dedicated, which support differential signal pairs and global and local clocks, and which require reference voltages.

4) By using the information and regional compatibility criteria of the above two spreadsheets mentioned, the most restricted signals are first assigned to the pins, and finally the least restricted ones are allocated. For example, you might need to assign serial bus and clock signals first, because they are usually assigned to specific pins.

5) Redistribute the signal bus to the restricted level. At this stage, you may need to carefully weigh design issues such as simultaneous switching output (SSO) and incompatible I/ O standards, especially if you have many high-speed outputs or use several different I/ O standards. If your design requires a local / regional clock, you will probably need to use pins near the high-speed bus. If the I/ O standard selected for a particular block requires a reference voltage signal, remember not to assign these pins first. Because differential signal allocation is always prior to single Terminal signal. If an FPGA provides on-chip termination, it may also apply to other compatibility rules.

6) Assign remaining signals properly.

At this stage, consider writing a HDL file that contains only port assignments. Then create a restriction file manually by using a vendor-supplied tool or using a text editor to add the necessary support information for the I/ O standard and SSO. Once these basic files are in place, you can run the layout tool to verify that some guidelines have been ignored or that a misallocation has been made.

CMOS-based design mainly consumes three types of power: internal (short circuit), leakage (static) and switching (capacitance). When the gate circuit transients, the short-circuit connection between the VDD and the ground consumes internal power. Leakage power is caused by parasitic effect in CMOS process. The switching power consumption is caused by discharge of self-loaded capacitor. Switching power consumption and short circuit power consumption together are called dynamic power consumption. The following is the way of reducing quiescent dissipation and dynamic power consumption .

quiescent dissipation 

Although the quiescent current is negligible compared to the dynamic current, the hand-held device powered by the battery is very important, especially when the device is powered on. The static current has a large number of factors, including the I/ O in the state where it is not fully turned off or on, the operating current of the internal transistor, the resistance of the internal connection, the pull-up or pull-down resistance of the input and the tri-state electric driver. In volatile technology, the retention of programming information also requires a certain amount of static power. The anti-fuse is a non-volatile technology so that the information store does not consume a quiescent current.

power consumption

1) The drive input should have a full voltage level so that all transistors are fully conductive or turned off.

2) Because the pull-up or pull-down resistors on the I/ O wires consume a certain amount of current, try to avoid the use of these resistors.

3) Less drive resistor or bipolar transistor, because these devices need to maintain a constant current, increasing the static current.

4) Connect the clock pins to the low level according to the parameters recommended by the table. In addition, suspended clock input will greatly increase static current.

5) Reduce the use of I/ O between devices when the design process is divided into multiple devices.

Note: The use of LP Pins for EX device

Actel's EX family has a special low-power "hibernation" mode. After the pin is driven to the high level 800ns, the device enters the very low power standby mode and the standby current is less than 100 μA. In low power mode, all I/ O (except clock input) are in three states, while the core system is completely powered off. When powered off, the information stored in the flip-flop is lost, and the user needs to initialize the device again when power on (after the pin is driven to a low-level 200ms). Similarly, the user should turn off all clock input via CLKA,CLKB and HCLK. Because the clock is not in three states, the clock can enter the device causing power consumption, so in low power mode, the clock input must be in logic 0 or logic 1.

Sometimes it is difficult for the user to prevent the clock from entering the device. On this occasion, the user can use the normal input pin adjacent to the CLKA and add the CLKINT. In this way, the clock will enter the device through the normal input near the clock pins, and then provide the clock resource to the device through the CLKINT.

With this input circuit, since the conventional I/ O is three-state, the user does not have to worry about the clock entering the device. Of course, adding a one-stage gate will result in a large clock delay for the 0.6ns, fortunately, this is acceptable in most low-power designs. Pay attention to that CLKA or CLKB pins associated with the CLKINT buffer should be grounded.

In addition, it is important to note that CLKINT can only be used as a connecting clock, and that HCLK does not have the ability to connect the internal wiring network to the HCLK, so the HCLK resource cannot be driven by conventional input. In other words, you can’t use HCLK and  LP pins synchronously. And you should truncate the clock signal externally when using HCLK.

reduce dynamic power consumption

Dynamic power consumption is the power consumption when the clock is working and input is on the switch end. For CMOS circuits, the dynamic power consumption basically determines the total power consumption. Dynamic power consumption consists of several components, mainly charge and discharge of capacitor load (internal and I/ O) and short circuit current. Most of the dynamic power is consumed by internal or external capacitors charging and discharging the device. If the device drives multiple I/ O loads, a large amount of dynamic current forms the main part of the total power consumption.

For a given driver in the design, the dynamic power consumption is calculated by the following formula.

p=CL×V 2 DD×f

The CL is the capacitor load, the VDD is the power supply voltage, and f is the switching frequency. Total power consumption is the sum of each driver's power consumption. Because the VDD is fixed, reducing the internal power consumption requires reducing the average logical switching frequency, reducing the total number of logical switches along each clock, and reducing the capacitance in the connected network, especially in the high frequency signal connection network. For low power design, preventive measures should be taken from the system to each design level of the process. The higher the level, the better the effect.


The discrimination and classification of FPGA and CPLD are mainly based on their structural characteristics and working principles. The usual classification is as follows:

Note: devices which constitute logical behavior in product structure are called CPLD, such as ispLSI series of Lattice, XC9500 series of Xilinx, MAX7000S series of Altera and Mach series of Lattice (original Vantis), etc.

The device that constitutes the logical behavior in the form of a look-up table method is called an FPGA, such as the SPARTAN series of Xilinx, the FLEX10K series or ACEX1K series of Altera, and so on.

Although both FPGA and CPLD are programmable ASIC devices with many common features, they have their own characteristics due to the differences in the structure of CPLD and FPGA.

1) CPLD is more suitable for various algorithms and combinatorial logic, while FPGA is more suitable for completing sequential logic. In other words, FPGA is more suitable for flip-flop-rich structure, and CPLD is more suitable for flip-flop-limited and product-rich structure.

2) The continuous routing structure of CPLD determines that its timing delay is uniform and predictable, while the segmented routing structure of FPGA determines the unpredictability of its delay.

3) When programming, FPGA is more flexible than CPLD. FPGA is programmed by modifying the logic function with fixed inner circuit, and FPGA is programmed by changing the wiring of internal connection. FPGA can be programmed under logic gate, while CPLD is programmed under logic block.

4) The integration of FPGA is higher than that of CPLD, and it has more complicated routing structure and logical implementation.

5) CPLD is more convenient to use than FPGA. E2PROM or FASTFLASH technology is used in the programming of CPLD, thus the external memory chip is not needed. The programming information of FPGA needs to be stored in the external memory, therefore, the method of using it is complicated.

6) CPLD is faster than FPGA and has greater time predictability. This is because FPGA is gate-level programming, and CLBs use distributed interconnection, while CPLD is logical block-level programming, and the interconnection between its logical blocks is aggregate.

7) In terms of programming, CPLD is mainly based on E2PROM or FLASH memory programming, and the number of programming can be up to 10, 000 times. Its advantage is that programming information is not lost when the system is powered off. CPLD can be divided into two types: programming on the programmer and programming in the system. Most of the FPGAs are based on SRAM programming, and the programming information is lost when the system is powered off, and every time the power is on, the programming information is lost when the system is powered off, and when the system is powered on, the programming information requires be written again on SRAM. Its advantage is that it can be programmed any time, and can be programmed quickly in the work to realize the dynamic configuration of board level and system level.

8) CPLD confidentiality is good, while FPGA confidentiality is poor.

9) In general, the power consumption of the CPLD is higher than that of the FPGA, and the higher the integration level is, the more obvious the power consumption will be.

Market Development

1) Overview of Market

When Xilinx created the FPGA in 1984, it was a simple glue logic chip, and now it has replaced ASIC and processors in signal processing and control applications.

Today, the semiconductor market has become a three-pronged trend: FPGA, ASIC and ASSP are as main three parts of the world. Market statistics show that FPGA has gradually eroded the traditional markets of ASIC and ASSP and is in a rapid growth stage.

In the global market, two major companies Xilinx and Altera still occupy the absolute monopoly position for the FPGA's technology. The two companies have nearly 90% of the market share, more than 6000 patents, and the monopoly is still strengthening. Therefore, the research and development of FPGA technology and products with independent intellectual property rights is of great significance to break the monopoly.

As a kind of programmable logic device, FPGA has evolved from the peripheral device of electronic design to the core of digital system in just more than two decades. With the progress of semiconductor technology, FPGA device design technology has made a leap forward development and breakthrough. According to the development process of FPGA devices, the following directions will still be developed in the future:

1) High density, high speed, wide band, high security

2) Low voltage, low power consumption, low cost, low price

3) IP soft / hard Core Multiplexing, system integration

4) Dynamic reconfigurable and monolithic cluster

5) Close combination of application needs, diversified development

In addition, integrated FPGA architecture, hard core CPU subsystem (ARM/MIPS/MCU) and other hard core IP chips have developed to a high level, thus it will be widely used in the coming decades, to provide more choices for system designers. For example, develop application-oriented seamless integration of specific functional modules into a patent-protected FPGA platform to create unique products with industry competitive advantages (cost-effective).

In the FPGA market, Xilinx and Altera have long held on to the first and second place. According to the latest Form-10K data, they possess 48% market share and 41% market share, respectively. Concretely, Xilinx had net sales of $2.31 billion and net income of $630 million, while Altera had net sales of $1.95 billion and net income of $780 million. The two companies dominate the FPGA market and technology, and the rest of the market has been dominated by Lattice.

To take the initiative in the competition, Xilinx and Altera recently announced that their next generation FPGA products will adopt 28nm high k metal gate technology to meet the growing bandwidth demand in areas such as cloud computing, mobile Internet and so on. Because PLD devices are manufactured with higher-tech process nodes, they can undoubtedly reduce costs and improve performance, especially to improve the power consumption level, which has been criticized by ASIC for a long time, to adapt to wider design applications.

Although Xilinx and Altera control nearly 90% of the world's FPGA market, most of their products are pure FPGA. "Platform" has become a developing trend of FPGA. Although Xilinx and Altera have also been involved in developing FPGA "platform" in recent years, the concept and characteristics are relatively simple, and complete idea has not been formed.

2) Overview of Development

1) circuit design

The connection logic and control logic are the most important field in the early part of the FPGA and the foundation of the application of the FPGA. In fact, the difficulty of applying the FPGA in the circuit design is still relatively large, which requires the developer to have the corresponding hardware knowledge (circuit knowledge) and the software application capability, because the premise of circuit design is to have certain hardware knowledge.

2) products design

Applying relatively mature technologies to specific areas such as communications, video, information processing, and so on, which is a key point to develop products that meet the needs of the industry and customers, in other words, this is mainly the combination of FPGA technology and professional technology. There are also interface problems with professional products and civilian products, the former focusing on performance, the latter is price-sensitive product design to achieve product functions as the main purpose. FPGA has the characteristics of interface, control, function IP, embedded CPU and so on to form a simple structure. The system product design with high curing degree and comprehensive function will be the most widely used in FPGA market.

3) system

The application at the system level is the combination of FPGA and traditional computer technology to realize a FPGA computer system, such as using Xilinx V-4, V-5 series FPGA to realize embedded POWER, PC, and CPU, meanwhile, cooperating with various peripheral functions to realize a basic environment. Running LINUX on this platform, this system can support a variety of standard peripherals and functional interfaces (such as image interface). This is very helpful for the rapid formation of large-scale FPGA system. 

Related News:

Mouser has signed a distribution agreement with Intel FPGA-based development board supplier ReFLEX CES.


Mouser has signed a distribution agreement with Intel FPGA-based development board supplier ReFLEX CES.

The online distributor will stock, the company’s Attilla, Alaric, and Achilles Arria 10 Instant Development Kits (IDKs).

The Arria 10 IDKs include the hardware, software design tools, and pre-verified test designs necessary to develop solutions based on Intel Arria 10 FPGAs and systems-on-chips (SoCs).

The Attila IDK is based on the Intel Arria 10 FPGA GX and is designed for high speed serial transceiver applications. The Atilla IDK comes equipped with an advanced memory interface with DDR4 SODIMM memory up to 16Gbyte, extension inputs and outputs, an on-board programmable PLL oscillator, and an eight-lane PCIe.

Network communications are developed using an RJ45 copper connector with 10/100/1000 Base-T Ethernet (through the RGMII PHY).

The Alaric IDK is based on Intel’s system-on-chip (SoC) FPGA technology, which integrates a dual-core ARM Cortex-A9 processor subsystem. It has DDR3 on-board memory up to 4Gbyte, a display output port for video and an eight-lane PCIe.

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