What Is Integrated Circuit and Its Uses (basic principle)



Video Expression

In this video we will discus about what is an ic , how it works , where to use them and can we even make one by ourself.


Catalog


Article Core

Integrated Circuit

Introduction

Definition

History

Development

Description of Integrated Circuits Labeling

Integrated Circuit Package Types

Acronym+Expressions

IC Types

IC Fabrication

Specific Packages Expression

Common Sense of Detection


Introduction


Integrated circuit (IC), also called microcircuit, microchip and chip, is a miniaturized way of  circuits (which mainly contains semiconductor devices) that can be machined on the surface of semiconductor wafers to produce various circuit element structures, in other words, it is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material. Therefore, it is also a general name for semiconductor component products, and it put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. Thus integrated circuits (ICs) are a keystone of modern electronics.

Integrated circuits, also called thin-film integrated circuits, which fabricated on the surface of a semiconductor chip, in addition, another thick-film hybrid integrated circuit is composed of independent semiconductor devices and passive components, which integrated into a substrate or circuit board to form a miniaturized circuit.

From 1949 to 1957, Werner Jacobi, Jeffrey Dummer, Sidney Darlington and Yasuo Tarui were all developed the different prototypes of integrated circuits. The first prototype of the integrated circuit was completed by Jack Kilby in 1958, it included a bipolar transistor, three resistors and a capacitor, and Kilby won the 2000 Nobel Prize in Physics for his part in the invention of the integrated circuit, in addition, his work was named an IEEE Milestone in 2009. Half a year after Kilby, Robert Noyce at Fairchild Semiconductor developed a new variety of integrated circuit, more practical than Kilby's implementation, Noyce credited Kurt Lehovec of Sprague Electric for the principle of p–n junction isolation, a key concept behind the IC, which helped to develop the modern practical integrated circuits.

After the invention and mass production of transistors, various solid semiconductor components, such as diodes and transistors, have been widely used to replace the vacuum tubes in circuits. By the mid-and late 20th century semiconductor manufacturing technology had advanced greatly, making it possible to develop integrate circuits. Compared to manually assembled circuits using individual discrete electronic components, integrated circuits can integrate a large number of microtransistors into a small chip, which is a huge advance. The modular mass-production, reliability, and modular circuit design ensures the standardized scale manufacture to replace using discrete transistors in design, which promotes the production efficiency.

Integrated circuits have two main advantages over discrete transistors: cost and performance. The lower cost is due to the fact that the chip uses photolithography technology to print all the components as a unit instead of making one transistor one by one at a time. Its high-performance is due to fast switching and lower energy consumption because the components are small and close to each other. In 2006, the chip area ranged from a few square millimeters to 350 mm2, and 1mm2 can hold 1 million transistors.

There are many kinds of integrated circuits in the market, up to now, there is no uniform standard for the designation of integrated circuit models in the world. Each manufacturer names the integrated circuits according to its own method. In general, many integrated circuits manufacturers put the acronyms of their company names or company product codes at the beginning of the model, followed by device number, package form and working temperature range and so on.

integrated circuit

ICs Package Types


Meanings of Common Letters 

C-ceramic

A mark representing a ceramic package. For example, CDIP represents a ceramic DIP.

H-with heat sink

It represents a tag with a heat sink. For example, HSOP represents a SOP with a heat sink.

P-plastic

A mark representing a plastic package. For example, PDIP means plastic DIP.

1. BGA (ball grid array)

The ball contact array, one of the surface mount packages. A spherical convex point is manufactured in an array manner on the back surface of the printed circuit board to replace a pin, an LSI chip is assembled on the front surface of the printed circuit board, and then a molding resin or a potting method is used for sealing, so it is also referred to as a convex point array carrier (PAC). The pins can exceed 200 and is a proper package for LSI. The package body can also be made smaller than the QFP (quad flat package). BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. 

The following are series of BGA family:

Acronym

Full Time

FBGA

Fine-pitch ball-grid array

LBGA

Low-profile ball-grid array

TEPBGA

Thermally-enhanced plastic ball-grid array

CBGA

Ceramic ball-grid array

OBGA

Organic ball-grid array

TFBGA

Thin fine-pitch ball-grid array

PBGA

Plastic ball-grid array

MAP-BGA

Mold array process - ball-grid array

μBGA

Micro ball-grid array

LFBGA

Low-profile fine-pitch ball-grid array

TBGA

Thin ball-grid array

SBGA

Super ball-grid array

UFBGA

Ultra-fine ball-grid array

2. BQFP (Bumpered quad flat-pack)

A four-side pin flat package with cushions, one of the QFP packages, a bulge (cushion) is arranged at the four corners of the package body to prevent the pin from bending during delivery.

3. Cerdip

Glass-sealed ceramic DIP is used for ECL RAM, DSP (Digital signal processor) and other circuits. It is also used for UVEPROM or microcomputer with EPROM.

4. Cerquad

One of the surface-mount packages, is used for the EPROM circuit. The heat-dissipation property is better than that of the plastic QFP, and the power of 1.5-2W can be allowed under the condition of natural cold air, but the packaging cost is 3-5 times higher than that of the plastic QFP. The  pin spacing has 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and so on, and the number of pins is from 32 to 368.

5. COB (chip on board)

Chip on board packaging is one of the bare chip-mount technology. Semiconductor chip is attached to the printed circuit board, and the electrical connection between the chip and the substrate is realized by the lead suture method, covered with resin to ensure reliability. Bare silicon chip, that is usually an integrated circuit, is supplied without a package.

6. DFP (dual flat package)

7. DIC (dual in-line ceramic package)

Nickname for ceramic DIP (including glass seals).

8. DIP (dual in-line package)

In microelectronics, a dual in-line package (DIP or DIL[1]), or dual in-line pin package (DIPP)[2] is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The packaging materials are plastic and ceramic. DIP is the most popular package, which includes standard logic IC, memory LSI, microcomputer circuit and so on. Pin spacing is 2. 54 mm, pin number from 6 to 64, the packaging width is usually 15.2mm. Some of the packages with width of 7.52mm and 10.16mm are called skinny DIP and slim DIP respectively. In addition, ceramic DIP sealed with low melting point glass is also known as cerdip.

The following are the acronyms of series of DIP family (they belong to through-hole packages)

Acronym

Full name

DIP

Dual in-line package

CDIP

Ceramic DIP

CERDIP

Glass-sealed ceramic DIP

SDIP

Skinny DIP

SDIP

Shrink DIP

MDIP

Molded DIP

PDIP

Plastic DIP

9. DIP (dual tape carrier package)

The name for DTCP from the Standard of Electronic Industries Association of Japan.

10. DIL (dual in-line)

It is the nickname for DIP. European semiconductor manufacturers often use this name.

11. DSO (dual small out-lint)

Dual small-outline package, the nickname for SOP, some semiconductor manufacturers use this name.

12. DICP (dual tape carrier package) 

Dual TCP, which pins are made on the insulating tape and drawn from both sides of the package. Due to the use of TAB technology, the package is very thin. It is often used in liquid-crystal display to drive LSI, but mostly are customized products.

13. FP (flat package)

One of the surface-mount packages. The nickname of QFP or SOP.

14. Flip-chip

One of the bare chip packaging techniques, fabricate metal bumps in the electrode area of LSI chip, and then connect the metal bumps to the electrode areas on the printed substrate. The occupied area of the package is basically the same as the chip size. Is the smallest and thinnest of all packaging types.

15. FQFP (fine pitch quad flat package)

Small pin spacing QFP. Usually refers to a QFP with the pin spacing less than 0.65mm. This name is used by some manufacturers of semiconductors.

16. CPAC (globe top pad array carrier)

The nickname of BGA from US Motorola Corporation.

17. CQFP (quad fiat package with guard ring)

QFP with protective ring. It is a plastic QFP, and pins masked with a resin protective ring to prevent bending deformation.

18. Pin grid arrays

It is a surface-mount PGA. In generally, PGA is usually a plug-in package with a pin length of about 3.4 mm. The surface-mount PGA has a display pin on the bottom of the package, and the length ranges from 1.5mm to 2.0mm. 

The following are the series of BGA family:

Acronym

Full Name

PGA(Also known as PPGA)

Pin-grid array

CPGA

Ceramic pin-grid array

FCPGA

Flip-chip pin-grid array

OPGA

Organic pin-grid array

19. LCC (Leadless chip carrier)

It is a surface-mount packaging where only has electrode contact but no pins in four sides. And it is high-speed and high-frequency IC packaging, also known as ceramic QFN or QFN-C.

The following are series of LCC family (a chip carrier is a rectangular package with contacts on all four edges.):

Acronym

Full Name

LCC

Lead-less chip carrier

LCC

Leaded chip carrier

LCCC

Leaded ceramic-chip carrier

CLCC

Ceramic lead-less chip carrier

DLCC

Dual lead-less chip carrier (ceramic)

PLCC

Plastic leaded chip carrier

20. JLCC (J-leaded chip carrier)

It is the nickname of CLCC with window and ceramic QFJ with window. The name adopted by some semiconductor manufacturers.

21. PLCC (plastic leaded chip carrier)

One of the surface-mount packages, with pins drawn from the four sides of the package. Texas Instruments was first used it in 64k-bit DRAM and 256k-bit DRAM, and it has been widely used in logical LSI, DLD in the 1990s.

22. P-LCC (plastic teadless chip carrier) (plastic leaded chip currier)

Sometimes it's a nickname for plastic QFJ, sometimes it's a nickname for QFN (plastic LCC). Some LSI manufacturers use PLCC to express lead packaging, and P-LCC to show on lead.

23. PCLP (printed circuit board leadless package)

Printed circuit board packaging without lead. The name used by Fujitsu Japan for plastic QFN (plastic LCC). Pin spacing: 0.55mm and 0.4mm.

24. LGA (land grid array)

There is array tantalum electrode contacts in the bottom, when assembling, it can be inserted into the socket.

25. LOC (lead on chip)

One of the LSI packaging, a structure in which the front end of the lead frame is located above the chip, and a convex spot is made near the center of the chip, which is electrically connected with a lead suture. The chip width contained in the same size package reaches 1mm.

26. LQFP (low profile quad flat package)

It means a kind of QFP with a 1.4mm(thickness) packaging body, and LQFP is the name used by the Electronic Industries Association of Japan according to the new QFP shape specification.

27. L-QUAD

It is one of the ceramic QFP. The thermal conductivity of aluminum nitride for packaging substrate is 7 ~ 8 times higher than that of alumina, so this packaging has good heat sink. The packaging frame is aluminum oxide and the chip is sealed by filling method, which reduces the cost. In addition, it is a kind of packages developed for logical LSI.

28. MCM (multi-chip module)

A package in which a number of semiconductor bare chipsets are mounted on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C and MCM-D. MCM-L is a component that uses a common glass epoxy multilayer printing substrate, in addition, the wiring density of it is not high and the cost is low. MCM-C is a kind of parts which using thick film technology to form multilayer wiring state, and the ceramic (alumina or glass ceramic) is used as the substrate material, which is similar to the thick film mixed IC using multilayer ceramic substrate. There is no obvious difference between these two. The wiring density of MCM-C is higher than MCM-L. MCM-D uses thin-film technique to make multilayer wiring with ceramic (alumina or aluminum nitride) as the substrates material.

29. MFP (mini flat package)

A nickname for plastic SOP or SSOP. The name adopted by some semiconductor manufacturers.

30. MQFP (metric quad flat package)

A classification of QFP according to the JEDEC memory standards. It is a standardized QFP with a pin spacing of 0.65 mm and a body thickness of 3.8mm~2.0mm.

31. MQUAD (metal quad)

Olin company of American develops this kind of QFP package. The substrate and seal-cover are made of aluminum. The power of 2.5W~2.8W can be allowed under the condition of natural air cooling.

32. MSP (mini square package)

The nickname of QFI, is known as MSP in the early stages of development. QFI is the name specified by the Electronic Industries Association of Japan.

33. OPMAC (over molded pad array carrier)

Moulded resin seal convex display carrier. The name for the moulded resin seal BGA from Motorola Corporation of the United States.

34. PAC (pad array carrier)

The nickname of BGA.

35. PFPF (plastic flat package)

The nickname of Plastic QFP. The name used by some LSI manufacturers.

36. PGA (pin grid array)

One of the plug-in packages in which the vertical pins on the bottom are arranged in a display form. The packaging substrate is basically using multilayer ceramic. In reality, most of the ceramic PGA. They are used in high-speed and large-scale logic LSI circuits, and the cost is high.

37. Piggy back

A ceramic package with a socket, is similar to DIP, QFP and QFN. When developing equipment with a microcomputer, it is used to detect program validation operations. For example, insert EPROM into a socket for debugging.

38. QFH (quad flat high package)

It is a kind of plastic QFP, in order to prevent the rupture of packaging body, the QFP body is thicker. The name adopted by some semiconductor manufacturers.

39. QFI (quad flat I-leaded packgac)

One of the surface-mount packages. The pin is drawn from the four sides of the package. Attach and printed substrate use butt welding connection. Because the pin has no protruding part, the mount occupied surface is less than QFP.

40. QFJ (quad flat J-leaded package)

One of the surface mount packages. The pin is drawn from the four sides of the package, down in J-shaped form. It is the name prescribed by the Electronic Industries Association of Japan. The pin spacing is 1.27mm.

It has plastic and ceramic materials. Plastic QFJ is called PLCC in most cases, for microcomputers, gate array, DRAM, ASSP, OTP circuits, etc.), number of pins from 18 to 84.

Ceramic QFJ, also known as CLCC or JLCC. The package with windows is used for UVEPROM and microcomputer chip circuit with EPROM, and number of pins are from 32 to 84.

41. QFN (quad flat non-leaded package)

One of the surface-mount packages. It is called LCC mostly in the late 1990s. QFN is the name prescribed by the Electronic Industries Association of Japan. The four sides of package have electrode contact, because of no pin, the area of mounting is smaller than QFP, and there are two kinds of materials: ceramic and plastic.

42. QFP (quad flat package)

One of the surface-mount packages, the pin is L-shaped from four sides. There are three kinds of substrate materials: ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the majority. The disadvantage of QFP is that when the pin spacing is less than 0.65mm, the pin is easy to bend.

43. QIC (quad in-line ceramic package)

The nickname for ceramic QFP. The name adopted by some semiconductor manufacturers.

44. QIP (quad in-line plastic package)

A nickname for plastic QFP. The name adopted by some semiconductor manufacturers.

45. QTCP (quad tape carrier package)

One of the TCP packages with pins on the insulating tape which draw from the four sides of the package. It is a kind of thin packaging that using TAB technology.

46. QTP (quad tape carrier package)

The name used by Electronic Industries Association of Japan in April 1993 for the shape specification of QTCP.

47. QUIL (quad in-line)

The nickname of QUIP.

48. QUIP (quad in-line package)

The pin is drawn from both sides of the package and bends down into four rows at alternate intervals. The pin spacing is 1.27 mm, and when inserted into the printed substrate, the insertion center distance becomes 2.5 mm. Therefore, it can be used in standardized printed circuit board. Is a smaller package than the standard DIP.

49. SDIP (Shrink dual in-line package)

One of the plug-in packages of the same shape as the DIP, but its pin spacing (1.778 mm) is smaller than that of DIP (2.54 mm). Pins quantity from 14 to 90, and its substrate material is available in both ceramic and plastic.

50. SH-DIP (Shrink dual in-line package)

It is same with SDIP. The name adopted by some semiconductor manufacturers.

51. SIL (Single in-line)

The nickname of SIP. European semiconductor manufacturers adopt this name.

52. SIMM (Single in-line memory module) 

A memory assembly with electrodes attached only to one side of the printed substrate. It usually means a plug-in component. Standard SIMM has 30-electrode with a pin spacing of 2.54 mm and 72-electrode with a pin spacing of 1.27 mm.

53. SIP (Single in-line package)

The pin is drawn from a side of the package and arranged in a straight line. When assembled on the printing substrate, the package is in a lateral position. Pin spacing is usually 2.54 mm, pin quantity from 2 to 23, and the related products are mostly customized.

54. SK-DIP (Skinny dual in-line package)

It is a kind of skinny DIP, with a body width of 7.62 mm and a pin spacing of 2.54 mm. It is usually referred to as DIP.

55. SMD (Surface mount devices)

Some semiconductor manufacturers will classify SOP as SMD at sometimes.

56. SOI (Small out-line I-leaded package)

One of the surface mount packages with I-shape pins. The pins lead down from both sides of the package in the shape of I with a pin spacing of 1.27 mm and surface-mount area is less than the SOP.

57. SOIC (Small out-line integrated circuit)

The nickname of SOP. Many semiconductor manufacturers at abroad adopt this name.

58. SOJ (Small Out-Line J-Leaded Package)

One of the surface-mount packages with J-shape pins. The pins lead down from both sides of the package in the shape of J, they are usually plastic. It mostly used for memory LSI circuits such as DRAM and SRAM, but most are DRAM.

59. SQL (Small Out-Line L-leaded package)

The name used for SOP in accordance with the JEDEC(Joint Electron Device Engineering Council) memory standards.

60. SONF (Small Out-Line Non-Fin)

It is the same as the usual SOP, but without the radiator. In order to express the difference of no radiator in power IC package, NF (non-fin) mark is added intentionally to distinguish. The name adopted by some semiconductor manufacturers.

61. SOP (Small Out-Line package)

One of the surface-mount packages in which the pins are drawn from both sides of the package in the form of L-shape. There are plastic and ceramic substrate materials. In addition, it's also called SOL and DFP.

It is used for the memory LSI, also widely used for small-scale circuits such as ASSP.

62. SOW-Small Outline Package(wide-jype)

A kind of wide-jype SOP. The name adopted by some semiconductor manufacturers.

Integrated Circuits


The Development of Integrated Circuits


The most advanced integrated circuits are the core of a microprocessor or multi-core processor that controls everything from a computer to a mobile phone, even a digital microwave. Although the cost of designing and developing a complex integrated circuit is very high, applying it on the market can generate huge profit. The performance of integrated circuits is very high, because small size brings short path, making low power logic circuits applied to fast switching speed.

With the development, integrated circuits have continued to grow to become more smaller, allowing each chip to package more circuits. This increases capacity per unit area, reducing costs and increasing functionality. In short, with the reduction of shape size, almost all of the indicators improved, in general, unit cost and switching power consumption decreased, and speed increased. However, integrated circuit also has problems, for example, IC integrated with nano-level devices will leak. This will increase the power consumption and decrease the operation efficiency. As a result, the IC has made a great process to improve the electronics industry and electrical devices, and meanwhile, it has still new problems to solve.

Only half a century after its development, integrated circuits became popular and ubiquitous. It becomes an indispensable part of the social life, such as computers, mobile phones and other digital appliances. This is because modern computing, communication, manufacturing and transportation systems are all depend on integrated circuits. In this case, many scholars believe that the digital revolution brought about by integrated circuits is the most important event in human history. The huge development of IC will bring about a great leap forward in modern technology, this is not only the great process in design technology or in semiconductor technology but for more high-level technical fields. 


Types


There are many ways to classify integrated circuits.

According to Transmission

It can be divided into: analog integrated circuit, digital integrated circuit and mixed signal integrated circuit.

Digital integrated circuits can contain anything, with logic gates, flip-flops, multitasking and other circuits that range from thousands to millions of millimeters in a few square millimeters. Although these circuits have small size, they can allow for higher speed, lower power consumption and lower manufacturing costs than board level integration. These digital IC, represented by microprocessors, digital signal processors and microcontrollers, use binary to process “1” and “0 “ signals.

Analog integrated circuits include sensors, power control circuits and operational amplifiers and so on to process analog signals. Generally, it can complete amplification, filtering, demodulation, mixing function and so on. By using analog integrated circuits, the burden of circuit designers is lightened, and it is not necessary to design everything from one transistor to another.

Integrated circuits can integrate analog and digital circuits into a single chip to make devices such as analog to digital converters or digital to analog converters. It has smaller sizes and lower costs, but needed to pay more attention to signal conflicts.

According to Application

Integrated circuits can be divided into standard general integrated circuits and special integrated circuits according to their application fields.

According to Shape

Integrated circuits can be divided into circular (metal transistor package, generally suitable for high power), flat (good stability, small size) and dual in-line type according to the shape.

The practical categories are as follows:

1. Television integrated circuits include line, field scanning integrated circuit, intermediate amplifier integrated circuit, audio integrated circuit, color decoding integrated circuit, AV/TV conversion integrated circuit, switching power supply integrated circuit, remote control integrated circuit, NICAM decoding integrated circuit, picture-in-picture processing integrated circuit, CPU, memory integrated circuit and so on.

2. Audio integrated circuits include AM/FM high-frequency circuit, stereo decoding circuit, audio preamplifier circuit, audio operation amplifier integrated circuit, audio power amplifier integrated circuit, surround sound processing integrated circuit, level drive integrated circuit, electronic volume control integrated circuit, delay reverberation integrated circuit, electronic switch integrated circuit and so on.

3. The integrated circuits used in video players include systematic control integrated circuits, video coding integrated circuits, MPEG decoding integrated circuits, audio signal processing integrated circuits, sound effect integrated circuits, RF signal processing integrated circuits, digital signal processing integrated circuits, servo integrated circuit, motor drive integrated circuit, etc.

4. VCR integrated circuits have system control integrated circuit, servo integrated circuit, driving integrated circuit, audio processing integrated circuit, video processing integrated circuit.

5. Integrated circuits in computer, including CPU, internal memory, external memory, I /O control circuit and so on.

6. Communication integrated circuit.

7. Special control integrated circuit.


IC Fabrication


Intergrated circuit

Since the 1930s, chemical-element semiconductors have been considered by researchers such as William Shockley of Bell Labs as the most likely raw materials for solid vacuum tubes. Materials from copper oxide to germanium to silicon were systematically studied from 1940s to 1950s. Today, while some III-V valence compounds such as gallium arsenide are used for special applications such as LED, lasers, solar cells and the most high-speed integrated circuits, only monocrystalline silicon has become the mainstay of integrated circuits. The method of creating defect-free crystals has a long way to go.

Integrated circuit processes of semiconductors includes the following steps:

Photolithography

Etching

Thin Film (Chemical vapor deposition or physical vapor deposition)

Doping (Thermal diffusion or ion implantation)

Chemical Mechanical Planarization (CMP)

The monocrystalline silicon wafer (or III-V family, such as gallium arsenide) is used as the substrate, then the components such as MOSFET or BJT are fabricated by photolithography, doping, CMP method and so on, and then the conductive paths are made by using thin film and CMP technology, repeating these processes, the chip is fabricated finally. Due to performance requirements and cost considerations of the product, conductive paths can be made by aluminum process (mainly splashing) and copper process (mainly electroplating). The main process can be divided into the following categories: photolithography(yellow light), etching, diffusion, film, flatting, metallization.

IC consists of multilayers, each defined by video technology, represented by different colors. Some layers indicate where is the diffusion layer, that is, different dopants diffuse into what layers; some definitions where is the instillation layer, means where needed additional ion instillation; some indicate where is the polycrystalline silicon or metal layer, which belongs to conductors; some define where is through holes or contact layers, that is connections between conductive layers. They are important, because all components consist of a specific combination of these layers.

In a CMOS process, all gate layers (polysilicon or metals) pass through the diffusion layer to form transistors.

Resistor structure: the ratio of length to width of resistor, combined with surface resistivity to determine resistance.

Capacitor structure: due to size limit, IC can only produce very small capacitance.

Rarer inductor structure can be made of on-chip inductors or simulated gyrotron.

Because CMOS devices only guide currents to transfer in logic gates, it consume much less current than bipolar components such as bipolar transistors. Through the design of the circuit, many transistor tubes can be painted on the silicon wafer, and the integrated circuits with different functions can be drawn.

RAM is the most common type of integrated circuit, even the microprocessor has memory. Despite the complexity of the chip structure, and its widths have been shrinking for decades, the layers of integrated circuits are still much thinner than their widths. The component layer is made much like a photographic process. Although visible spectrum light waves cannot be used to expose component layers because they are too large, high-frequency photon, ultraviolet are usually used to create patterns for each layer. In addition, each feature of layers is very small, electron microscopy is a necessary tool for a process engineer who is debugging the manufacturing process.

Each device is tested before ATE packaging is used. The testing process is called wafer testing or wafer probing. Wafers are cut into rectangular blocks, which called "die". Each good die is welded to aluminum or gold wires on the "pads", connected to the package. After packaging, the device is detected by the ATE device in wafer testing. The test cost can reach 25% of the manufacturing cost of a low-cost product, but is negligible for high cost equipment.

Whole Fabrication Process Overview

The whole process of a chip includes chip design, chip fabrication, package fabrication, testing and so on, among them chip fabrication is the most difficult.

First of all, the chip design, according to the design requirements to draw diagram.

Chip Wafer

The composition of the wafer is silicon(refined by quartz sand). The wafer is purified by the silicon(99.999%), and then the pure silicon is made into a silicon crystal rod, which is used as a quartz semiconductor material for the manufacture of integrated circuits. Finally, slicing it is making the specific required wafer. The thinner the wafer, the lower the cost of production, but this requires high-level technique.

Wafer Coating

Wafer coating can resist oxidation and level temperature resistance, in addition, it is a kind of photoresistance.

Wafer Photolithography and Etching

The basic process of photolithography. First, coat a layer of photoresist on the wafer (or substrate) surface and dry. The dried wafer is transmitted to the photoetching machine. The pattern of the mask is projected onto the photoresist of the wafer surface by a mask to expose the light and excite the photochemical reaction. After exposure, the wafer needed to drying again, this process makes a complete photochemical reaction. Finally, the developer is sprayed on the photoresist on the wafer surface to develop the exposure pattern. After developed, the pattern on the mask is left on the photoresist. In addition, coating, baking and developing are done in a leveling machine, while exposure is done in aphotoetching machine. The whole exposure development system is closed and the wafer is not directly exposed to the surrounding environment in order to reduce the influence of harmful factors in the environment on photoresist and photochemical reaction.

The process uses UV-sensitive chemicals. The shape of the chip can be obtained by controlling the position of the shading object. The silicon wafer is coated with a photoresist, which will dissolve in ultraviolet light and can be washed away by solvent. The rest is the same shape as the shading, in this way we get the silica layer we need.

Admixture Impurity

The ions were implanted into the wafer to form the corresponding P-based and N-based semiconductors. First, the exposed silicon wafer put into the chemical ion mixture, and this process will change the way in which the dopant region conducts electricity, allowing each transistor to turn on or carry data. A simple chip may have only one layer, but a complex chip usually has many layers. At this time, this process is repeated and the different layers can be connected by opening a window, which is similar to the production principle of multilayer PCB board. A more complex chip may require more than one silica layer, which needed repeat the above processes to form a requiring chip structure.

Wafer Test

After several processes above mentioned, grid grains are formed on the wafer. The electrical properties test of each grain is necessary. Generally, each chip has a large number of grains, and organizing a accuracy detection is a very complex process, which requires mass production of as many models as possible with the same chip specifications. Therefore, the larger the quantity, the lower the relative cost, which is one of the reasons for the low cost of mainstream chip devices.

After the fabrication of the wafer is finished, the pin is fixed necessarily. Because different packaging forms are made based on the requirements, which is why the same chip core can have different packaging forms, such as DIP, QFP, PLCC, QFN and so on. This is mainly determined by the user's application, applying environment, market state and other peripheral factors.

Testing | Packaging

After the above process, the chip production has been completed, the following step is to talk about packaging.

The earliest integrated circuits used ceramic flat packages, which for many years continued to be used by the military for its reliability and small size. The commercial circuit packaging is a dual row straight package, starting with ceramics, then plastic. In the 1980s, the pins of VLSI(very-large-scale integration) circuits exceeded the applying limits of DIP packaging, resulting in the emergence of pin grid arrays and chip carriers.

Chip carriers may have either J-shaped metal leads for connections by solder or by a socket, or may be lead-less with metal pads for connections. If the leads extend beyond the package, the preferred description is “flat packaging”. Chip carriers are smaller than dual in-line packages and since they use all four edges of the package it can have a larger pin count. Chip carriers may be made of ceramic or plastic. Some forms of chip carrier package are standardized in dimensions and registered with trade industry associations such as JEDEC. Other forms are proprietary to one or two manufacturers. Sometimes the term chip carrier is used to refer generically to any package for an integrated circuit.

Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs), it is emerged in the early 1980s, which became popular in the late 1980s. An electronic device so made is called a surface-mount device (SMD). In industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board, with the through-hole technology used for components not suitable for surface mounting such as large transformers and heat-sinked power semiconductors.

surface-mount tech

It uses finer pin spacing and pins are shaped as gull wing or J-shaped. Take Small-Outline Integrated Circuit (SOIC) as an example, 30%-50% less than equal DIP area, 70% less thickness. In 1990s, although PGA packaging is still used in high-end microprocessors, PQFP and TSOP(thin small-outline package) become the usual packaging for high-pin devices. The high-end microprocessing of Intel and AMD are now moving from PGA (pine grid arrays) packaging to LGA (land grid arrays) packaging.

The ball grid arrays(BGA) package began to use in the 1970s, and in the 1990s, it was developed with more pins than any other package. In FCBGA packaging, the die is flipped up and down to install. These are amazingly intricate little packages where little balls of solder are arranged in a 2-D grid on the bottom of the IC. Sometimes the solder balls are attached directly to the die! BGA packages are usually reserved for advanced microprocessors. FCBGA packages enables input and output signal arrays (known as the I/O region) to be distributed across the surface of the chip, rather than being confined to the periphery of the chip. With the development, packaging technology will also affect product quality and yield strongly. 


Common Sense of Detection


1. Before testing, we should understand the working principle of integrated circuit and its related circuits.

Before checking and repairing the integrated circuit, we should be familiar with the IC function, the internal circuit, the main electrical parameters, the function of each pin, the normal voltage of  pins, frequency waveform and peripheral components.

2. When testing, do not cause short circuit between pins.

When measuring voltage or measuring waveform with oscilloscope probe, avoid short circuit between pins. It is best to measure it on peripheral printed circuit directly connected with pin. Any instant short-circuit can easily damage integrated circuit devices, especially when testing flat CMOS ICs needed greater care.

3. It is strictly prohibited to contact equipment without isolating transformers.

For example, when it comes into contact with special television or audio equipment, especially those with higher output power or less knowledge of the nature of the power used, it is necessary to ascertain whether the chassis of the machine is power-on, otherwise, it is easy to cause short circuit of power supply, and cause further expansion of fault with live TV, audio and other equipment on the backboard.

4. Pay attention to the insulation performance of electric soldering iron.

Soldering is not allowed when power on. It is best to grounding the shell of the soldering iron. For example, to the MOS circuit, it is safer to use a low voltage soldering iron with 6V to 8V.

5. Ensure welding quality

When welding, solder accumulation and porosity are easy to lead to improper welding. Welding time is not more than 3 seconds, the power of soldering iron is 25W or so. The welded integrated circuit should be carefully checked. It is best to measure the short circuit between the pins with ohmmeter, and confirm that there is no bonding between solder and switch on the power.

6. Do not easily judge the damage to the integrated circuit.

Don't judge easily that the integrated circuit is damaged. Because the vast majority of integrated circuits are directly coupled, once a circuit is not normal, it can lead to multiple voltage changes that are not necessarily caused by integrated circuit damage. In addition, in some cases, the pin voltage is in accordance with or close to the normal value, which doesn’t mean the IC is good. Because some small faults do not cause DC voltage changed.

7. The internal resistance of the test instrument should be large.

When measuring DC voltage of IC pins, the multimeter is better more than 20KΩ /V, otherwise, there will be a great error in measuring some pins voltages.

8. Pay attention to the heat dissipation of power integrated circuits.

Power integrated circuits should have good heat dissipation and are not allowed to work in high power without radiators.

9. Lead layout should be reasonable.

If it is necessary to add peripheral elements to replace damaged parts inside the integrated circuit, small components should be used, and the wiring should be reasonable to avoid unnecessary parasitic coupling. Especially to deal with the earthing end between the audio power amplifier integrated circuit and the preamplifier circuit.


Related News:


sensor 

Elementary particle strip sensor with a size of 15 cm x 10 cm in the center of the wafer.

Ninety-five percent of the universe is still considered unexplored. Scientists at CERN, the world's largest particle physics research center, located in Geneva, are working on solving these mysteries. In May 2012, researchers there discovered the so-called Higgs Boson, whose prediction won Peter Higgs and François Englert the Nobel prize in physics. One of the things CERN scientists are researching at the moment is dark matter: Although it may well have five times the mass of visible matter in the universe, this extent can only be indirectly proved. With a bit of luck, CERN will also succeed in generating dark matter.

A unique sensor chip can contribute to proving the existence of dark matter: It is eight inches or 15 cm x 10 cm and was developed jointly by Infineon Technologies Austria and the Austrian Academy of Sciences' Institute of High Energy Physics (HEPHY). Tens of thousands of these silicon components could be used at CERN in the near future. They are not only more economical to produce than previous sensors, which measured up to six inches. The components also stand up better to constant radiation and thus age slower than the previous generation. Planned experiments will scarcely be possible without resistant sensors.

The experiments at CERN are analyzing the structure of matter and the interplay among elementary particles: Protons are accelerated almost to the speed of light and then made to collide, giving rise to new particles whose properties can be reconstructed with various detectors. "In particle physics and cosmology, there are many questions that are still open and to which mankind still has no answer," says Dr. Manfred Krammer, head of the Experimental Physics Department at CERN. "To make new advances in these areas, we need a new generation of particle sensors. Cooperation with high-tech companies like Infineon allows us to develop the technologies we need for that."

     Elementary particle strip sensor with a size of 15 cm x 10 cm. Credit: Infineon Technologies Austria AG

As tall as an apartment building and 100 meters below ground

Two of the detectors for which the use of the Infineon specialized sensors is currently being tested are named ATLAS (A Toroidal LHC Apparatus) and CMS (Compact Muon Solenoid). Particle physics experiments are huge cameras: When particles penetrate the silicon detectors, it registers them. With twenty meters (ATLAS) respectively fifteen meters (CMS) height both experiments are located 100 meters below ground. They have been in almost round-the-clock operation for years, carrying out 40 million individual experiments each second. The two sides are currently discussing possible production of chips with a total area of up to 1,000 m².

But researchers need a great deal of persistence. "It may take generations for the basic research to change everyday life," says Andreas Urschitz, head of the Power Management & Multimarket Division at Infineon Technologies AG. "That mustn't keep people from research. Without Marie Curie, we wouldn't have the X-ray, and without Maxwell, we wouldn't have cell phones." Marie Curie coined the term "radioactivity" in 1898. James Clerk Maxwell's equations, with which the Scottish physicist described electromagnetism between 1861 and 1864, are already 150 years old.

The technology developed for CERN could help cancer patients in less than ten years: Several groups of researchers are currently testing proton computed tomography. The medical imaging procedure is based on the same fundamentals as the chip technology for CERN. Large silicon detectors like the ones Infineon and HEPHY are developing could supply tomographic images during therapeutic radiation. This would better determine the position of the tumor, allowing less damage to be done to healthy tissue than is possible with conventional X-rays. It would reduce the radiation load by a factor of 40.

sensor chip

                    One end-cap of the CMS tracker is opened during installation work.

sensor chip

First half of CMS inner tracker barrel.

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