CTS Electrocomponents 208-3

Description

The LIBERATOR™ CL1K family offers you all of the time-to-market benefits of designing with programmable logic. Simply use Altera ACEXfi 1K FPGAs to prototype and verify the design. Then, take five minutes to submit the bitstream using Clear Logic’s web site! Within eight weeks, your system can be in volume production using compatible Clear Logic devices.
LIBERATOR technology frees you to completely design, prototype, and verify your custom logic using Altera ACEX 1K products. Clear Logic’s innovative technology eliminates NRE costs, test vector development, ordering minimums, and long lead times. No re-simulation or re-layout is required, because Clear Logic offers an architecture that is exactly compatible to the functionality of the FPGA prototype. Clear Logic’s NoFaultfi test technology ensures complete test coverage through the use of special scan test registers.
The LIBERATOR family is based upon an array of logic elements. Each logic element contains a configurable look-up table for combinatorial functions and a register for sequential operations. Eight logic elements in a group form a block. Logic functions and signal routing are defined by Clear Logic’s proprietary vertical metal links.
Laser-based configuration allows quick-turn prototyping and eliminates NRE costs for photomasks. Inherent CL1K family performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events.

Key Features

♦ Fully Compatible to the Alterafi ACEXfi 1K Family
♦ Prototype Your System With Altera FPGAs
♦ Seamlessly Migrate Production To Clear Logic
♦ No ASIC Engineering, No NRE, And No Test Vector Development
♦ Very Fast, Dense Signal Routing Using Vertical Link Interconnect
♦ "Gate Array" Option Eliminates Configuration EPROMs
♦ Fabricated Using 0.35 Micron CMOS Process
♦ Very Low Power Consumption (Active And Standby)
♦ High Density
- 50,000 Usable Gates
- 2,880 Logic Elements
- 40,960 RAM Bits
- 249 Maximum User I/O Pins