Phone

    00852-6915 1330

W25Q128FVFIG Serial Flash Memory: Block Diagram, Datasheet, Features [Video&FAQ]

  • Contents

Catalog

Product Overview

W25Q128FVFIG Related Video Introduction

W25Q128FVFIG Pin Configuration

W25Q128FVFIG Block Diagram

W25Q128FVFIG Features

W25Q128FVFIG SPI / QPI Operations

W25Q128FVFIG Datasheet

W25Q128FVFIG Specifications

W25Q128FVFIG Manufacturer

Using Warning

W25Q128FVFIG FAQ

Product Overview

The W25Q128FV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI(XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in spacesaving packages.

 

The W25Q128FV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128FV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage.

 

The W25Q128FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.

 

A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.

 

W25Q128FVFIG Video Description: In this video, I am going to explain how Flash Memory and Solid-state drives (SSD) work! Have fun, get some popcorn and enjoy!

 

Everybody stores pictures, music, and videos on their devices nowadays. The encoded information is even stored when the device shuts down due to low energy. After powering it on again, we find the same media and are glad that it did not disappear.

 

Flash memory was invented in 1984 by Japanese engineer Fujio Masuoka at the Toshiba Corporation. An electrical storage medium that does not require any energy to retain data. The name "Flash" was suggested by a coworker of Masuoka, Shoji Ariizumi because the erasure process of the newly invented device reminded him of a camera's flash. Later, the invention of flash memory allowed the wide use of solid-state-drives (SSD) that most of us have in their computers today.

 

The fundamental building block of flash memory is the floating-gate MOSFET, in short, FGMOS. Dependant on the kind of used technology, flash cells can store one or up to four bits (single-level cell (SLC) = 1 bit; multi-level cell (MLC) = 2 bits; triple-level cell (TLC) = 3 bits; quad-level cell (QLC) = 4 bits) - five bits per cell (penta-level-cell (PLC) = 5 bits) is in development currently. In a nutshell, these memory cells are arranged right next to each other and layered on top of one another to realize a highly capable storage medium. This makes it possible to produce a chip with trillions of flash cells, which then can store up to 1 TB of data! A perfect SSD! Flash memory is amazing and you know what? Engineers and semiconductor manufacturers will continue to shrink the size of flash cells in order to improve storage capacity and to reduce the price per bit. Therefore creating even better technology and cheaper solid-state-drives (SSDs) in the future!

 

W25Q128FVFIG Pin Configuration

W25Q128FVFIG Pin Configuration

Figure: W25Q128FVFIG Pin Configuration

Pin Description

PIN NO. PIN NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)
2 VCC   Power Supply
3 /RESET I Reset Input
4 N/C   No Connect
5 N/C   No Connect
6 N/C   No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)
10 GND   Ground
11 N/C   No Connect
12 N/C   No Connect
13 N/C   No Connect
14 N/C   No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)
16 CLK I Serial Clock Input

 

W25Q128FVFIG Block Diagram

W25Q128FVFIG Block Diagram

Figure: W25Q128FVFIG Block Diagram

 

W25Q128FVFIG Features

  • New Family of SpiFlash Memories

– W25Q128FV: 128M-bit / 16M-byte

– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold

– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold

– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

– QPI: CLK, /CS, IO0, IO1, IO2, IO3

– Software & Hardware Reset

  • Highest Performance Serial Flash

– 104MHz Single, Dual/Quad SPI clocks

– 208/416MHz equivalent Dual/Quad SPI

– 50MB/S continuous data transfer rate

– More than 100,000 erase/program cycles

– More than 20-year data retention

  • Efficient “Continuous Read” and QPI Mode

– Continuous Read with 8/16/32/64-Byte Wrap

– As few as 8 clocks to address memory

Quad Peripheral Interface (QPI) reduces instruction overhead

– Allows true XIP (execute in place) operation

– Outperforms X16 Parallel Flash

  • Low Power, Wide Temperature Range

– Single 2.7 to 3.6V supply

– 4mA active current, <1µA Power-down (typ.)

– -40°C to +85°C operating range

  • Flexible Architecture with 4KB sectors

– Uniform Sector/Block Erase (4K/32K/64K-Byte)

– Program 1 to 256 byte per programmable page

– Erase/Program Suspend & Resume

  • Advanced Security Features

– Software and Hardware Write-Protect

– Power Supply Lock-Down and OTP protection

– Top/Bottom, Complement array protection

– Individual Block/Sector array protection

– 64-Bit Unique ID for each device

– Discoverable Parameters (SFDP) Register

– 3X256-Bytes Security Registers with OTP locks

– Volatile & Non-volatile Status Register Bits

  • Space Efficient Packaging

– 8-pin SOIC / VSOP 208-mil

– 8-pin PDIP 300-mil

– 8-pad WSON 6x5-mm / 8x6-mm

– 16-pin SOIC 300-mil (additional /RESET pin)

– 24-ball TFBGA 8x6-mm

– Contact Winbond for KGD and other options

 

W25Q128FVFIG SPI / QPI Operations

W25Q128FV Serial Flash Memory Operation Diagram

Figure: W25Q128FV Serial Flash Memory Operation Diagram

Standard SPI Instructions

The W25Q128FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock   (CLK), Chip Select(/CS), Serial Data Input (DI) and Serial Data Output  (DO). Standard SPI instructions use the DI  input pin to serially write instructions.  addresses or data to the device on the rising edge of CLK,  The DO output pin is used to read data or status from the device on the falling edge of CLK

 

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK  signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK  signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK  signal is normally high on the falling and rising edges of /CS.

 

Dual SPI Instructions

The W25Q128FV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices, The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing nonspeed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions. the DI and DO pins become bidirectional I/O pins: IO0 and IO1.

 

Quad SPI Instructions

The W25Q128FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the nonvolatile Quad Enable bit (QE) in Status Register-2 to be set.

 

QPI Instructions

The W25Q128FV supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.

 

Hold Function

For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q128FV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD, when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.

 

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device.

 

Software Reset & Hardware /RESET pin

The W25Q128FV can be reset to the initial power-on state by a software Reset sequence, either in SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS (tRST) to reset. No command will be accepted during the reset period.

 

For the WSON-8 and TFBGA package types, W25Q128FV can also be configured to utilize a hardware /RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any command input.

 

If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four data I/O pins.

 

For the SOIC-16 package, W25Q128FV provides a dedicated /RESET pin in addition to the /HOLD (IO3) pin as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will not affect the function of this dedicated /RESET pin.

 

Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).

 

Note:

 

W25Q128FVFIG Datasheet

You can download the datasheet from the link given below:

W25Q128FVFIG Datasheet

 

W25Q128FVFIG Specifications

Type Description
Category Integrated Circuits (ICs)
Memory
Mfr Winbond Electronics
Series SpiFlash®
Package Tube
Part Status Discontinued at Digi-Key
Memory Type Non-Volatile
Memory Format FLASH
Technology FLASH - NOR
Memory Size 128Mb (16M x 8)
Memory Interface SPI - Quad I/O, QPI
Clock Frequency 104 MHz
Write Cycle Time - Word, Page 50µs, 3ms
Voltage - Supply 2.7V ~ 3.6V
Operating Temperature -40°C ~ 85°C (TA)
Mounting Type Surface Mount
Package / Case 16-SOIC (0.295", 7.50mm Width)
Supplier Device Package 16-SOIC

 

W25Q128FVFIG Manufacturer

Winbond Electronics Corporation is a leading global supplier of semiconductor memory solutions. The company provides customer-driven memory solutions backed by the expert capabilities of product design, R&D, manufacturing, and sales services. Winbond’s product portfolio, consisting of Specialty DRAM, Mobile DRAM, Code Storage Flash, and TrustME® Secure Flash, is widely used by tier-1 customers in communication, consumer electronics, automotive and industrial, and computer peripheral markets.

 

Winbond is headquartered in Central Taiwan Science Park (CTSP) and it has subsidiaries in the USA, Japan, Israel, China, Hong Kong, and Germany. Based on Taichung and new Kaohsiung 12-inch fabs in Taiwan, Winbond keeps pace to develop in-house technologies to provide high-quality memory IC products.

 

Using Warning

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

W25Q128FVFIG FAQ

What is a serial flash memory?

A serial Flash device is a non-volatile memory that can be electrically erased and reprogrammed. It is used for storing executable code in devices such as DVD players, DSL modems, routers, hard-disk drives, and printers.

 

What is the purpose of SPI Flash memory?

SPI Flash memory, also known as Flash storage, has become widespread in the embedded industry and is commonly used for storage and data transfers in portable devices. Common devices include phones, tablets, and media players, as well as industrial devices like security systems and medical products.

 

What is the difference between flash memory and EEPROM?

The main difference between EEPROM and flash memory is that most EEPROM devices can erase any byte of memory at any time. Flash memory can only erase an entire chunk, or "sector", of memory at a time. This means that flash memory can wear out faster than EEPROM.

 

W25Q128FVFIG Documents & Media

Download datasheets and manufacturer documentation for Winbond Electronics W25Q128FVFIG.
Datasheets
PCN Part Status Change

W25Q128FVFIG PCB Symbol, Footprint & 3D Model

Winbond Electronics W25Q128FVFIG

Winbond Electronics

NOR Flash Serial-SPI 3.3V 128Mbit 16M x 8bit 7ns 16-Pin SOIC Tube

Get a quote

Quantity:

Click To Quote

Kynix

Kynix was founded in 2008, specializing in the electronic components distribution business. We adhere to honesty and ethics as our business philosophy and have gradually established an excellent reputation and credibility in our international business. With the accurate quotation, excellent credit, reasonable price, reliable quality, fast delivery, and authentic service, we have won the praise of the majority of customers.

Join our mailing list!

Be the first to know about new products, special offers, and more.

Leave a Reply

We'd love to hear from you! Feel free to share your thoughts and comments below. Rest assured, your email address will remain private.

Name *
Email *
Captcha *
Rating:

Kynix

  • How to purchase

  • Order
  • Search & Inquiry
  • Shipping & Tracking
  • Payment Methods
  • Contact Us

  • Tel: 00852-6915 1330
  • Email: info@kynix.com
  • Follow Us

authentication

Kynix

© 2008-2026 kynix.com all rights reserved.