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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

  • Contents

General Description

This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

 

Catalog

General Description

Ordering Code

Connection Diagram

Function Table

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Switching Characteristics 

Physical Dimensions

LIFE SUPPORT POLICY

DM74LS112A Datasheet

Using Warnings

DM74LS112A FAQ

 

Ordering Code

Ordering Code:

Order Number

Package Number

Package Description

DM74KS112AM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS112AN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

 

Connection Diagram

The following figure is the diagram of DM74LS112A pinout.

 

DM74LS112A Pinout

DM74LS112A Pinout

 

Function Table

Inputs

Outputs

PR

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H L

H

L

X

X

X

L H

L

L

X

X

X

H (Note 1) H (Note 1)

H

H

¯

L

L

Q0 Q0

H

H

¯

H

L

H L

H

H

¯

L

H

L H

H

H

¯

H

H

Toggle

H

H

H

X

X

Q0 Q0

 

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

↓ = Negative Going Edge of Pulse

Q0 = The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.

Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (HIGH) level.

 

Absolute Maximum Ratings

Supply Voltage  7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range  −65°C to +150°C

 

Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

 

Symbol

Parameter

Min

Nom

Max

Units

VCC

Supply Voltage

4.75

5

5.25

V

VIH

HIGH Level Input Voltage

2

 

 

V

VIL

LOW Level Input Voltage

 

 

0.8

V

IOH

HIGH Level Output Current

 

 

-0.4

mA

IOL

LOW Level Output Current

 

 

8

mA

fCLK

Clock Frequency (Note 3)

0

 

30

MHz

fCLK

Clock Frequency (Note 5)

0

 

25

MHz

tW

Pulse Width (Note 3)

Clock HIGH

20

 

 

 

ns

 

 

Preset LOW

25

 

 

 

 

 

Clear LOW

25

 

 

 

tW

Pulse Width (Note 5)

Clock HIGH

25

 

 

 

ns

 

 

Preset LOW

30

 

 

 

 

 

Clear LOW

30

 

 

 

tSU

Setup Time (Note 3)(Note 4)

20¯

 

 

ns

tSU

Setup Time (Note 4)(Note 5)

25¯

 

 

ns

tH

Hold Time (Note 3)(Note 4)

0¯

 

 

ns

tH

Hold Time (Note 4)(Note 5)

5¯

 

 

ns

TA

Free Air Operating Temperature

0

 

70

°C

 

Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.

Note 5: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

 

Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

(Note 6)

Max

Units

VI

Input Clamp Voltage

VCC = Min, II = -18 mA

 

 

-1.5

V

VOH

HIGH Level

Output Voltage

VCC = Min, IOH = Max

VIL = Max, VIH = Min

2.7

3.4

 

V

VOL

LOW Level Output Voltage

VCC = Min, IOL = Max

VIL = Max, VIH = Min

 

0.35

0.5

 

V

 

 

IOL = 4 mA, VCC = Min

 

0.25

0.4

 

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

J, K

 

 

0.1

 

 

mA

 

 

 

Clear

 

 

0.3

 

 

 

 

Preset

 

 

0.3

 

 

 

 

Clock

 

 

0.4

 

IIH

 

 

 

IIL

HIGH Level Input Current

VCC = Max, VI = 2.7V

J, K

 

 

20

 

 

mA

 

 

 

Clear

 

 

60

 

 

 

 

Preset

 

 

60

 

 

 

 

Clock

 

 

80

 

 

LOW Level Input Current

VCC = Max, VI = 0.4V

J, K

 

 

-0.4

 

 

mA

 

 

 

Clear

 

 

-0.8

 

 

 

 

Preset

 

 

-0.8

 

 

 

 

Clock

 

 

-0.8

 

IOS

Short Circuit Output Current

VCC = Max (Note 7)

 

-20

 

-100

mA

ICC

Supply Current

VCC = Max (Note 8)

 

4

6

mA

 

Note 6: All typicals are at VCC = 5V, TA = 25°C.

Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,

where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum

and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.

 

Switching Characteristics 

Symbol

 

Parameter

From (Input) To (Output)

RL = 2 kW

 

Units

 

 

 

CL = 15 pF

CL = 50 pF

 

 

 

 

Min

Max

Min

Max

 

fMAX

Maximum Clock Frequency

 

30

 

25

 

MHz

tPLH

Propagation Delay Time

LOW-to-HIGH Level Output

Preset to Q

 

20

 

24

ns

tPHL

Propagation Delay Time

HIGH-to-LOW Level Output

 

Preset to Q

 

 

20

 

 

28

 

ns

tPLH

Propagation Delay Time

LOW-to-HIGH Level Output

 

Clear to Q

 

 

20

 

 

24

 

ns

tPHL

Propagation Delay Time

HIGH-to-LOW Level Output

Clear to Q

 

20

 

28

ns

tPLH

Propagation Delay Time

LOW-to-HIGH Level Output

 

Clock to Q or Q

 

 

20

 

 

24

 

ns

tPHL

Propagation Delay Time

HIGH-to-LOW Level Output

 

Clock to Q or Q

 

 

20

 

 

28

 

ns

 

Physical Dimensions

The following diagram shows the DM74LS112A package, inches (millimeters) unless otherwise noted.

 

 

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

 

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N16E

 

 

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

 

1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user.

 

2.A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

 

DM74LS112A Datasheet

You can download DM74LS112A datasheet from the link given below:

DM74LS112A Datasheet

 

Using Warnings

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

DM74LS112A FAQ

What is JK flip flop?

The JK flip flop is a universal flip flop having two inputs 'J' and 'K'. So, the JK flip-flop has four possible input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of JK flip flop is the same as SR Bistable Latch except for the addition of a clock input.

 

Why JK flipflop is used?

A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator circuit, thus eliminating the invalid condition when both of it are set,reset is 1.

 

What is the JK flip flop characteristic?

A J-K flip-flop has very similar characteristics to an S-R flip-flop. The only difference is that the undefined condition for an S-R flip-flop, i.e., Sn = Rn = 1 condition, is also included in this case. Inputs J and K behave like inputs S and R to set and reset the flip-flop respectively.

 

Why is J-K flip-flop better than SC flip flop?

The only difference is that the intermediate state is more refined and precise than that of a S-R flip flop. The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.

 

What is a flip flop explain the RS and J-K flip-flop?

It has two states as logic 1(High) and logic 0(low) states. A flip flop is a sequential circuit which consists of a single binary state of information or data. The digital circuit is a flip flop which has two outputs and are of opposite states. It is also known as a Bistable Multivibrator.

DM74LS112AN Documents & Media

Download datasheets and manufacturer documentation for ON Semiconductor DM74LS112AN.
Datasheets
datasheet

DM74LS112AN PCB Symbol, Footprint & 3D Model

ON Semiconductor DM74LS112AN

ON Semiconductor

IC FF JK TYPE DUAL 1BIT 16DIP

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