Understanding Output Capacitance Losses and Dynamic Threshold Voltage

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Author: Rakesh Kumar, Ph.D.

Published: 2023-09-12 | Last Updated: 2023-09-12

Contents

Overview: This article discusses the output capacitance losses and dynamic threshold voltage in Gallium nitride devices. The output capacitance losses are a significant percentage of the device's total loss. The dynamic threshold voltage is a very important factor in power applications.

In the area of technological advancements, Gallium nitride (GaN) devices have emerged as a promising solution for various applications. However, despite their growing deployment, there remain persistent uncertainties surrounding their stability, reliability, and robustness. In both academia and industry, there is a growing focus on addressing the challenges related to the stability, reliability, and robustness of GaN devices.

Gallium nitride high-electron mobility transistors (GaN HEMTs) have stability issues like dynamic on-resistance, dynamic threshold voltage, and output capacitance losses. All of these things are very important in power applications, especially at high frequencies. This article provides a detailed discussion on output capacitance losses and dynamic threshold voltage

When using gallium nitride, how does output capacitance loss impact stability?

GaN HEMTs are responsible for the output capacitance losses. When the off-state power device's equivalent output capacitance is charged and discharged, this loss occurs. In an ideal capacitor, this loss would be zero.

Large-signal, dynamic double sweep in GaN HEMTs leads to power loss because of hysteresis in the relationship between the output charge and the drain-to-source bias. This loss problem has just been brought to light in GaN HEMTs; however, it was first noticed in Si superjunction devices.

GaN HEMTs are experiencing significant output capacitance losses. In high-frequency soft-switching applications, this loss starts to become a significant percentage of the device's total loss from the perspective of the system. This loss is often significantly smaller than the other device losses in hard switching (HSW) or low-frequency applications. Unexpected increases in junction temperature can severely degrade system performance.

Methods to Determine Output Capacitance Loss

This loss has been quantified using a variety of approaches, including calorimetric (thermal) and electric (Sawyer-Tower, nonlinear resonance, and unclamped inductive switching), as shown in Fig. 1. There are benefits and drawbacks to each of these approaches.

Fig. 1. Output Capacitance Loss Determining Method

Thermal Method

Calorimetric Method

One of these methods is the calorimetric method, which involves connecting the device under test (DUT) in parallel with an active switch, leaving the DUT unpowered while the active switch controls the drain-to-source bias, and figuring out the output capacitance loss from the change in junction temperature.

This technique permits the measurement of the loss of the device under test in active soft-switched converters without regard to the operating frequency. However, system calibration in this approach may be time-consuming, and isolating device output capacitance loss from other losses may be difficult. At low power levels, the calorimetric measurement may also lose some of its precision.

Electrical Method

Electrical technique implementation and related data processing are typically easier.

Sawyer-Tower Technique

To generate the sinusoidal excitation, the Sawyer-Tower technique uses a network that includes the DUT, a reference capacitor, and a power amplifier. Since the DUT is always turned off, the input voltage and the capacitor voltage can be used to determine the DUT's large-signal charge-voltage waveforms; the output capacitance loss can then be extracted from the hysteresis of the waveforms.

Nonlinear Resonance or Unclamped Inductive Switching Techniques

The DUT can be switched on or off when using nonlinear resonance or unclamped inductive switching techniques.

Challanges

While these electrical systems require a less complex setup, noise and variation in the waveforms and equipment used (such as narrow probe bandwidth, probe delays, and waveform distortion at high frequencies) may have an impact on their accuracy.

Calorimetric and Sawyer-Tower methods only include the device in its off-state, so they can't be used to investigate how on-state current affects output capacitance loss. The output capacitance loss data from different approaches requires careful consideration of these factors.

Finally, there is still a disagreement over where exactly the output capacitance loss in GaN HEMTs originates, despite widespread agreement that carrier trapping or de-trapping causes output capacitance hysteresis and is a major contributor. The relevant traps' physical origins, location, time constant, and energy level remain unknown.

Output capacitance loss has been linked to both leakage current in the epitaxial structure and resonance on the Si substrate. There haven't been many reports on methods for minimizing output capacitance loss because its cause isn't fully understood. Redesigning the GaN HEMT architecture and epitaxial stack has been proven experimentally to decrease the output capacitance losses.

Output capacitance loss has a major effect on the device selection for high- and very-high-frequency power converters from the perspective of the application. An established approach to characterization that takes into account both the on and off states of the device and faithfully depicts its steady-state switching in converters would greatly speed up this process.

What causes threshold voltage in gallium nitride devices?

The instability of the threshold voltage at high bias temperatures in Si and SiC MOSFETs has been a central topic of study for decades. GaN HEMTs of varying gate designs were also investigated. GaN metal-insulator-semiconductor (MIS) HEMTs were the primary focus of early research.

In MIS-HEMTs, just like in Si and SiC MOSFETs, trapping at the insulator/GaN interface or in the bulk dielectric is what causes the unstable threshold voltage.

Dynamic Threshold Voltage

Recent years have seen a shift in research attention to commercial p-gate HEMTs as p-gate gradually becomes the prevailing E-mode GaN technology. Unlike the threshold voltage instability seen in MOSFETs and MIS-HEMTs, the dynamic threshold voltage in SP-HEMTs is an inherent characteristic of the floating p-GaN layer.

Fig. 2 depicts the SP-HEMT gate stack, which comprises a back-to-back set of p-GaN Schottky junctions coupled with a p-Gan/AlGaN/GaN p-n junction. This "floating" p-GaN layer is the result of the fact that its charges cannot be successfully supplied or removed in fast switching since the bias state (forward or reverse) of these two junctions is opposite each other.

Fig. 2. Typical trapping locations Source: IEEE Transactions on Power Electronics

Positive dynamic threshold voltage shifts are common due to the charge storage process in p-GaN. The off-state blocking voltage and switching frequency both contribute to a larger threshold voltage shift. An Ohmic contact on p-GaN is a notable component of the hybrid-drain gate injection transistor since it facilitates efficient charge supply and extraction and, in turn, a reliable threshold voltage.

Trapping may potentially play a role in the dynamic threshold voltage, in addition to the free-floating p-GaN. There are two trapping mechanisms that can affect a threshold voltage shift when operating under a forward gate-to-source bias.

The first technique causes a negative threshold voltage shift by recoverable hole trapping. The second mechanism causes a positive threshold voltage shift because electrons are trapped and take time to recover.

The dynamic threshold voltage shift may have a significant impact on switching processes in devices. Power loss in SP-HEMT grows as the reverse conduction voltage rises with a positive shift.

The dynamic threshold voltage of SP-HEMTs will influence the majority of their turn-on losses. As a result, the gate's dependability is compromised, and a large gate-drive voltage is required to properly turn on the device.

Therefore, the dynamic threshold voltage should be taken into account in circuit simulations to accurately portray real-world circuit properties. The switching transients in a phase-leg circuit have been recently analyzed using a SPICE model with a dynamic threshold voltage.

What are the additional problems associated with composite devices?

Given their multi-chip nature, composite devices may experience instability problems stemming from both the GaN HEMTs and the interconnections between the Si devices and the GaN HEMTs.

For instance, there have been reports of instability in cascode GaN HEMTs. A diverging oscillation can arise due to a capacitance mismatch between the GaN and Si switches during high-current turn-off situations. Internal switching losses may also rise as a result of the bond wires' inductance between the switches and the Si avalanche.

The current generation of commercial cascode GaN HEMTs does not have internal bond wires between the two chips. Instead, the Si chip is stacked directly on the source pad of the GaN HEMT, which reduces the connectivity-induced loss.

False turn-on events, however, are possible, as are catastrophic failures brought on by SC oscillations. Cascode GaN HEMTs and direct-drive devices, on the other hand, rarely have gate instability because a Si MOSFET drives them largely or because extra protection circuits are copackaged with the GaN HEMT.

Summarizing the Key Points

Gallium nitride (GaN) devices are a promising solution for various applications.

Despite their growing deployment, there remain uncertainties surrounding their stability, reliability, and robustness.

GaN HEMTs have stability issues like dynamic on-resistance, dynamic threshold voltage, and output capacitance losses.

Output capacitance losses are a significant percentage of the device's total loss.

Dynamic threshold voltage is a very important factor in power applications, especially at high frequencies.

Addressing the challenges related to the stability, reliability, and robustness of GaN devices is a growing focus in both academia and industry.

Reference

Kozak, Joseph Peter, Ruizhe Zhang, Matthew Porter, Qihao Song, Jingcun Liu, Bixuan Wang, Rudy Wang, Wataru Saito, and Yuhao Zhang. “Stability, Reliability, and Robustness of GaN Power Devices: A Review.” IEEE Transactions on Power Electronics 38, no. 7 (July 2023): 8442–71. https://doi.org/10.1109/tpel.2023.3266365.

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Rakesh Kumar, Ph.D.

Rakesh Kumar holds a Ph.D. in electrical engineering, specializing in power electronics. He is a Senior Member of the IEEE Power Electronics Society, Class of 2021. He writes high-quality, long-form technical articles for global B2B semiconductor brands. Feel free to reach out to him at rakesh.a@ieee.org! Checkout his complete portfolio @muckrack.com/rakesh-kumar-phd | @linkedin.com/in/rakesh-kumar-phd

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Understanding Output Capacitance Losses and Dynamic Threshold Voltage

When using gallium nitride, how does output capacitance loss impact stability?