The Kynix Blog

(USC professor Sri Narayan's research focuses on the fundamental and applied aspects of electrochemical energy conversion and storage to reduce the carbon footprint of energy use and by providing energy alternatives to fossil fuel, Wednesday, June 10, 2014 in Los Angeles.) Scientists at USC have developed a water-based organic battery that is long lasting, built from cheap, eco-friendly components. The new battery -- which uses no metals or toxic materials -- is intended for use in power plants, where it can make the energy grid more resilient and efficient by creating a large-scale means to store energy for use as needed. "The batteries last for about 5,000 recharge cycles, giving them an estimated 15-year lifespan," said Sri Narayan, professor of chemistry at the USC Dornsife College of Letters, Arts and Sciences and corresponding author of a paper describing the new batteries that was published online by the Journal of the Electrochemical Society on June 20. "Lithium ion batteries degrade after around 1,000 cycles, and cost 10 times more to manufacture." Narayan collaborated with Surya Prakash, Prakash, professor of chemistry and director of the USC Loker Hydrocarbon Research Institute, as well as USC's Bo Yang, Lena Hoober-Burkhardt, and Fang Wang. "Such organic flow batteries will be game-changers for grid electrical energy storage in terms of simplicity, cost, reliability and sustainability," said Prakash. The batteries could pave the way for renewable energy sources to make up a greater share of the nation's energy generation. Solar panels can only generate power when the sun's shining, and wind turbines can only generate power when the wind blows. That inherent unreliability makes it difficult for power companies to rely on them to meet customer demand. With batteries to store surplus energy and then dole it out as needed, that sporadic unreliability could cease to be such an issue. "'Mega-scale' energy storage is a critical problem in the future of the renewable energy, requiring inexpensive and eco-friendly solutions," Narayan said. The new battery is based on a redox flow design -- similar in design to a fuel cell, with two tanks of electroactive materials dissolved in water. The solutions are pumped into a cell containing a membrane between the two fluids with electrodes on either side, releasing energy. The design has the advantage of decoupling power from energy. The tanks of electroactive materials can be made as large as needed -- increasing total amount of energy the system can store -- or the central cell can be tweaked to release that energy faster or slower, altering the amount of power (energy released over time) that the system can generate. The team's breakthrough centered around the electroactive materials. While previous battery designs have used metals or toxic chemicals, Narayan and Prakash wanted to find an organic compound that could be dissolved in water. Such a system would create a minimal impact on the environment, and would likely be cheap, they figured. Through a combination of molecule design and trial-and-error, they found that certain naturally occurring quinones -- oxidized organic compounds -- fit the bill. Quinones are found in plants, fungi, bacteria, and some animals, and are involved in photosynthesis and cellular respiration. "These are the types of molecules that nature uses for energy transfer," Narayan said. Currently, the quinones needed for the batteries are manufactured from naturally occurring hydrocarbons. In the future, the potential exists to derive them from carbon dioxide, Narayan said. The team has filed several patents in regards to design of the battery, and next plans to build a larger scale version. This research was funded by the ARPA-E Open-FOA program (DE-AR0000337), the University of Southern California, and the Loker Hydrocarbon Research Institute. Ref.ML-621S/DNVL-1220/HFNLC-R061R3P

A new compact transistor model was developed and the framework for realizing a faster design support process and product development for integrated circuits in the ultra-low voltage category was established. The new compact model, HiSIM-SOTB (Hiroshima University STARC IGFET Model Silicon-on-Thin BOX), was developed by Hiroshima University's HiSIM Research Center in collaboration with its partners in the industry and government institutions, including the National Institute of Advanced Industrial Science and Technology (AIST) of Japan. On June 20, 2014, after a two-year-long effort by the industry/government/academia research team, this new model was selected as an international industry standard during a meeting in Washington D.C., which was held by the Compact Modeling Coalition (CMC) of the Silicon Integration Initiative (Si2).HiSIM-SOTB accurately replicates the characteristics of the SOTB-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is expected to become a practical transistor structure for super-low-power-consumption by lowering the operating voltage of integrated circuits. The research team, which was led by Prof. Mitiko Miura-Mattausch, HiSIM Research Center of Hiroshima University (headed by Prof. Hans Jurgen Mattausch) and Dr. Hanpei Koike, Leader, Electroinformatics Group, Nanoelectronics Research Institute (headed by Dr. Tetsuji Yasuda) of AIST, successfully implemented the loop between Hiroshima University's development of the transistor model and AIST's reproduction tests of measured data. The results verify that HiSIM-SOTB enables the accurate simulation of circuit operations in the case of substantially lowered supply voltages for transistor operation, ranging from 1 V to 0.4 V.By solving the Poisson equation, HiSIM-SOTB accurately finds the surface potentials at three required positions: the upper and lower sides of the ultrathin SOI (Silicon-on-insulator as a silicon channel layer) film, and the upper side of the substrate. For this purpose, the device physics was represented using three basic equations. To solve these equations including the three surface potentials, it was necessary to address the challenge of stably solving the third-order Newton equation in order to obtain their numerical solutions. However, by developing an appropriate algorithm, the research group has enabled HiSIM-SOTB to accurately reproduce the changes in the substrate-carrier concentration and in the carrier distribution as a function of the applied substrate bias voltage. In parallel, HiSIM-SOTB includes a variety of ingenious twists to shorten the calculation time. HiSIM-SOTB has subsequently been completed as an ultimate compact model that is applicable to any device structure.During the early stages of the development of HiSIM-SOTB, the cooperation that leveraged the strengths of each of our partners in industry, government, and academia was beneficial. This collaboration was carried out based on each partner's previous attempts to realize a standardized compact transistor model. The realization of this effective and rapid cooperation was one of the major reasons why the research team could solve the problems related to the perfection of a compact model for the standardization within the limited time available. Indeed, this collaboration has enabled the ideal scenario to be realized, in that before finalizing the device's design, the evaluation of the circuit characteristics was completed, and an environment for large-scale circuit design was already established. 

Last March, the AI program AlphaGo beat Korean Go champion LEE Se-Dol at the Asian board game. "The game was quite tight, but AlphaGo used 1200 CPUs and 56,000 watts per hour, while Lee used only 20 W. If a hardware that mimics the human brain structure is developed, we can operate artificial intelligence with less power," points out Professor YU Woo Jong.In collaboration with Sungkyunkwan University, researchers from the Center for Integrated Nanostructure Physics within the Institute for Basic Science (IBS), have devised a new memory device inspired by the neuron connections of the human brain.The research, published in Nature Communications, highlights the devise's highly reliable performance, long retention time and endurance. Moreover, its stretchability and flexibility makes it a promising tool for next-gen soft electronics attached to clothes or body.The brain is able to learn and memorise thanks to a huge number of connections between neurons. The information you memorise is transmitted through synapses from one neuron to the next as an electro-chemical signal.Inspired by these connections, IBS scientists constructed a memory called two-terminal tunnelling random access memory (TRAM), where two electrodes, referred to as drain and source, resemble the two communicating neurons of the synapse.While mainstream mobile electronics, like digital cameras and mobile phones use the so-called three-terminal flash memory, the advantage of two-terminal memories like TRAM is that two-terminal memories do not need a thick and rigid oxide layer."Flash memory is still more reliable and has better performance, but TRAM is more flexible and can be scalable," explains Professor Yu.TRAM is made up of a stack of one-atom-thick or a few atom-thick 2D crystal layers: One layer of the semiconductor molybdenum disulfide (MoS2) with two electrodes (drain and source), an insulating layer of hexagonal boron nitride (h-BN) and a graphene layer.In simple terms, memory is created (logical-0), read and erased (logical-1) by the flowing of charges through these layers. TRAM stores data by keeping electrons on its graphene layer. By applying different voltages between the electrodes, electrons flow from the drain to the graphene layer tunnelling through the insulating h-BN layer.The graphene layer becomes negatively charged and memory is written and stored and vice versa, when positive charges are introduced in the graphene layer, memory is erased.IBS scientists carefully selected the thickness of the insulating h-BN layer as they found that a thickness of 7.5 nm allows the electrons to tunnel from the drain electrode to the graphene layer without leakages and without losing flexibility.Flexibility and stretchability are indeed two key features of TRAM. When TRAM was fabricated on flexible plastic (PET) and stretachable silicone materials (PDMS), it could be strained up to 0.5% and 20%, respectively.In the future, TRAM can be useful to save data from flexible or wearable smartphones, eye cameras, smart surgical gloves, and body-attachable biomedical devices.Last but not least, TRAM has better performance than other types of two-terminal memories known as phase-change random-access memory (PRAM) and resistive random-access memory (RRAM).Reference:MT16JTF51264AZ-1G6M1MD2202-D192MD2203-D576

Linear Technology introduces the LTM4631, a dual 10-A or single 20-A µModule (power module) step-down regulator in a 1.91-mm-high LGA package with a 16 x 16-mm footprint. The packaging is what makes this module significant and sets it apart from the competition. Why? Because the device provides a regulator, including the inductor, in one package, while others, like Intersil and Altera/Enpirion, need two chips for the solution. That means that the Linear product needs 400 mm2 compared to the 750 mm2 for the Intersil product and about 600 mm2 for the Altera/Enpirion solutions. At 1.91 mm, the height of the package is also very significant because it means it’s under 2.00 mm, which is a barrier to designs that aim to provide solutions for the underside of the PCB. Presently, Altera/Enpirion, at 1.85 mm, is the only other company that can offer a solution profile less than 2.00 mm. The LTM4631 regulator, although a very significant achievement in packaging, is not a solution for every design because not everyone is looking for a cutting-edge solution. However, for the targeted markets, designers could find this device to be aspirin for their design pains. It is a solution you can’t find anywhere else. The micro-module can be placed on a PCB very close to the load, such as an FPGA, and can share one heat sink covering both of the low-profile packages. It frees space on the topside for components such as DDR-QDR memory and transceiver ICs. Examples of applications include plug-in and mezzanine cards in embedded systems, data storage systems, gateway controllers, and 40- to 100-Gbps networks. These applications are very competitive and gaining space as shown in the figure is a significant advantage, to system designers.  When I first looked at this product, I was very impressed with the specs, especially the packaging, but the price could give you heartburn. Some companies with the technical chops could design a discrete solution for a much lower cost, but then there’s the obvious problem of excessive footprint caused by all of those components. There is also a potential of reduced reliability with discretes. At $24.88 ea/1,000, deciding to use this product isn’t quite a no-brainer, but if you do, it means that you want to spend your engineering time on what you design best, such as embedded systems or gateway controllers, and getting the extra board space for your latest product.  The LTM4631 wasn’t just a simple redesign of what Linear already offered, although according to Afshin Odabaee, business unit manager of power modules for Linear Technology, at the start of the regulator design, they thought it would take about six months to finish. It took much longer to finish — almost 2 years. But they learned a lot along the way, such as how to get the inductor smaller, what materials to use in the inductor, and even how to get the accuracy down to 1.5% for the total dc output error over line, load and temperature. The specs for the LTM4631 show that it operates from 4.5- to 15-V input supplies and regulates an output voltage from 0.6 to 1.8 V with ±1.5% maximum total dc output voltage error from –40°C to 125°C. Its two outputs operate 180° out-of-phase, each capable of delivering 10 A or 20 A when the outputs current share. Two devices can current share, delivering up to 40 A while minimizing input and output ripple current. The device features output overcurrent foldback and overvoltage protection. 

Overview: This article explores the SPI communication protocol, detailing its components, working principles, and applications in IoT and embedded systems for efficient data exchange.The SPI communication protocol is the recommended option for applications needing quick and effective data interchange in IoT sensors, memory modules, and display controllers because it offers excellent data transfer rates.What is an SPI?The serial peripheral interface (SPI) is a 4-wire, serial, synchronous, full-duplex communication protocol for data exchange between a microcontroller and peripheral devices. It was introduced by Motorola and is based on a master-slave architecture featuring one master (controller) and one or more slaves (peripherals).Key ComponentsSPI uses separate clock signals, and the term "4-wire" refers to communication between a master device and one or more slave devices using four signal lines, enabling simultaneous data transmission and reception, as shown in Fig. 1.Fig. 1. Diagrammatic illustration of SPI framework. Source: Journal of Physics Conference SeriesChip Select (CS)The master uses this line to select the specific slave device it wants to communicate with. For systems with multiple slaves, each device can have a dedicated CS line or multiple devices can be managed with fewer CS lines.Serial Clock (SCLK)The master generates this clock signal to synchronize data transfer between devices. Only the master generates the SCLK signal, and the slave cannot initiate communication or adjust the clock.Master Out Slave In (MOSI)This line carries data from the master to the slave. The data is transmitted serially, starting with the most significant bit (MSB).Master In Slave Out (MISO)This line carries data from the slave back to the master. The data is sent serially, often starting with the least significant bit (LSB).Working PrincipleThe data transmission is initiated by pulling the CS line low, and the master directly selects the target device. This CS line eliminates the need for explicit addressing required in protocols like I2C and CAN bus. After the master pulls the CS line low, it generates the clock signal to ensure both master and slave devices are synchronized.MOSI begins to send data from the master to the slave. The data is sent serially, bit by bit, and SPI allows for multiple bytes to be sent sequentially without interruption. This is achieved by keeping the CS line low throughout the data transfer, and the slave remains selected and continues to receive data.While data is being sent from the master to the slave via MOSI, data can simultaneously be sent from the slave to the master via MISO. This full-duplex nature of SPI enables efficient communication.MISO is used by slave devices to send data back to the master, often as a response to commands or queries (e.g., sensor readings and status updates). Some peripherals (e.g., displays, DACs) only receive data and lack MISO. In such cases, SPI operates with three wires (MOSI, SCLK, CS).Key ParametersClock polarity (CPOL) and clock phase (CPHA) are essential parameters in SPI protocol.Clock PolarityThe SPI clock can be idle low, or high.Idle Low (CPOL = 0): The clock signal is held at a low voltage level during idle state.Idle High (CPOL = 1): The clock signal is held at a high voltage level during idle state.Clock PhaseThe clock phase works with CPOL to define whether data is sampled on the rising or falling edge of the clock cycle.CPHA = 0: Data is sampled on the rising clock edge (relative to the idle state).CPHA = 1: Data is sampled on the falling clock edge.Four SPI modes are defined by the combination of CPOL and CPHA values, as shown in Fig. 2.Fig. 2. Four working modes of SPI based on the combination of CPOL and CPHA. Source: Journal of Physics Conference SeriesMode 0 (CPOL = 0, CPHA = 0): In this mode, the clock signal remains low during the idle state, and data sampling occurs on the rising edge.Mode 1 (CPOL = 0, CPHA = 1): In this mode, the clock signal remains low during idle, and data is sampled on the falling edge.Mode 2 (CPOL = 1, CPHA = 0): In this mode, the clock signal remains high during idle, and data is sampled on the falling edge.Mode 3 (CPOL = 1, CPHA = 1): In this mode, the clock signal remains high during idle, and the data is sampled on the rising edge.AdvantagesWith only four primary signal lines, SPI simplifies hardware design compared to more complex protocols like I2C. The SPI protocol enables serial communication where data is transmitted sequentially, one bit at a time, by using a minimal number of cables. It reduces hardware costs and complexity compared to parallel systems.SPI facilitates synchronous communication using a shared clock signal between the sender and receiver. It enables full-duplex communication where devices send and receive data simultaneously through separate lines. It supports configurable data widths, allowing up to 128 bits, which provides adaptability for various applications. It achieves high data rates, typically up to several Mbps or MHz.ApplicationsSPI is more commonly used in consumer electronics, particularly in low-power and cost-effective systems. It interfaces with sensors, displays, memory devices, ADC/DAC converters, real-time clocks, game controllers, wireless modules like Wi-Fi and Bluetooth, EEPROM, flash, digital signal processor, and a digital signal decoder facilitating efficient data exchange. The SPI protocol is more commonly used in wearables and IoT devices.Summarizing the Key PointsSPI is a 4-wire, full-duplex communication protocol that facilitates quick data exchange between microcontrollers and peripherals.The protocol utilizes four main signal lines: MOSI, MISO, SCLK, and CS, simplifying hardware design compared to more complex protocols like I2C.There are four SPI modes determined by clock polarity and clock phase, influencing data sampling and synchronization rates.Typical applications of SPI include interfacing with sensors, displays, memory devices, and wireless modules.ReferenceLiao, C., Yu, H., & Liao, Y. (2025). Verification of SPI protocol using universal verification methodology for modern IoT and wearable devices. Electronics, 14(5), 837. https://doi.org/10.3390/electronics14050837Qiang, J., Gu, Y., & Chen, G. (2020). FPGA implementation of SPI bus communication based on state machine Method. Journal of Physics Conference Series, 1449(1), 012027. https://doi.org/10.1088/1742-6596/1449/1/012027Rohde & Schwarz. (2023, April 12). Understanding SPI [Video]. YouTube. https://www.youtube.com/watch?v=0nVNwozXsIc

Researchers have developed a prototype of a next-generation lithium-sulphur battery which takes its inspiration in part from the cells lining the human intestine. The batteries, if commercially developed, would have five times the energy density of the lithium-ion batteries used in smartphones and other electronics.The new design, by researchers from the University of Cambridge, overcomes one of the key technical problems hindering the commercial development of lithium-sulphur batteries, by preventing the degradation of the battery caused by the loss of material within it. The results are reported in the journal Advanced Functional Materials.Working with collaborators at the Beijing Institute of Technology, the Cambridge researchers based in Dr Vasant Kumar's team in the Department of Materials Science and Metallurgy developed and tested a lightweight nanostructured material which resembles villi, the finger-like protrusions which line the small intestine. In the human body, villi are used to absorb the products of digestion and increase the surface area over which this process can take place.In the new lithium-sulphur battery, a layer of material with a villi-like structure, made from tiny zinc oxide wires, is placed on the surface of one of the battery's electrodes. This can trap fragments of the active material when they break off, keeping them electrochemically accessible and allowing the material to be reused."It's a tiny thing, this layer, but it's important," said study co-author Dr Paul Coxon from Cambridge's Department of Materials Science and Metallurgy. "This gets us a long way through the bottleneck which is preventing the development of better batteries."A typical lithium-ion battery is made of three separate components: an anode (negative electrode), a cathode (positive electrode) and an electrolyte in the middle. The most common materials for the anode and cathode are graphite and lithium cobalt oxide respectively, which both have layered structures. Positively-charged lithium ions move back and forth from the cathode, through the electrolyte and into the anode.The crystal structure of the electrode materials determines how much energy can be squeezed into the battery. For example, due to the atomic structure of carbon, each carbon atom can take on six lithium ions, limiting the maximum capacity of the battery.Sulphur and lithium react differently, via a multi-electron transfer mechanism meaning that elemental sulphur can offer a much higher theoretical capacity, resulting in a lithium-sulphur battery with much higher energy density. However, when the battery discharges, the lithium and sulphur interact and the ring-like sulphur molecules transform into chain-like structures, known as a poly-sulphides. As the battery undergoes several charge-discharge cycles, bits of the poly-sulphide can go into the electrolyte, so that over time the battery gradually loses active material.The Cambridge researchers have created a functional layer which lies on top of the cathode and fixes the active material to a conductive framework so the active material can be reused. The layer is made up of tiny, one-dimensional zinc oxide nanowires grown on a scaffold. The concept was trialled using commercially-available nickel foam for support. After successful results, the foam was replaced by a lightweight carbon fibre mat to reduce the battery's overall weight."Changing from stiff nickel foam to flexible carbon fibre mat makes the layer mimic the way small intestine works even further," said study co-author Dr Yingjun Liu.This functional layer, like the intestinal villi it resembles, has a very high surface area. The material has a very strong chemical bond with the poly-sulphides, allowing the active material to be used for longer, greatly increasing the lifespan of the battery."This is the first time a chemically functional layer with a well-organised nano-architecture has been proposed to trap and reuse the dissolved active materials during battery charging and discharging," said the study's lead author Teng Zhao, a PhD student from the Department of Materials Science & Metallurgy. "By taking our inspiration from the natural world, we were able to come up with a solution that we hope will accelerate the development of next-generation batteries."For the time being, the device is a proof of principle, so commercially-available lithium-sulphur batteries are still some years away. Additionally, while the number of times the battery can be charged and discharged has been improved, it is still not able to go through as many charge cycles as a lithium-ion battery. However, since a lithium-sulphur battery does not need to be charged as often as a lithium-ion battery, it may be the case that the increase in energy density cancels out the lower total number of charge-discharge cycles."This is a way of getting around one of those awkward little problems that affects all of us," said Coxon. "We're all tied in to our electronic devices - ultimately, we're just trying to make those devices work better, hopefully making our lives a little bit nicer."Reference:KY605-ML-621S/ZTNKY605-MS412FE-FL26EKY605-MS518SE-FL35E