The Kynix Blog - IC Chips

A simple and efficient PWM lamp dimmer using timer IC NE555 is discussed in this article. Yesterdays linear regulator based dimmers can only attain a maximum efficiency  of 50% and are far inferior when compared to the PWM based dimmers which can hit well over 90% efficiency. Since less amount of power is wasted as heat, the switching elements of PWM dimmers require a smaller heat sink and this saves a lot of size and weight. In simple words, the most outstanding features of the PWM based lamp dimmers are high efficiency and low physical size. The circuit diagram of a 12V PWM lamp dimmer is shown below. As you can see, NE555 timer IC which is wired as an astable multivibrator operating at 2.8KHz forms the heart of this circuit. Resistors R1,R2, POT R3 and capacitor C1 are the timing components. Duty cycle of the IC’s output can be adjusted using the POT R3. higher the duty cycle means higher the lamp brightness and lower the duty cycle means lower the lamp brightness. Diode D1 by-passes the lower half of the POT R3 during the charging cycle of the astable multivibrator. This is done in order to keep the output frequency constant irrespective of the duty cycle. Transistors Q1 and Q2 forms a darlington driver stage for the 12V lamp. Resistor R4 limits the base current of transistor Q1.Understanding the variable duty cycle astable multivibrator.As I have said earlier, the variable duty cycle astable multi vibrator based on NE555 forms the foundation of this circuit and a good knowledge on it is essential for designing projects like this. For the ease of explanation the timing side of the astable multivibrator is redrawn in the figure below.Upper and lower halves of the POT R3 are denoted as Rx and Ry respectively. Consider the output of the astable multivibrator to be high at the starting instant. Now the capacitor C1 charges through the path R1, Rx, and R2. The lower half of POT R3 ie; Ry is out of the scene because the diode D1 by-passes it. When the voltage across the capacitor reaches 2/3 Vcc, the internal upper comparator flips its output which makes the internal flip flop to toggle its output. As a result the output of the astable multivibrator goes low. In simple words, the output of the astable multivibrator remains high until the charge across C1 becomes equal to 2/3 Vcc and here it is according to the equation Ton =0.67(R1+Rx+R2)C1.Since the internal flip flop is set now, the capacitor starts discharging through the path R2,Ry into the discharge pin. When the voltage across the capacitor C1 becomes 1/3 Vcc, the lower comparator flips its output and this in turn makes the internal flip flop to toggle its output again. This makes the output of the astable multivibrator high. To be simple, the output of the astable multivibrator remains low until the voltage across the capacitor C1 becomes 1/3 Vcc and it is according to the equation Toff = 0.67(R2+Ry)C1. Have a look at the internal block diagram of NE555 timer shown below for better understanding.How does the frequency remain constant irrespective of the position of POT3 knob?.What ever may be the position of  POT3 knob, the total resistance across it remains the same (50K here). If anything decreases in the upper side (Rx) the same amount will be increased in the lower (Ry) and the same thing gets applied to the higher(Ton) and lower(Toff) time periods. The derivation shown below will help you to grasp the matter easily.With reference to Fig 2, we have:Ton = 0.67(R1+Rx+R2)C1Toff= 0.67(R2+Ry)C1Total time period of the output waveform “T” is according to the equation :T = Ton + ToffThere fore, T = 0.67(R1+Rx+R2+R2+Ry)C1                        T= 0.67(R1+2R2+Rx+Ry)C1We know that Rx+Ry = R3There fore T = 0.67(R1+2R2+R3)C1Therefore frequency F = 1/(0.67(R1+2R2+R3)C1) From the above equation its is clear that the frequency depends only on the value of the components C1, R1, R2  and the over all value of R3 and it has nothing to do with the position of R3 knob.  Ref:KY32-NE555KY32-NE555.NE555DR.NE555P 

Today, at the imec technology forum (ITF2017), imec demonstrated the world's first self-learning neuromorphic chip. The brain-inspired chip, based on OxRAM technology, has the capability of self-learning and has been demonstrated to have the ability to compose music.The human brain is a dream for computer scientists: it has a huge computing power while consuming only a few tens of Watts. Imec researchers are combining state-of-the-art hardware and software to design chips that feature these desirable characteristics of a self-learning system. Imec's ultimate goal is to design the process technology and building blocks to make artificial intelligence to be energy efficient so that that it can be integrated into sensors. Such intelligent sensors will drive the internet of things forward. This would not only allow machine learning to be present in all sensors but also allow on-field learning capability to further improve the learning.By co-optimizing the hardware and the software, the chip features machine learning and intelligence characteristics on a small area, while consuming only very little power. The chip is self-learning, meaning that is makes associations between what it has experienced and what it experiences. The more it experiences, the stronger the connections will be. The chip presented today has learned to compose new music and the rules for the composition are learnt on the fly.It is imec's ultimate goal to further advance both hardware and software to achieve very low-power, high-performance, low-cost and highly miniaturized neuromorphic chips that can be applied in many domains ranging for personal health, energy, traffic management etc. For example, neuromorphic chips integrated into sensors for health monitoring would enable to identify a particular heartrate change that could lead to heart abnormalities, and would learn to recognize slightly different ECG patterns that vary between individuals. Such neuromorphic chips would thus enable more customized and patient-centric monitoring."Because we have hardware, system design and software expertise under one roof, imec is ideally positioned to drive neuromorphic computing forward," says Praveen Raghavan, distinguished member of the technical Staff at imec. "Our chip has evolved from co-optimizing logic, memory, algorithms and system in a holistic way. This way, we succeeded in developing the building blocks for such a self-learning system." Ref:KY32-MAX1490AEPG+KY32-LN3251MPW

As integrated circuit components are coming up against size limits, manufacturers are turning to new approaches based on stacking extremely thin wafers. However, the thin wafers easily warp under the stresses involved in fabrication, and measuring the stress and warpage has so far proven challenging.In a paper published in the Journal of Applied Crystallography, Professor Patrick McNally's team at Dublin City University, together with collaborators Brian Tanner at Durham University and Andreas Danilewsky at the University of Freiburg, report on a new technique using the Test beamline (B16) at Diamond Light Source to accurately, precisely, and verifiably measure the stress and warpage in individual silicon wafers. The researchers are now cooperating with industry partners to translate their approach into a tool which can be used for quality assurance and to improve fabrication processes. Meanwhile, they continue to work at Diamond to improve the technique and adapt it to different contexts and materials.A stack of measurement troubleIn a 1965 paper, Intel co-founder Gordon Moore observed that the density of transistors in integrated circuits doubled every 18-24 months, a trend which has held well in the decades since. However, manufacturing techniques are nearing the limits of 'Moore's law' as the components printed onto integrated circuits approach atomic dimensions. To continue improving performance, manufacturers are exploring a new direction by combining different chips, each with a specialised function, into a vertical package in a 'more than Moore' approach known as heterogeneous integration.The new technique involves using wafers less than a tenth as thick as those currently in use. Since they are so thin – just 25 to 100 µm – the wafers are extremely flexible, but they are also subjected to extreme stress during the fabrication process. "Imagine you glue together four or five pieces of silicon, each thinner than a human hair, then heat them up to 100-200° C, and then stand on top of them with your boot. Maybe you jump up and down a bit. That's the sort of damage that's done as part of semiconductor processing," explains Professor Patrick McNally of Dublin City University. The stress and resulting warpage of the wafers during manufacturing can lead to malfunctions, altered performance, and silicon 'real estate' lost to stress-related 'keep out zones' on the chip. To avoid these pitfalls, manufacturers are eager to understand how to manage stress and warpage in their design and fabrication processes.So far, measuring the warpage of the individual silicon wafers without damaging them has been impossible, forcing people to use the warpage of the entire package as a proxy. Using the Test beamline (B16) at Diamond, the trio have developed a non-destructive technique to precisely and accurately measure the warpage of each wafer in a package through transmission X-ray diffraction imaging. To confirm their measurement technique, the team included samples with known curvature and displacement from IMEC in Belgium. "We've proven that it can be done reliably and verifiably," said Professor McNally.To industry and beyondWhile the new technique shows great promise, "no one in the semiconductor business is going to back a synchrotron into their fabrication facility," noted Professor McNally. The team has already successfully carried out preliminary trials with a commercial tool as an X-ray source, and work is underway with X-ray metrology companies to bring the technique into industry as a quality assurance tool. Improving the measurement speed of the commercial tools is a major outstanding challenge – measurements done in minutes at Diamond can take hours with commercial tools – but the team is pursuing avenues to improve this.The technique offers an opportunity not only to measure warpage during fabrication but also to improve the design process. Mechanical engineers at a large chip company are working with the team to test the finite element models they use to predict stress and warpage in their designs. "The idea is that we provide a 'sanity check' on their modelling so they can use it to improve their designs," said Professor McNally.Meanwhile, the team is continuing to develop the approach using the facilities at Diamond, which underpins any advancements. The team has recently tested their new technique on chips, which were receiving power to measure how the warpage might change under different usage conditions. "We do our top end development at Diamond," said Professor McNally, explaining that the ability to rapidly test and explore ideas at the synchrotron is crucial before they can be adapted for industry applications.Ref:KY32-MAX1490AEPG+KY32-LMX4169AQFXN      

The giant chip maker Intel has finally released its 3ed generation chips named Ivy Bridge. They says that the new microprocessor chips used fundamentally different technology. These chips comes with 3D Transistors and are manufactured at 22nm process. The new technology will ensure high processing speed along with power saving. The chip makers keep the pace of Moore’s law by making the new chips using 3d transistor technology along with other advanced capabilities. We can hope that, customers will certainly welcome the new chip, because of the competence of it predecessors including the current Sandy Bridge chips. We know that transistors are the heart of processors and a microprocessor contains millions of it. Until today transistors were 2D (planar) devices, but Intel’s new Ivy Bridge chips comes with sophisticated 3D Tri-Gate Transistors. The new Ivy Bridge chips will power Gaming PC’s, Servers, Super Computers and all-in-one PC’s. We can hope that through this new line of chips, Intel will dominate in chip market with its major rival AMD. Now we will discuss some of the important features of the new Ivy Bridge chips. Ivy Bridge chips are relatively smaller and lighter in weight as it utilizes advanced technologies. The 3D Transistors these chips are lighter compared to transistors used in previous chips of Intel, through this Intel delivers the advantages of Moore’s law to its users. Intel has shrunk the Manufacturing technology of Ivy Bridge chips lower to 22nm because Intel notes that smaller chips are better in providing higher performance and higher efficiency. Intel says that in 2007 their CPU manufacturing process has changed to 45nm with high-k/metal gate, in 2009 to 32nm and now to 22nm with the world’s first 3-D transistor in a high volume logic process. Intel has made the new Ivy Bridge transistors in such a way that it can work efficiently even at lower voltages. Thus through this advanced sophisticated Ivy Bridge chips Intel strengthened its domination in global chip market and the company lifts up challenge not only to AMD but also to ARM holding the mobile chip market. Reference: KY32-NU80579EZ600CT KY32-NU80579ED009C

Harvard University researchers have made the first entirely 3D-printed organ-on-a-chip with integrated sensing. Built by a fully automated, digital manufacturing procedure, the 3D-printed heart-on-a-chip can be quickly fabricated in customized form factors allowing researchers to easily collect reliable data for short-term and long-term studies.This new approach to manufacturing may one day allow researchers to rapidly design organs-on-chips, also known as microphysiological systems, that match the properties of a specific disease or even an individual patient's cells.The research is published in Nature Materials."This new programmable approach to building organs-on-chips not only allows us to easily change and customize the design of the system by integrating sensing but also drastically simplifies data acquisition," said Johan Ulrik Lind, first author of the paper and postdoctoral fellow at the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS). Lind is also a researcher at the Wyss Institute for Biologically Inspired Engineering at Harvard University."Our microfabrication approach opens new avenues for in vitro tissue engineering, toxicology and drug screening research," said Kit Parker, Tarr Family Professor of Bioengineering and Applied Physics at SEAS, who coauthored the study. Parker is also a Core Faculty Member of the Wyss Institute.Organs-on-chips mimic the structure and function of native tissue and have emerged as a promising alternative to traditional animal testing. Harvard researchers have developed microphysiological systems that mimic the microarchitecture and functions of lungs, hearts, tongues and intestines.However, the fabrication and data collection process for organs-on-chips is expensive and laborious. Currently, these devices are built in clean rooms using a complex, multi-step lithographic process and collecting data requires microscopy or high-speed cameras."Our approach was to address these two challenges simultaneously via digital manufacturing," said Travis Busbee, coauthor of the paper and graduate student in the Lewis Lab. "By developing new printable inks for multi-material 3D printing, we were able to automate the fabrication process while increasing the complexity of the devices."The researchers developed six different inks that integrated soft strain sensors within the micro-architecture of the tissue. In a single, continuous procedure, the team 3D printed those materials into a cardiac microphysiological device—a heart on a chip—with integrated sensors."We are pushing the boundaries of three-dimensional printing by developing and integrating multiple functional materials within printed devices," said Jennifer Lewis, Hansjorg Wyss Professor of Biologically Inspired Engineering, and coauthor of the study. "This study is a powerful demonstration of how our platform can be used to create fully functional, instrumented chips for drug screening and disease modeling."The chip contains multiple wells, each with separate tissues and integrated sensors, allowing researchers to study many engineered cardiac tissues at once. To demonstrate the efficacy of the device, the team performed drug studies and longer-term studies of gradual changes in the contractile stress of engineered cardiac tissues, which can occur over the course of several weeks."Researchers are often left working in the dark when it comes to gradual changes that occur during cardiac tissue development and maturation because there has been a lack of easy, non-invasive ways to measure the tissue functional performance," said Lind. "These integrated sensors allow researchers to continuously collect data while tissues mature and improve their contractility. Similarly, they will enable studies of gradual effects of chronic exposure to toxins.""Translating microphysiological devices into truly valuable platforms for studying human health and disease requires that we address both data acquisition and manufacturing of our devices," said Parker. "This work offers new potential solutions to both of these central challenges."Reference:KY45-59020-010KY45-59135-020KY45-MK21P-1B90C-500W   

What about using wax with a processor as part of a technique to stave off smartphone overheating? Can wax be the answer to the thermal problem confronting smartphones? That is the proposal coming from a University of Pensylvania and University of Michigan team of researchers, who have been studying ways to manage the chip performance of smartphones. Milo Martin, an associate professor with the University of Pennsylvania and his colleagues at the two schools believe the answer is in computational sprinting involving wax. "When someone cranks the chip well beyond its recommended speeds, the wax absorbs the extra heat coming off the silicon, and at 54 degrees Celsius, it starts to melt," said a report about their research in Wired. Small mobile devices don't have room for the large fans that cool a laptop. If mobile phones actually used all of their transistors at the same time, they would overheat. Only a portion of a smartphone chip's transistors can operate at once. If you hear the term "dark silicon" it refers to the large portions of a silicon chip that must remain off at a given time. As transistors get smaller, the heat problems may only get worse.This is where computational sprinting comes into view. Under the concept of computational sprinting, a chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip returns to nominal operation to cool down. The team from the two schools have been exploring computational sprinting for several years. This is a technique that uses all transistors at once, using the sprint-and-rest technique of periodic boosts.In 2012, the researchers presented a paper at the High Performance Computer Architecture (HPCA) symposium, where they noted how many mobile applications do not demand sustained performance; rather, they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, the authors explored activating otherwise powered-down cores for subsecond bursts of intense parallel computation.The authors concluded that "Although numerous engineering challenges remain (in cost, thermal materials, packaging, and power supply), our study indicates that it is feasible to capture the responsiveness of a 16W chip within the engineering constraints of a 1W mobile device via parallel computational sprinting."Back in 2012 they had wax in mind as a heat-spreading structure that includes an encapsulated phase change material—like candle wax—which would absorb heat by melting during the sprint, then slowly dissipate it by hardening while the device is at rest, according to a University of Michigan News Services report.This year, reported Wired, "they set up an Intel Core i7 test processor with a custom cooling system that could run comfortably at a maximum of 10 watts of power. In their tests, though, they would periodically boost the chip to 50 watts."That is enough to overheat the chip in seconds, "but it speeds up the chip's clock speed and it uses more transistors." The team thinks they could possibly boost the chip up to 100 watts for short periods, becoming very hot, and that is where the wax could absorb much of the heat quickly until it melts.Related products:KY56-KST2222KY56-KST06KY56-KSH2955