The Kynix Blog - News Room

Using microfluidic passages cut directly into the backsides of production field-programmable gate array (FPGA) devices, Georgia Institute of Technology researchers are putting liquid cooling right where it's needed the most - a few hundred microns away from where the transistors are operating.Combined with connection technology that operates through structures in the cooling passages, the new technologies could allow development of denser and more powerful integrated electronic systems that would no longer require heat sinks or cooling fans on top of the integrated circuits. Working with popular 28-nanometer FPGA devices made by Altera Corp., the researchers have demonstrated a monolithically-cooled chip that can operate at temperatures more than 60 percent below those of similar air-cooled chips.In addition to more processing power, the lower temperatures can mean longer device life and less current leakage. The cooling comes from simple de-ionized water flowing through microfluidic passages that replace the massive air-cooled heat sinks normally placed on the backs of chips."We believe we have eliminated one of the major barriers to building high-performance systems that are more compact and energy efficient," said Muhannad Bakir, an associate professor and ON Semiconductor Junior Professor in the Georgia Tech School of Electrical and Computer Engineering. "We have eliminated the heat sink atop the silicon die by moving liquid cooling just a few hundred microns away from the transistors. We believe that reliably integrating microfluidic cooling directly on the silicon will be a disruptive technology for a new generation of electronics."Liquid cooling has been used to address the heat challenges facing computing systems whose power needs have been increasing. However, existing liquid cooling technology removes heat using cold plates externally attached to fully packaged silicon chips - adding thermal resistance and reducing the heat-rejection efficiency.To make their liquid cooling system, Bakir and graduate student Thomas Sarvey removed the heat sink and heat-spreading materials from the backs of stock Altera FPGA chips. They then etched cooling passages into the silicon, incorporating silicon cylinders approximately 100 microns in diameter to improve heat transmission into the liquid. A silicon layer was then placed over the flow passages, and ports were attached for the connection of water tubes.In multiple tests - including a demonstration for DARPA officials in Arlington, Virginia - a liquid-cooled FPGA was operated using a custom processor architecture provided by Altera. With a water inlet temperature of approximately 20 degrees Celsius and an inlet flow rate of 147 milliliters per minute, the liquid-cooled FPGA operated at a temperature of less than 24 degrees Celsius, compared to an air-cooled device that operated at 60 degrees Celsius.Sudhakar Yalamanchili, a professor in the Georgia Tech School of Electrical and Computer Engineering and one of the research group's collaborators, joined the team for the DARPA demonstration to discuss electrical-thermal co-design."We have created a real electronic platform to evaluate the benefits of liquid cooling versus air cooling," said Bakir. "This may open the door to stacking multiple chips, potentially multiple FPGA chips or FPGA chips with other chips that are high in power consumption. We are seeing a significant reduction in the temperature of these liquid-cooled chips."The research team chose FPGAs for their test because they provide a platform to test different circuit designs, and because FPGAs are common in many market segments, including defense. However, the same technology could also be used to cool CPUs, GPUs and other devices such as power amplifiers, Bakir said.In addition to improving overall cooling, the system could reduce hotspots in circuits by applying cooling much closer to the power source. Eliminating the heat sink could allow more compact packaging of electronic devices - but only if electrical connection issues are also addressed.In a separate research project, Bakir's group has demonstrated the fabrication of copper vias that would run through the silicon columns that are part of the cooling structure fabricated on the FPGAs. Graduate student Hanju Oh, co-advised with College of Engineering Dean Gary May, fabricated high aspect ratio copper vias through the silicon columns, reducing the capacitance of the connections that would carry signals between chips in an array."The moment you start thinking about stacking the chips, you need to have copper vias to connect them," Bakir said. "By bringing system components closer together, we can reduce interconnect length and that will lead to improvements in bandwidth density and reductions in energy use."The cooling research was funded by DARPA's Microsystems Technology Office, through the ICECOOL program. At Georgia Tech, DARPA funds two major cooling and system integration projects, one called STAECool directed by George W. Woodruff School of Mechanical Engineering Professor Yogendra Joshi, and the other, called SuperCool, that is directed by Bakir. In collaboration with the STAECool effort, Bakir and Joshi, along with Professors Andrei Fedorov and Suresh Sitaraman from the School of Mechanical Engineering, developed a thermal design vehicle to emulate challenging power maps to test the benefits of microfluidic cooling."We have reached an important milestone that we hope to use as a stepping stone to reach other objectives," said Bakir. "There is still a big challenge ahead, but we expect this to allow much denser, higher-performance computing systems that will dissipate less power. We can think of many interesting applications for these cooling technologies."Altera's principal investigator for the project, Arifur Rahman, said: "Future high-performance semiconductor electronics will be increasingly dominated by thermal budget and ability to remove heat. The embedded microfluidic channels provide an intriguing option to remove heat from future microelectronics systems."   

Arash Moradi and Mohamad Sawan from Polytechnique Montreal in Canada discuss their new low-power VCO design for medical implants. This oscillator was implemented to provide the frequency deviation of frequency-shift-keying (FSK) modulation in implantable radio-frequency (RF) transceivers.How are wireless RF transceivers used in medical applications?Implantable medical sensors keep short-range wireless communication a challenging and hot research topic for the monitoring and detection of various health parameters, such as temperature, pressure, oxygenation, seizures and other signs of diseases. For instance, the continuous monitoring of oxygen levels of the blood for patients suffering from epilepsy may help locate, treat and even prevent the emergence of seizures, thanks to low-power, high-data-rate wireless links. Even monitoring the behaviour of freely-moving animals, where light and free-running circuits are demanded, offers the chance to extract medical information in realistic conditions.Why is it so challenging to build wireless RF transceivers for implantable sensors?The constraints of the RF transceivers for wireless body area networks are different from conventional ones. The two main challenges are reducing the size and the power consumption of the transmitter front-end to maintain real-time, long-term data transmission. Thanks to CMOS technology, the small size of the wireless interface helps to get rid of most of the external bulky components. In practice, since the implanted devices have limited power storage, different circuits and systems design techniques have to be invented to achieve an energy-efficient communication interface. The battery cell of the current power-hungry wireless transmitter in existing medical implants has to be recharged or replaced through frequent medical surgeries, which is not adequate, and the transmitter power budget may be notably reduced.What motivated you to develop a new low power VCO?As reported in the literature, crystal-less and inductor-less voltage-controlled oscillators (VCOs) help to implement the fundamental building blocks in implantable and VLSI systems with different frequency ranges. Specifically, in widely-used binary FSK-based transceiver architectures, the carrier frequency gets shifted up and down by a frequency deviation to distinguish between the signal levels low (0) and high (1). Such frequency deviation is usually defined by differential quadrature signals that can be generated by cascaded flip-flops acting as a frequency divider fed by an external reference clock or crystal oscillators. However, crystal oscillators may not be suitable for integrated and implantable sensors. The frequency may also vary, depending on the application and the available channel bandwidth. As a result, a quadrature VCO (QVCO) is designed to provide the required quadrature signals with specific characteristics to help realise the target energy-efficient FSK-based RF transceiver.Previous VCOs with such frequency range did not offer all the desired features including consuming small current and providing rail-to-rail, differential and quadrature versions of the signal at the same time.Can you describe the design of the VCO reported in your Electronics Letters paper?Our low-power differential rail-to-rail QVCO is composed of a 2-stage quadrature oscillator, where each stage is acting similar to a bi-stable circuit triggered by the output of the other one. This can be considered as a ring oscillator where no external clock signal is required and facilitates the integration of the oscillator; therefore, it only needs a small silicon area and a low current consumption. The start-up circuit is also designed to initiate the oscillation and is then automatically disconnected from the oscillator's circuit so as not to affect the oscillation.Single-ended variable-frequency ring-oscillators have been already presented with similar frequency and power range to the new QVCO. However, this is the first design of a fully-integrated low-power QVCO that is capable of providing rail-to-rail, differential and quadrature versions of a variable-frequency signal, simultaneously.When will you have a prototype?The first prototype of the designed QVCO is in the fabrication and packaging process and is due to be tested soon. Challenges include the parasitic capacitance and resistance within the test-setup, as well as probing itself, which may play major roles in changing the behaviour of the expected output signals. Besides, producing the input signals – including the ones for enabling or disabling different blocks – with proper falling and rising time and providing the power supply, will have to be carefully planned.We plan to use a functional implemented QVCO as an actual block to characterise the target implemented RF transceiver. More controlling signals may be added in future prototypes so that it can be used for several communication applications with different frequency and current ranges, such as providing the optimum carrier frequency for wireless power transfer using inductive links.How do you see this technology developing in the future?Wireless link technologies are increasing, in particular in implantable medical devices, where very low-power circuits and systems are necessary. Nowadays, a typical wireless link may occupy up to 90% of the device's total power consumption. Recent deep sub-micron technologies look promising in allowing the improvement of the speed with much lower power leakage and smaller size, which will help designers to improve the performance of the wireless links of these devices.To help this field progress, we would like to see better connection of academic and industrial researchers, as shared access to various deep sub-micron technologies may widen the window to develop new ideas in circuits and systems designs. 

New research, led by the University of Southampton, has demonstrated that a nanoscale device, called a memristor, could be the 'missing link' in the development of implants that use electrical signals from the brain to help treat medical conditions.Monitoring neuronal cell activity is fundamental to neuroscience and the development of neuroprosthetics – biomedically engineered devices that are driven by neural activity. However, a persistent problem is the device being able to process the neural data in real-time, which imposes restrictive requirements on bandwidth, energy and computation capacity.In a new study, published in Nature Communications, the researchers showed that memristors could provide real-time processing of neuronal signals (spiking events) leading to efficient data compression and the potential to develop more precise and affordable neuroprosthetics and bioelectronic medicines.Memristors are electrical components that limit or regulate the flow of electrical current in a circuit and can remember the amount of charge that was flowing through it and retain the data, even when the power is turned off.Lead author Isha Gupta, Postgraduate Research Student at the University of Southampton, said: "Our work can significantly contribute towards further enhancing the understanding of neuroscience, developing neuroprosthetics and bio-electronic medicines by building tools essential for interpreting the big data in a more effective way."The research team developed a nanoscale Memristive Integrating Sensor (MIS) into which they fed a series of voltage-time samples, which replicated neuronal electrical activity.Acting like synapses in the brain, the metal-oxide MIS was able to encode and compress (up to 200 times) neuronal spiking activity recorded by multi-electrode arrays. Besides addressing the bandwidth constraints, this approach was also very power efficient – the power needed per recording channel was up to 100 times less when compared to current best practice.Co-author Dr Themis Prodromakis at the University of Southampton said: "We are thrilled that we succeeded in demonstrating that these emerging nanoscale devices, despite being rather simple in architecture, possess ultra-rich dynamics that can be harnessed beyond the obvious memory applications to address the fundamental constraints in bandwidth and power that currently prohibit scaling neural interfaces beyond 1,000 recording channels."

Researchers at the University of Alabama at Birmingham have found a novel and practical way to combat malicious attacks on motion sensors inside mobile devices.In a study published in proceedings of the 9th Association for Computing Machinery Conference on Security & Privacy in Wireless and Mobile Networks, associate professor Nitesh Saxena, Ph.D., and Ph.D. students Prakash Shrestha and Manar Mohamed have created a way to defend mobile device users against motion-based touchstroke leakage with the injection of noise.Previous research shows that, much like the way a hacker can covertly capture inputs made from a regular computer keyboard, it is also possible to capture a user's inputs on a touchscreen. Currently, motion sensors on Android devices can be accessed by any application downloaded to the device, without a user's being prompted to give permission. By tricking a user into unknowingly downloading a malicious program, hackers could obtain sensitive information like passwords and PINs by tracking the vibrations made from the touchscreen and decoding the movements based on a keyboard's layout. Given the accuracy rate of this type of attack, mobile security experts consider it a significant threat to user privacy and are exploring methods to combat it."Most mobile platforms have established a sensor security access control model," Saxena said. "Android follows a model where read access to many sensitive sensors, like a phone's camera or microphone, is very restrictive or requires special permissions granted by the user. However, the read access to other sensors, like inertial sensors, is not restricted because Android may not consider these sensors explicitly sensitive. This openness in the Android sensor security architecture has given rise to potentially significant threat of motion-based side channel attacks."By utilizing a recently developed framework called SMASheD (Sniffing and Manipulating Android Sensor Data), initially created as a malicious application, the study's authors built a defense mechanism called Slogger that can be used to thwart sensor-based touchstroke logging attacks. As a user enters sensitive information, Slogger transparently inserts noisy sensor readings in order to obscure the original readings. Slogger works in the background of a device and is completely unnoticeable to a user and other trusted applications. It can be installed through the Android Debug Bridge, without the need to root the device or change its operating system.To test Slogger's effectiveness, the authors compromised an Android device using two of the latest touchstroke logging algorithms developed for touchstroke detection and inference. During this type of attack, the start and end points of a user's taps are monitored. With data recorded by the accelerometer, a hacker could determine whether a user is holding the device vertically or horizontally. They can also predict what areas of the screen were tapped by applying machine learning tools. Later, by mapping the predicted areas with the standard keyboard layout, a hacker can determine the series of taps.After installing the malicious application, the authors also installed Slogger. Upon being installed, Slogger prompts the user to do a series of typing tests, holding the device in various positions. This allows Slogger to learn the range of the sensor values based on the user's typing style. The user types while holding the phone in his or her hand and while it is lying on a flat surface. The values are later used to set the range of values for injecting noise during an attack."During the evaluation phase, we implemented Slogger in such a way that, whenever the user launches the application used for the attack, a noise inject request is sent to the Slogger server," Saxena said. "When the user closes the application, a request to stop Slogger is sent. The application can also be updated to send an inject request whenever the keyboard is running or whenever a user is entering sensitive information."Slogger searches for system files related to motion sensors such as an accelerometer or gyroscope, and injects noise until it receives a request to stop, like when the application being used for the malicious attack is closed. Without Slogger, the touchstroke detector had an 85 percent rate of accuracy. Once the Slogger application was enabled, the touchstroke detector was unable to detect any touchstrokes. During the touchstroke inference test, there was a 90 percent accuracy rate without Slogger. Slogger was able to reduce inference accuracy to 56 percent while the device lay on a flat surface. While the user held the device, inference accuracy was reduced by more than 20 percent.During the evaluation, the authors discovered Slogger was also highly effective in minimizing touchstroke leakage even when more than one motion sensor is leveraged by an attacker. 

Imec, the Belgian nanoelectronics research center, will present at this week's 'CMOS Image Sensors for High Performance Applications' workshop in Toulouse (France) a prototype of a high-performance, time-delay-integration (TDI) image sensor. The image sensor is based on imec's proprietary embedded charge-coupled device (CCD) in CMOS technology. Imec developed and fabricated the sensor for the French Space Agency, CNES, which plans to utilize the technology for space-based earth observation.  The prototype image sensor combines a light-sensitive, CCD-based TDI pixel array with peripheral CMOS readout electronics. By integrating CCD with CMOS technology, imec combined the best of both worlds. The CCD pixel structure delivers low-noise TDI performance in the charge domain, while CMOS technology enables low-power, on-chip integration of fast and complex circuitry readouts.A TDI imager is a linear device that utilizes a clever synchronization of the linear motion of the scene with multiple samplings of the same image, thereby increasing the signal to noise ratio. CCDs fit extremely well with the TDI application since they operate in the charge domain, enabling the movement of charges without creating excess noise. By combining the TDI pixels array with CMOS readout circuitry on the same die, imec produced a camera-on-a-chip or system-on-a-chip (SOC) imager, which reduces the overall system complexity and cost. The CMOS technology enables on-chip readout electronics, such as clock drivers and analog-to-digital convertors (ADCs), operating at higher speeds and lower power consumption not possible with traditional CCD technology.The prototypes were fabricated using imec's 130nm process with an additional CCD process module. An excellent charge transfer efficiency of 99.9987 % has been measured ensuring almost lossless transport of charges in the TDI array, and guaranteeing high image quality. Imec's specialty imaging platform combines custom design (i.e., specialized pixels, high-performance readout circuits and chip architectures) with optimized silicon processing, such as dedicated implants and backside thinning, to achieve high-end specialized imagers.  

At SPIE Photonics West, imec will present a new set of snapshot hyperspectral CMOS image sensors featuring spectral filter structures in a mosaic layout, processed per-pixel on 4x4 and 5x5 'Bayer-like' arrays.Imec's hyperspectral filter structures are processed at wafer-level on commercially available CMOS image sensor wafers, enabling extremely compact, low cost and mass-producible hyperspectral imaging solutions. This paves the way to multiple applications ranging from machine vision, medical imaging, precision agriculture to higher volume industries such as security, automotive and consumer electronic devices."Imec's latest achievements in hyperspectral imaging emphasize how our promising technology has become an industrially viable solution for a number of applications," said Andy Lambrechts, program manager at imec. "The new mosaic architecture, and extended spectral range, brings unique advantages compared to our previously announced hyperspectral linescan sensors for applications in which scanning would not be practical. It enables spectral imaging in a truly compact, tiny form-factor, that can even be scaled to handheld devices. From the technology standpoint, we have now successfully demonstrated linescan and tiled sensors, in which spectral filters cover many pixels, to mosaic sensors, in which filters vary from pixel to pixel. At the same time, the spectral range is extended and now covers down to 470nm."The newly developed mosaic sensors feature one spectral filter per pixel, arranged in mosaics of 4x4 (16 spectral bands) or 5x5 (25 spectral bands) deposited onto a full array of 2 Million pixels 5.5µm size CMOSIS CMV2000 sensor. Two versions of the mosaic hyperspectral image sensors have been developed:one 4x4 mosaic with 16 bands in the 470-630nm (visible range)one 5x5 mosaic with 25 bands in the 600-1000nm range (Visible – NIR range)"Imec's hyperspectral imaging sensors (100bands linescan, 32bands tiled and 16/25bands mosaic designs) are off-the-shelf, commercially available engineering sample sensors that we developed to address the fragmented machine vision market and to trigger interest for this unique technology from potential end-users in other industries," explained Jerome Baron, business development manager at imec. "We also offer customized spectral filtering solutions for companies that are already familiar with the technology and interested in developing proprietary solutions with a specific performance in terms of speed, compactness, spatial versus spectral resolution, bands selection, or cost."Related products:ANPVC5030ANPVC2260ANPVC1470ANPVC1210