The Kynix Blog - FPGA

Warm hints: The word in this article is about 4000 words and  reading time is about 20 minutes.SummaryThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of system clock and the delay of clock to ensure the stability of design. CoreClock in FPGA designPurposeDetermining the influencing factors of clock to ensure the stability of designEnglish nameField Programmable Gate ArrayCategoryDigital electronic circuitFunctionCreating digital circuitsFeatureTotally up to the designer to create a bit fileCatalogsCatalogsⅠ. What is Setup time and Hold timeⅢ. Analyzing with the help of timing diagram3. The composition of the state machine1. Synchronization between single bits and each pulse transmitted has at least 1 cycle width1. Setup timeⅣ. How to increase the clock working frequencyⅤ. An example showing a good method for state machine design2. The input pulse could be less than a synchronous circuit under a clock cycle width 2. Hold time1. Changing the line type for circuit wiringⅥ. The introduction of state machine Ⅱ. A basic model of synchronous design using a single clock2. Splitting the combinational logicⅦ. What we should pay attention when designing the clock in FPGA  IntroductionⅠ. What is Setup time and Hold timeThe clock is the most important and special signal in the entire circuit. The movement of most of the devices in the system is performed on the edge of the clock. This requires that the delay of the clock signal is very small, otherwise it may cause an error in the timing logic. Therefore, it is very important for the design of FPGA to determine the factors of the system clock and the delay of the clock to ensure the stability of the design.Learn how a clock drives all sequential logic in FPGA, from Flip-Flops to Block RAMs; The clock tells you how fast you can run your FPGA;This video demonstrates how to properly deal with multiple clock domains inside your design.1. Setup timeSetup time(Tsu) is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.2. Hold timeHold time(Thd) is defined as the minimum amount of time after the clock's active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.Figure 1 Shows setup time and hold timeFigure 2 If data will change in tsu then it will cause setup violation and if data will change in thd then it will cause hold violation  DtailⅡ. A basic model of synchronous design using a single clockIn the same module of FPGA design, it often contains the combinational logic and the sequential logic. In order to guarantee the data in this logic interface can be processed steadily, then figuring out the concept of setup time and hold time is very important. Then we could be able to think about this following question:Figure 3 Shows a basic model of synchronous design using a single clockTco: Delay of the data output of the trigger;Tdelay: Delay of the combinational logic;Tsetup: The trigger's setup time;Tpd: Delay of the clock (negligible).T: clock cycleT3: D2 setup timeT4: D2 hold timeIf the first trigger D1 has a maximum setup time of T1max and a minimum of T1min, the combinational logic has a maximum delay of T2max and a minimum of T2min. The question is what conditions setup time T3 and hold time T4 of the second trigger D2 should be met, or what the maximum clock cycle given T3 and T4. This is the thing must be carefully considered in the process of design, because only by clarifying this issue can we ensure that the delay of the  combinational logic designed meets the requirements.Ⅲ. Analyzing with the help of timing diagramNow let us analyze this question with the help of timing diagram: let the input of the first flip-flop be D1, the output be Q1; the input of the second flip-flop be D2, the output be Q2;Given the clock is uniformly sampled on the rising edge, for ease of analysis we would discuss two cases, the first one: Assume that the delay of the clock Tpd is zero, which in fact, is often met in the FPGA design where the unified system clock it is generally adopted and the clock be input through the global clock pin, therefore the internal clock delay can be completely ignored. In this case, it is not necessary to consider the hold time, because each data maintains one clock tick while there is also delay line, that is, the delay based on CLOCK is much smaller than the delay based on data, so the hold time can meet the requirement. The setup time is what we should care about. If the setup time D2 meets the requirement, the timing diagram should be as shown as Figure 4.Figure 4 Shows the timing chart that meets the requirementsFrom the figure 4 we can see:T-Tco-Tdelay>T3That is Tdelay< T-Tco-T3During the setup time D2, the signal can reach D2 through the combinational logic D1, i.e. the data is already in Tsup before the second CLK arrive.Then it meets the requirement of setup time, where T as the clock period, the second flip-flop can pick up D2 on the rising edge of the second clock in this case. {D1 => setup time => hold time => trigger data output delay => combinational logic delay => D2 => ...}If the delay time of the combinational logic is too largeT-Tco-Tdelay < T3 (Tcox<D2 setup time)Then it will not meet the requirements. The second trigger will pick up an unstable state on the rising edge of the second clock, as shown in Figure 5, then the circuit will not work properly.Figure 5 The delay time of the combinational logic is too large to meet the requirementsSo you can deriveT - the Tco - T2max > = T3This is the setup time for D2.From the timing diagram above, it also can be seen that the setup time and hold time of D2 are not related to the setup and hold time of D1, except the combinational logic in front of D2 and the data transmission delay of D1. This is also a Very important conclusion, which shows that the delay has no additive effect.However, if there is a delay in the clock instead, the hold time must be considered in this case, together with the setup time. Most clocks with large delays are designed using asynchronous clocks, which is difficult to guarantee the data synchronization, so it is rarely used in actual designs. At this point, if the setup time and hold time all meet the requirements, you will see the output timing as shown in Figure 6.Figure 6. Clock has a delay but meets the timingIt can be easily seen from figure 5 that the Tpd is relaxed for the setup time, so the setup time of D2 must meet the requirements:Tpd+T-Tco-T2max>=T3 (T3 is the setup time of D2, T2max is the maximum delay of  combinatorial logic, Tpd is the clock delay)As shown in the FIG. 6, since the sum of setup time and hold time is a stable clock period (T), if the clock has a delay and the data delay is small, then the setup time will increase inevitably,  and the decrease of hold time goes with it. If it is reduced to not meet the requirement of hold time D2 , the correct data cannot be collected.That is T-(Tpd-Tco-T2min)T-(Tpd+T-Tco-T2min)>=T4 i.e. Tco+T2min-Tpd>=T4 (D2 hold time )From the formula above we could also figure out that if Tpd = 0, that is to say the delay of the clock is 0, then the same requirements goes with Tco + T2min> T4, however in practical applications the delay of T2 i.e. the delay of line is much larger than the trigger's hold time T4, it becomes not necessary to take the hold time into consideration.Figure 7 The clock has a delay and the hold time does not meet requirementsIn summary, if you do not consider the delay of the clock, the only thing you need to care about is the setup time, or the hold time instead. Then let us think about in FPGA design, how to increase the working clock in the synchronous system. AnalysisⅣ. How to increase the clock working frequencyFrom the above analysis, we can see that the requirements of setup time T3 for the D2 in the synchronization system is as follows:T-Tco-T2max>=T3So it is easy to derive:T>=T3+Tco+T2maxwhere T3 is the setup time Tset of D2, and T2 is the delay time of the combinational logic. In a design, T3 and Tco are both fixed values determined by the device, the only factor that we could control is the input delay of the combination logic T2. Therefore, by reducing T2 as much as possible, the clock working frequency can be increased. In order to achieve the reduction of T2 in the design, there are different comprehensive methods we can use.1. Changing the line type for circuit wiringAltera devices, for example, there are many bars in the quartus timing closure floorplan, so we can slice and dice them into rows and columns: Each bar represents 1 LAB, each LAB has 8 or 10 LEs in. The relationship of their routing delay is as follows: the same LAB (fastest) < the same row and column < different row and column. We could add appropriate constraints to the synthesizer (this should be given appropriate, generally 5% margin adding, for example, if the circuit works at 100Mhz, then adding constraints to 105Mhz is sufficient, because the excessive constraint could do a bad effect instead, and greatly increases the integration time) to make the relevant logic circuit wiring be placed as close as possible, thereby reducing the routing delay.2. Splitting the combinational logicSince the general synchronous circuits are more than a?single?stage latch (as shown in Figure 9), and to make the circuit stable, the clock period must meet the maximum delay requirement, and the maximum?delay of the longest path can be shortened before the operating frequency of the circuit be increased.As shown in Figure 8, we can decompose the larger combinatorial logic into smaller blocks and insert flip-flops in the middle, which can increase the operating frequency of the circuit. This is also the basic principle of the so-called "pipelining" technology.For the upper part of Figure 9, its clock frequency is subject to the delay of the second larger combinational logic. By appropriately distributing the combinational logic, excessive delay between the two flip-flops can be avoided and speed bottlenecks can be eliminated.Figure 8 Splitting combination logicFigure 9 Transferring Combination LogicHow to split the combinatorial logic in design, the better method should be accumulated in practice, but some good design ideas and methods also need to be mastered. We know that at present most of the FPGAs based on 4-input LUTs, if an output criteria corresponding is more than four inputs, then the multiple LUT cascade will be needed, thus introducing the delay of one-stage combinational logic. That is we want to reduce the number of combinational logic, the logic is nothing more than to make the input conditions as few as possible, so that less multiple LUT cascade need to be use, thereby reducing the time delay caused by combinational logic.The pipelining that we usually hear is a way to increase the operating frequency by splitting a large combinational logic (in the middle of which a singer or multiple stages of D flip-flops are inserted, thereby reducing the number of combinatorial logic between registers) to a smaller one. For example, a 32-bit counter, with a very long carry chain, will inevitably reduce the operating frequency, so we can split it into a 4-bit and a 8-bit one, whenever the 4-bit counter counts to 15 and triggers an 8-bit one, which enable the counter to be split and increases the operating frequency.Just as the same, large counters are generally moved out of the state machine, because if they, with usually more than 4 inputs, are used as state transition criteria with other conditions, they will increase the multiple LUT cascade, and then increasing the combination logic.Taking a 6-input counter as an example, we wanted to make a state transition after the counter counted to 111100, now because we put the counter out of the state machine, when it counts to 111011, a signal of "enable" is generated and then trigger the state transition, which obviously reduces the combinatorial logic.3. The composition of the state machineThe state machine generally contains three modules:An output moduleA module that determines what the next state isA module that saves the current stateThe logic used to form these three modules is also different. The output module usually contains both combinatorial logic and sequential logic; the module that determines the next state is usually composed of combinatorial logic; and the module that saves the current state is usually composed of sequential logic. The relationship between these three modules is shown in Figure 10.Figure 10 The composition of the state machineⅤ. An example showing a good method for state machine designThat is why when writing the state machine, the state machine is always divided into three parts according to these three modules. The following example shows a good method of state machine design: -----------------------------------------------------*/module arbiter2 (                    clock , // clock                    reset , // Active high, syn reset                    req_0 , // Request 0                    req_1 , // Request 1                    gnt_0 ,                    gnt_1                );//-------------Input Ports-----------------------------input    clock ;input    reset ;input    req_0 ;input    req_1 ;//-------------Output Ports----------------------------output    gnt_0 ;output    gnt_1 ;//-------------Input ports Data Type-------------------wire    clock ;wire    reset ;wire    req_0 ;wire    req_1 ;//-------------Output Ports Data Type------------------reg        gnt_0 ;reg        gnt_1 ;//-------------Internal Constants--------------------------parameter     SIZE = 3 ;parameter     IDLE = 3'b001 ,            GNT0 = 3'b010 ,            GNT1 = 3'b100 ;//-------------Internal Variables---------------------------reg        [SIZE-1:0] state ;        // Seq part of the FSMwire    [SIZE-1:0] next_state ;    // combo part of FSM //----------Code startes Here------------------------assign    next_state = fsm_function(req_0, req_1);//------------fsm_function--------------//function [SIZE-1:0] fsm_function;input     req_0;    //parameterinput     req_1;    //parameterbegin    case(state)        IDLE :                if (req_0 == 1'b1)                    fsm_function = GNT0;            else if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function = IDLE;        GNT0 :             if (req_0 == 1'b1)                fsm_function = GNT0;            else                fsm_function = IDLE;        GNT1 :            if (req_1 == 1'b1)                fsm_function = GNT1;            else                fsm_function =IDLE;        default : fsm_function = IDLE;        endcaseendendfunction always@(posedge clock)begin    if (reset == 1'b1)        state <= IDLE;    else        state <= next_state;end//----------Output Logic-----------------------------always @ (posedge clock)begin    if (reset == 1'b1)         begin        gnt_0 <= #1 1'b0;        gnt_1 <= #1 1'b0;        end    else         begin        case(state)            IDLE :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end            GNT0 :                 begin                gnt_0 <= #1 1'b1;                gnt_1 <= #1 1'b0;                end            GNT1 :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b1;                end            default :                 begin                gnt_0 <= #1 1'b0;                gnt_1 <= #1 1'b0;                end        endcase        endend // End Of Block OUTPUT_Endmodule Ⅵ. The introduction of state machineState machines are usually written in three segments to avoid excessive combinational logic.All we mentioned above shows how we could use the way of pipelining to split the combinational logic, but in some cases it is difficult for us to do that, and then what should we do?The state machine is such an example that we cannot add assembly line in the state decoding combinational logic. If there is a design of state machine with dozens of states, there is no doubt that its state decoding logic will be very large and this will be the critical path in the design. So what should we do?Just the same way, reducing the combinatorial logic. We can analyze the output of the state, reclassify and redefine them into a group of small state machines. By selecting the input (case statement) and triggering the corresponding small state machine, we can achieve a large state machine splitting into several small state machines. In the ATA6 specification (hard disk standard), there are about 20 kinds of input commands, and each piece of command corresponds to a variety of states. It is unthinkable to do it with a large state machine (nesting), however in the contrary, if you use the case statement to decode the command and trigger the corresponding state machine, in this way the module can run very fast.The key to increasing the operating frequency is to reduce the time delay from register to register, and the most effective method for reduction is to avoid large combinational logic, that is, to try to meet the four-input condition, reducing the number of LUT cascades, that’s mean that we could increase the working frequency by adding constraints, using a way of pipelining and splitting states.Ⅶ. What we should pay attention when designing the clock in FPGA1.Try to use only one clock in a module, and a module here means a module or an entity. In the design of multi-clock domain, it is better to have an extra special module for the isolation of clock domain. This allows the synthesizer to get a better results.2. Unless it is a low-power design, otherwise do not use the gated clock (gllobal Clock buffer such as IBUFG within FPGA) to control the input of clock edge of flip-flop, but use combinational logic and other timing logic (such as frequency divider) to generate signals used as the input of clock edge of flip-flop---all this is to reduce the instability of the design.3. Do not use the signals divided by counter as the clock of other modules, but  with the help of clock enable(CE). Otherwise, this clock-like manner is extremely unfavorable to the reliability of the design, and greatly increases the complexity of the static timing analysis .Ⅷ. Synchronization Between Different Clock DomainsIf two modules in a design using two respective operating clock, then at their interfaces there would emerge a phenomenon which called as Asynchronous Patterns. In order to ensure data correct processed, the two modules must be synchronized.There are usually two cases of different clock domains here (discrete clock source):1. the frequency of two clocks is different;2. the two clocks share a same frequency, but they are actually two separate clocks with no relation to the phase.Just as shown in the following two figures:Figure 11 The frequencies of two clocks are completely differentFigure 12 The frequencies of the two clocks are the same, but the phases are irrelevantThe data transmission between two clock domains usually adopts different synchronization methods according to different bit widths.1. Synchronization between single bits and each pulse transmitted has at least 1 cycle widthThis kind of synchronization is mainly used for the synchronization of some control signals. As shown in Figure 13 below:Figure 13 One bit synchronizer designThe following points are required to be explained for this synchronization:(1) synchronous circuit of figure 12 is actually called "one bit synchronizer", it can only be used for one bit asynchronous signal which must be wider than that of the Current stage’s clock, otherwise it may be unable to adopt this asynchronous signal.(2) why is the circuit in figure 13 can only be used in one bit asynchronous signals?When two or more asynchronous signals (control or address) simultaneously get into the current time domain and take control the circuit of current time domain, problems arise if these signals are all synchronized using the same circuit in FIG. 13. Skews has arisen between two or more asynchronous signals (control or address) due to connection delays or other delays, and then the skew is greatly enlarged via the synchronizer in Figure 13 when getting into the current time domain, or competition may caused and finally leading to an error in the time domain circuit.Figure 14 Problem-passing multiple control signals between clock domainsIf the asynchronous data bus is to enter the current time domain, the circuit in Figure 13 cannot be used either, because data change very randomly and the width of 0 or 1 has nothing to do with the clock pulse of the current time domain, so the circuit in Figure 13 may be unable to adopt the correct data.(3) Please note that the second trigger is not used for avoiding the occurrence of "metastable state", on the contrary, it can prevent the transmission of metastable state. In other words, once the first flip-flop becomes metastable (possibly), due to the second flip-flop, the metastability will not be transmitted to the circuit following.(4) The first-stage trigger has a metastable state, which means it will require a recovery time to stabilize again, or it is also called Withdrawal from metastable state. The recovery time plus the establishment time of the second-stage flip-flop (say more precisely, maybe also minus the clock skew) is less than or equal to the clock period, which can be easily satisfied. This is means thees two stages of flip-flop should be put together as close as possible, without any combinatorial logic between them or excessive skews to the clock, and then the second-stage flip-flop can adopt data stably and preventing the transmission of metastable state.(5) FF1 is the sampling output of FF2, so of course, what is output by FF1 is  what output by FF2, everything is the same except one cycle of delay. Note that “meta-stableit” means that once the data of FF1 enters, its electrical level would be indefinite and maybe incorrect. So although this method can prevent transmission of metastable state, it does not guarantee the data after the two-stage flip-flop is correct. Therefore, this kind of circuit always has a certain amount of fault-tolerance. This applies only to a some error-insensitive cases, but for other sensitive circuits, dual-port RAM or FIFO are better choices.2. The input pulse could be less than a synchronous circuit under a clock cycle width How is that possible? Has it not less than the original clock? For this case, the Feedback shown in Figure 15 below may usually be taken into consideration. The analysis of this circuit is as follows: Assume that the input data is high level, because the first flip-flop FF1 is high-level cleared, then all outputs should also be high and correctly adopted. On the other hand, if the input is low-level, data of FF1 would be forced to clear and the output level is zero, which ensures the correctness of the output.Figure 15 Synchronous circuit--input pulse may be less than one clock cycle width  Book SuggestionBuilding Embedded Systems: Programmable Hardware 1st ed. EditionThis is a book for embedded-system engineers and intermediate electronics enthusiasts who are seeking tighter integration between software and hardware. Those who favor the System on a Programmable Chip (SOPC) approach will in particular benefit from this book. Students in both Electrical Engineering and Computer Science can also benefit from this book and the real-life industry practice it provides.--Changyi GuDigital Integrated Circuit Design Using Verilog and Systemverilog 1st Edition, Kindle EditionFor those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. --Ronald W. MehlerPower Converters with Digital Filter Feedback Control 1st Edition, Kindle EditionThis book builds a bridge for moving a power converter with conventional analog feedback to one with modern digital filter control and enlists the state space averaging technique to identify the core control function in analytical, close form in s-domain (Laplace). It is a useful reference for all professionals and electrical engineers engaged in electrical power equipment/systems design, integration, and management.--Keng C. Wu Relevant information "Discussion on the influencing factors of clock in FPGA design"About the article "Discussion on the influencing factors of clock in FPGA design", If you have better ideas, don't hesitate to  write your thoughts in the following comment area. You also can find more articles about electronic semiconductor through Google search engine, or refer to the following related articles.To Solve the Problems of Cloud Skyrocket--Edge ProcessingFPGAs Power Facial Recognition Technology Was Issued by NECNew Software for C2000 MCUs Eliminates the FPGA in industrial designsCustomisable Ethernet switch designed for embedded applicationsMouser signs Intel FPGA board firm ReFLEX CES

TroublesAs the deployment of Industrial IoT systems continues to proliferate,the streams of data transferred to the cloud skyrockets, drastically increasing the cost for cloud computing.  SolutionIn order to meet this trouble, many systems designers are adopting edge computing,in which data processing is done close to the source like sensors in a bid to reduce data transfer,storage and processing costs,plus address a few other concerns over Cloud Computing,in particular security. What is Big DataBig Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Huge datacentres are required if you want to store Big Data.Big Data is a broad label for the growing amount of data generated by IoT devices and smart systems. For instance, some aircraft engines have more than 5,000 elements that are monitored at relatively high sample rates. Most of the data is transferred to a ground station for the real-time monitoring of the engine and for future R&D work. But this is only part of a growing trend. Most ‘smart’ systems produce vast amounts of data which needs to be processed immediately or be stored for subsequent processing. Cloud Computing's advantages and disadvantagesCloud Computing has a lot of advantages including cost efficiency (i.e. no need to invest in and maintain your own hardware), scalability, resource availability (for all your users irrespective of their geographic locations), lower latency (as you can specify servers that are closest to the relevant users/customers) and peace of mind in terms of back-ups. There are,however,some disadvantages also. The biggest of which is that no provider can guarantee 100% availability. Data security and privacy are also causes for concern, both on the cloud and for data in transit. Latency can be an issue for Big Data, and doing computationally intensive tasks on the cloud will increase the cost. Of these concerns the last two, in particular, can be negated through edge processing; i.e. performing much of the computationally intensive work near the source data. Benefits here include real-time or near-real-time data processing and reduced network traffic, as you need only transfer the product of the edge processing, thus resulting in lower Cloud Computing costs. Security and privacy can be improved by keeping the sensitive data (a.k.a. Hot Data) within the edge processing environment and only sending less sensitive (Cold) data to the cloud. FPGAs have the edgeThere are technologies that can be used for edge processing applications. These include the use of traditional CPUs (scoring high in terms of flexibility), application-specific processors (e.g. GPUs) and ASICs/SoCs (scoring high on performance). However, it is FPGAs that are slotting into most edge processing applications. Why is this so? Well, let’s consider the requirements. Edge processing needs to be high-performance and in this respect an FPGA can perform several different tasks in parallel. For example, consider executing many non-dependent computations (such as A=B+C, D=E+F and G=H+I). On a CPU, these would have to be performed sequentially, with each sum requiring a few clock cycles. In an FPGA, an array of adders could do the computations in parallel, possibly requiring only a single clock cycle. Power efficiency is essential too, as the end product may well be battery-powered. With an FPGA the function (design) need be the only circuit present, whereas the architecture of a CPU or GPU may not be fully utilized. Also, with an FPGA comes the benefit of reprogrammability. Higher security is afforded too because the edge processing functions are hard wired into the FPGA. It is also possible to encrypt the transaction bus and to even go as far as designing your own processor. ConnectingA prime example of where edge processing is extremely useful, and in which FPGAs can play a significant role, is within an embedded system in which data derived from images needs to be transferred. For example, in the automotive sector Advanced Driver Assistance Systems (ADAS) are under development to make driving safer, easier and more comfortable, and ADAS is regarded as a significant step towards fully autonomous cars. The data processed by an ADAS can be used to notify the driver of problems or to automatically trigger responses such as deceleration, braking and/or the execution of a manoeuvre. The data can also be useful outside the vehicle. Let's discuss the embedded vision system first though by considering an ADAS demo unit that was built for this year's Embedded Vision show in Santa Clara, California. The demo comprised a TySOM-2-7Z100 prototyping board (see figure 1) which includes a Xilinx Zynq XC7Z100 device and a TySOM-FMC-ADAS daughter board to interface with four 960 x 540 pixel cameras. The processing was shared between a dual-core ARM Cortex-A9 processor and FPGA logic (both of which reside within the Zynq device) and began with frame grabbing images from the cameras and applying an edge detection algorithm (‘edge’ here in the sense of physical edges, such as objects, lane markings etc.). This is a computational-intensive task because of the pixel-level computations being applied (i.e. more than 2 million pixels). To perform this task on the ARM CPU a frame rate of only 3 per second could have been realised, whereas in the FPGA 27.5 fps was achieved.This picture is a TySOM-2-7Z100 prototyping board. Mixed technology (like CPU and FPGA) boards are proving very popular for edge processing applications and for connecting with the cloud.  The ARM CPU was mainly used for superimposing detected edges over the initial camera images, colour-space conversions, the formation of a composite image (see main image) and outputting it to an HD buffer. The FPGA and CPU could also work together to recognise and distinguish between obstacles and pedestrians close to the car and to provide lane departure warnings. What goes upSending the processed data to the cloud for further processing and/or storage is then a relatively simple task. Firstly, an AWS account would be created along with an AWS IoT environment. Next, we would configure a Thing (seeing as it is the IoT) and download the public and private keys needed for secure communications with the cloud.The embedded C MQTT standard would be the ideal Software Development Kit (SDK), because it is secure and requires minimal bandwidth. An application would then be prepared to run on the ARM CPU to publish the data onto the cloud. Imagine a scenario,howevber,under which we have data from thousands of vehicles going to the cloud.Analysis of the data could be performed on the cloud and made available for traffic systems or highway maintenance organisations, for example. There may also be instances where data from the cloud feeds into an edge-processing application, in which case applications are also available from AWS. All in all,there are both advantages and disadvantages associated with cloud computing. And many of the disadvantages will be overcome though edge-processing that FPGAs are a particularly suitable activity.  Article provided by Farhad Fallah,an Application Engineer with EDA company AldecArticle edited by Kynix 

To help detect and prevent possible incidents at critical facilities and public venues, Intel technology is powering a face recognition engine that can rapidly and accurately identify people, even when they are moving and in a crowd. NEC relied on Intel Arria 10 field programmable gate arrays (FPGAs) operating on Intel Xeon processor–based servers to increase the performance of its NEC NeoFace facial recognition engine to a level where an individual can be identified smoothly from a high-resolution image with dozens of faces.  “Facial recognition in a moving crowd requires highly advanced techniques when compared to still images because these cameras are affected by many factors: camera location, image quality and lighting, along with the subject’s size, walking speed and face direction,” said Tadashige Kadoi, general manager of IoT Platform Development Division, NEC. “Intel FPGAs and their parallel processing capability help NEC to enable fast and accurate collection and processing of images from even 4K high-resolution remote cameras.” Intel FPGA acceleration technology played a role in a recent achievement for NEC. In March, NEC NeoFace was ranked Number 1 in almost all tests by the US National Institute of Standards and Technology (NIST) specifically for face-in-video evaluation. The NIST tests evaluated the accuracy of the technology in two real-life test scenarios including a test for entry-exit management at an airport passenger gate. It determined whether and how well the engine could recognise people as they walked through an area one at a time without stopping or looking at the camera. NEC's face recognition technology won first place with a matching accuracy of 99.2%. The error rate of 0.8% is less than one-fourth of the second place error rate. In the second test, the technology was asked to detect suspicious individuals at an indoor stadium. This test was conducted with an individual situated far from the camera, with their face direction changing frequently. NEC's face recognition technology won first place with an error rate half that of the second place error rate. To create the NeoFace Accelerator, NEC’s NeoFace facial recognition engine software IP is integrated into an Intel Arria 10 FPGA, keeping the same accuracy level while achieving higher performance in facial recognition than the previous solution. Intel teams also worked with NEC to enhance the performance of NeoFace data centre server technology. NEC NeoFace Accelerator includes not only the Intel Arria 10 FPGA, but also an Intel MAX 10 low-cost FPGA and Intel Enpirion power devices. Ref.KY32-EP1S60B956C6KY32-EP4CGX150DF27I7 

A software called DesignDRIVE Fast Current Loop that makes C2000 microcontrollers (MCUs) the first devices to push current-loop performance to less than 1 microsecond, has been introduced by Texas Instruments. Together, TI's C2000 MCU portfolio and DesignDRIVE software delivers System-on-Chip (SOC) functionality which simplifies drive control system development.       The DesignDRIVE Fast Current Loop software out performs traditional microcontroller (MCU)-based current-loop solutions and can simplify designs by eliminating the Field-Programmable Gate Array (FPGA) typically used for external current-loop control. Fast Current Loop software is a free update available for C2000 controlSUITE software.   TI's DesignDRIVE technology is a unified hardware and software platform that makes it easier for engineers to develop and evaluate solutions for a variety of industrial drive and servo topologies. As a key part of DesignDRIVE solutions, the Fast Current Loop software enables developers to achieve higher control performance while saving valuable board space and simplifying thermal considerations.     Features and benefits of TI's DesignDRIVE Fast Current Loop software   · Innovative subcycle Pulse-Width Modulation (PWM) update techniques significantly improve control-loop bandwidths to potentially triple the motor torque response. · A novel cycle-scavenging C2000 MCU needs only 460 nanoseconds for field-oriented control processing. · A new complex controller replaces traditional proportional integration control and facilitates greater stability at higher speeds. · Industrial drive systems designed with Fast Current Loop software on a C2000 MCU, like the TMS320F28379, delivers SOC functionality to reduce board space, complexity and overall cost.      Ref. KY32-TMS320F28379 KY362-C2000    

The introduction of the LDD-ES8, a customisable gigabit Ethernet switch module for industrial, commercial and building automation data services, has been announced by LDD Technology. The standard LDD-ES8 module is an 8 port unmanaged Ethernet Switch on a PC/104-Plus form factor intended for use in embedded applications. It features a high performance, low latency, switch able to handle full-rate gigabit packets on all ports simultaneously.Auto-negotiation allows each port to operate at 10/100/1000 Mbits with dual LEDs per port to indicate negotiated speed and link activity. Power is provided from the PC/104 stack or through a Molex Microclasp connector. The LDD-ES8 module is designed for fully independent operation but a USB port is provided to allow monitoring of port performance if required. Power consumption is typically 5W with all ports operating at 1 Gbit/sec.The LDD-ES8 Gigabit Ethernet switch was developed in response to a number of enquiries for custom designed products from customers who had been unable to find suitable off-the-shelf products which met their performance, footprint and end product life requirements.LDD Technology is able to offer an efficient and cost-effective customisation service in the event that customers require a design with a different number of ports or in a different form factor. The module has been designed using programmable FPGA technology which offers end users a further range of customisation options not normally found on competitive products based on dedicated devices with limited programmability.This allows customers the option of including the functionality of the standard Ethernet Switch into other designs which may require Ethernet switching as part of a more complex system with additional interfaces or processing being included in the FPGA as required.“Our LDD-ES8 Gigabit Ethernet Switch is an excellent example of how our extensive custom design experience for many different clients can be used to create a flexible standard solution for many applications” commented Malcolm Locke, Managing Director of LDD Technology. Ref:KY32-EP1S60B956C6KY32-XC7K325T-2FFG900CKY32-EPF8636ALC84-3