The Kynix Blog - Memory

A new, environmentally-friendly electronic alloy consisting of 50 aluminum atoms bound to 50 atoms of antimony may be promising for building next-generation "phase-change" memory devices, which may be the data-storage technology of the future, according to a new paper published in the journal Applied Physics Letters, which is produced by AIP Publishing.Phase-change memory is being actively pursued as an alternative to the ubiquitous flash memory for data storage applications, because flash memory is limited in its storage density and phase-change memory can operate much faster.Phase-change memory relies on materials that change from a disordered, amorphous structure to a crystalline structure when an electrical pulse is applied. The material has high electrical resistance in its amorphous state and low resistance in its crystalline state—corresponding to the 1 and 0 states of binary data.Flash memory has problems when devices get smaller than 20 nanometers. But a phase-change memory device can be less than 10 nanometers—allowing more memory to be squeezed into tinier spaces. "That's the most important feature of this kind of memory," said Xilin Zhou of the Shanghai Institute of Microsystem and Information Technology at the Chinese Academy of Sciences. Data can also be written into phase-change memories very quickly and the devices would be relatively inexpensive, he added.So far, the most popular material for phase-change memory devices contains germanium, antimony, and tellurium. But compounds with three elements are more difficult to work with, Zhou said."It's difficult to control the phase-change memory manufacturing process of ternary alloys such as the traditionally used germanium-antimony-tellurium material. Etching and polishing of the material with chalcogens can change the material's composition, due to the motion of the tellurium atoms," explained Zhou.Zhou and his colleagues turned to a material with just two elements: aluminum and antimony. They studied the material's phase-changing properties, finding that it's more thermally stable than the Ge-Sb-Te compound. The researchers discovered that Al50Sb50, in particular, has three distinct levels of resistance—and thus the ability to store three bits of data in a single memory cell, instead of just two. This suggests that this material can be used for multilevel data storage."A two-step resistance drop during the crystallization of the material can be used for multilevel data storage (MLS) and, interestingly, three distinct resistance levels are achieved in the phase-change memory cells," Zhou says. "So the aluminum-antimony material looks promising for use in high-density nonvolatile memory applications because of its good thermal stability and MLS capacity."  

Japan's Toshiba is teaming up with US chip giant SanDisk to produce a "3D" memory chip they hope will allow users to save up to 50 hours of ultra-high definition video.In a deal worth a reported 500 billion yen ($4.84 billion) the companies will build a factory to make flash memory consisting of several layers of semiconductors stacked together to give as much as a terabyte—1,000 gigabytes—of storage.That is around 16 times bigger than the largest 64-gigabyte Toshiba memory currently available in smart phones and tablet devices.Toshiba will demolish its existing plant in Japan to build a new facility that will house production apparatus using technologies from both firms and which the firms hope will start operating in 2016, a statement said."In about five years (from the planned start of the factory), we would like to produce one-terabyte products," said a Toshiba spokeswoman.The plan comes at a time of increasing competition among the world's technology firms to meet demand for ever-higher capacity memory chips for consumers increasingly using mobile devices such as smart phones, tablet computers and wearable gadgets.The spread of high-definition video, with so-called 4K screens at the leading edge, is boosting demand for computing memory to store content."Small, high-capacity memories can of course be applied to smartphones, but they could also be used for wearable devices," the Toshiba spokeswoman said.Manufacturers have traditionally competed with regular chips by trying to make the physical object smaller.Toshiba, along with major rivals such as Samsung, believe they are reaching the physical limit, and are shifting toward 3D memories, where layering—effectively a third dimension—is used to boost the capacity of objects the same size.Yasuo Naruke, Toshiba senior vice president, said in a statement: "Our determination to develop advanced technologies underlines our commitment to respond to continued demand (for) flash memory."SanDisk president and chief executive Sanjay Mehrotra said the plant "will advance our leadership in memory technology into the 3D... era". 

In a word first, researchers from Tohoku University have successfully developed a technology to stack magnetic tunnel junctions (MTJ) directly on the vertical interconnect access (via) without causing deterioration to its electric/magnetic characteristics. The via in an integrated circuit design is a small opening that allows a conductive connection between the different layers of a semiconductor device. This new discovery will be particularly significant in reducing the chip area of spin-transfer torque magnetic random access memory (STT-MRAM), making its commercialization more practical. The team led by Professor Tetsuo Endoh, Director of the Center for Innovative Integrated Electronic Systems (CIES), focused on reducing the memory cell area of STT-MRAMs in order to lower manufacturing costs, making them competitive with conventional semiconductor memories like dynamic random access memory (DRAM). Because MTJs use magnetic properties, the quality of the surface between the MTJ and its lower electrode is important. If the surface area is not smooth, the electric/magnetic characteristics of the MTJ will degrade. For this reason, placing an MTJ directly on the via holes in STT-MRAMs has been avoided until now, although it increases the size of the memory cell. Endoh's group has tackled the issue by developing a special polishing process technology to prevent any interference between the MTJ and its lower electrode. The technology's effectiveness was successfully verified by an experiment using single-MTJ test chips. To further test the success of this development, a 2-Mbit STT-MRAM test chip integrating the new technology has been designed to verify the space needed for the integrated circuits—this includes more than 1million MTJs. "Not only does this test chip show a 70% improvement in its memory bit yield compared to standard STT-MRAM, but its memory cell area is reduced by 30%," says Endoh. "It will be very effective for reducing the chip area of MRAM." CIES develops material, process, circuit and test technologies in integrated electronic systems. The center's main focus is on developing high-performance, low-power technologies for a more energy-efficient society.    

In today's computer chips, memory management is based on what computer scientists call the principle of locality: If a program needs a chunk of data stored at some memory location, it probably needs the neighboring chunks as well.But that assumption breaks down in the age of big data, now that computer programs more frequently act on just a few data items scattered arbitrarily across huge data sets. Since fetching data from their main memory banks is the major performance bottleneck in today's chips, having to fetch it more frequently can dramatically slow program execution.This week, at the International Conference on Parallel Architectures and Compilation Techniques, researchers from MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL) are presenting a new programming language, called Milk, that lets application developers manage memory more efficiently in programs that deal with scattered data points in large data sets.In tests on several common algorithms, programs written in the new language were four times as fast as those written in existing languages. But the researchers believe that further work will yield even larger gains.The reason that today's big data sets pose problems for existing memory management techniques, explains Saman Amarasinghe, a professor of electrical engineering and computer science, is not so much that they are large as that they are what computer scientists call "sparse." That is, with big data, the scale of the solution does not necessarily increase proportionally with the scale of the problem."In social settings, we used to look at smaller problems," Amarasinghe says. "If you look at the people in this [CSAIL] building, we're all connected. But if you look at the planet scale, I don't scale my number of friends. The planet has billions of people, but I still have only hundreds of friends. Suddenly you have a very sparse problem."Similarly, Amarasinghe says, an online bookseller with, say, 1,000 customers might like to provide its visitors with a list of its 20 most popular books. It doesn't follow, however, that an online bookseller with a million customers would want to provide its visitors with a list of its 20,000 most popular books.Thinking locallyToday's computer chips are not optimized for sparse data—in fact, the reverse is true. Because fetching data from the chip's main memory bank is slow, every core, or processor, in a modern chip has its own "cache," a relatively small, local, high-speed memory bank. Rather than fetching a single data item at a time from main memory, a core will fetch an entire block of data. And that block is selected according to the principle of locality.It's easy to see how the principle of locality works with, say, image processing. If the purpose of a program is to apply a visual filter to an image, and it works on one block of the image at a time, then when a core requests a block, it should receive all the adjacent blocks its cache can hold, so that it can grind away on block after block without fetching any more data.But that approach doesn't work if the algorithm is interested in only 20 books out of the 2 million in an online retailer's database. If it requests the data associated with one book, it's likely that the data associated with the 100 adjacent books will be irrelevant.Going to main memory for a single data item at a time is woefully inefficient. "It's as if, every time you want a spoonful of cereal, you open the fridge, open the milk carton, pour a spoonful of milk, close the carton, and put it back in the fridge," says Vladimir Kiriansky, a PhD student in electrical engineering and computer science and first author on the new paper. He's joined by Amarasinghe and Yunming Zhang, also a PhD student in electrical engineering and computer science.Batch processingMilk simply adds a few commands to OpenMP, an extension of languages such as C and Fortran that makes it easier to write code for multicore processors. With Milk, a programmer inserts a couple additional lines of code around any instruction that iterates through a large data collection looking for a comparatively small number of items. Milk's compiler—the program that converts high-level code into low-level instructions—then figures out how to manage memory accordingly.With a Milk program, when a core discovers that it needs a piece of data, it doesn't request it—and a cacheful of adjacent data—from main memory. Instead, it adds the data item's address to a list of locally stored addresses. When the list is long enough, all the chip's cores pool their lists, group together those addresses that are near each other, and redistribute them to the cores. That way, each core requests only data items that it knows it needs and that can be retrieved efficiently.That's the high-level description, but the details get more complicated. In fact, most modern computer chips have several different levels of caches, each one larger but also slightly less efficient than the last. The Milk compiler has to keep track of not only a list of memory addresses but also the data stored at those addresses, and it regularly shuffles both around between cache levels. It also has to decide which addresses should be retained because they might be accessed again, and which to discard. Improving the algorithm that choreographs this intricate data ballet is where the researchers see hope for further performance gains."Many important applications today are data-intensive, but unfortunately, the growing gap in performance between memory and CPU means they do not fully utilize current hardware," says Matei Zaharia, an assistant professor of computer science at Stanford University. "Milk helps to address this gap by optimizing memory access in common programming constructs. The work combines detailed knowledge about the design of memory controllers with knowledge about compilers to implement good optimizations for current hardware."  

The current memory landscape spans from venerable DRAM to hard disk drives to ubiquitous flash. But in the last several years PCM has attracted the industry's attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density. For example, PCM doesn't lose data when powered off, unlike DRAM, and the technology can endure at least 10 million write cycles, compared to an average flash USB stick, which tops out at 3,000 write cycles. This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the Internet of Things. Applications IBM scientists envision standalone PCM as well as hybrid applications, which combine PCM and flash storage together, with PCM as an extremely fast cache. For example, a mobile phone's operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing for time-critical online applications, such as financial transactions. Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations. How PCM Works PCM materials exhibit two stable states, the amorphous (without a clearly defined structure) and crystalline (with structure) phases, of low and high electrical conductivity, respectively. To store a '0' or a '1', known as bits, on a PCM cell, a high or medium electrical current is applied to the material. A '0' can be programmed to be written in the amorphous phase or a '1' in the crystalline phase, or vice versa. Then to read the bit back, a low voltage is applied. This is how re-writable Blue-ray Discs store videos. Previously scientists at IBM and other institutes have successfully demonstrated the ability to store 1 bit per cell in PCM, but today at the IEEE International Memory Workshop in Paris, IBM scientists are presenting, for the first time, successfully storing 3 bits per cell in a 64k-cell array at elevated temperatures and after 1 million endurance cycles. "Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry," said Dr. Haris Pozidis, an author of the paper and the manager of non-volatile memory research at IBM Research - Zurich. "Reaching three bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash." To achieve multi-bit storage IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes. More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell's electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell's stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility. "Combined these advancements address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity and endurance cycling," said Dr. Evangelos Eleftheriou, IBM Fellow. The experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 μm × 800 μm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90 nm CMOS baseline technology. Source from IBM