The Kynix Blog - Memory

Toshiba Memory has announced development of the world’s first BiCS FLASH three-dimensional (3D) flash memory utilising Through Silicon Via (TSV) technology with 3-bit-per-cell (triple-level cell, TLC) technology. Shipments of prototypes for development purposes started in June, and product samples are scheduled for release in the second half of 2017. The prototype of this ground-breaking device will be showcased at the 2017 Flash Memory Summit in Santa Clara, California, United States, from August 7-10.Devices fabricated with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections, an architecture that realises high speed data input and output while reducing power consumption. Real-world performance has been proven previously, with the introduction of Toshiba’s 2D NAND Flash memory. Combining a 48-layer 3D flash process and TSV technology has allowed Toshiba Memory Corporation to successfully increase product programming bandwidth while achieving low power consumption. The power efficiency of a single package is approximately twice that of the same generation BiCS FLASH memory fabricated with wire-bonding technology. TSV BiCS FLASH also enables a 1-terabyte (TB) device with a 16-die stacked architecture in a single package. Toshiba Memory will commercialise BiCS FLASH with TSV technology to provide an ideal solution in respect for storage applications requiring low latency, high bandwidth and high IOPS/W, including high-end enterprise SSDs. Ref.KY32-CG7937AAKY32-CG7797AAT

Techniques and coding theories in information sciences have helped to design new concepts for faster and better data storage. Rapid and reliable data storage is crucial for the success of businesses, online platforms, information repositories and research centres. The EU-funded INFO-STORE (Novel data storage by advancing information sciences) project investigated how to overcome challenges and limitations in emerging data storage applications.Combining theory, practice and expert discussions in a series of five subprojects, the project examined how to improve information storage through breakthroughs in coding theory and related theoretical disciplines. The project made significant progress with respect to multilevel non-volatile memories and their trade-offs between storage density and read/write speeds. This included designing new coding frameworks to improve read/write speeds, maximising the number of writes, reading memory cells in parallel, and balancing density and speed in multilevel memories. To develop high-throughput memory systems for network switches and routers, INFO-STORE produced a coding framework that switches packets between input and output ports. This also involved new codes for optimal switching guarantees, algorithms that exploit such codes in a network switch or router, and compression of forwarding databases. The achievements in this vein overcame the challenge of memory contention in network switches and routers. High-density memristor (resistive memory) storage and associated reliability challenges were also studied to avoid a key obstacle known as sneak paths. In addition, work on memristor issues involved using regular arrays of memristor devices that combine storage and logic. Another important project milestone involved distributed storage systems and the need for flexible data reconstruction in the presence of failing and busy nodes. To overcome this obstacle, INFO-STORE developed a 2D coding framework that allows only a number of nodes to provide a small portion of their stored information – i.e. partial delivery. Lastly, researchers proposed efficient data distribution schemes that work well with the short packet blocks. As data distribution schemes using fountain codes operate optimally only when the packet blocks are very large, the team produced a coding scheme to optimise encoder operation for the receiver's state. This lowers the overhead considerably for short blocks. The project's results were followed by many other ideas and proposals, including a publication on elastic compression of content in web servers to improve server security against denial-of-service attacks. The project's research findings have already begun contributing to the development of quicker, better and safer data storage. Ref.KY32-CY7C1357S-100AXCKY32-CY7C131E-55NXI

Imec, the world-leading research and innovation hub in nanoelectronics and digital technology, announced today at the 2017 Symposia on VLSI Technology and Circuits the world's first demonstration of a vertically stacked ferroelectric Al doped HfO2 device for NAND applications. Using a new material and a novel architecture, imec has created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention. The achievement shows that ferro-electric memory is a highly promising technology at various points in the memory hierarchy, and as a new technology for storage class memory. Imec will further develop the concept in collaboration with the world's leading producers of memory ICs.  Ferro-electric materials consist of crystals that exhibit spontaneous polarization; they can be in one of two states, which can be reversed with a suitable electric field. This non-volatile characteristic resembles ferromagnetism, after which they have been named. Discovered more than five decades ago, ferro-electric memory has always been considered ideal, due to its very low power needs, non-volatile character and high switching speed. However, issues with the complex materials, the breakdown of the interfacial layer and bad retention characteristics have presented significant challenges. The recent discovery of a ferro-electric phase in HfO2, a well-known and less complex material, has triggered a renewed interest in this memory concept."With HfO2, there is now a material with which we can process ferro-electric memories that are fully CMOS compatible. This allows us to make a ferro-electric FET (FeFET) in both planar and vertical varieties," noted Jan Van Houdt, imec's chief scientist for memory technology. "We are working to overcome some of the remaining issues, such as retention, precise doping techniques and interface properties, in order to stabilize the ferro-electric phase. We are now confident that our FeFET concept has all the required characteristics. It is, in fact, suitable for both stand-alone and embedded memories at various points in the memory hierarchy, going all the way from non-volatile DRAM to Flash-like memories. It has particularly interesting characteristics for future storage-class memory, which will help overcome the current bottleneck caused by the differences in speed between fast processors and slower mass memory."Imec recently presented the first, extremely positive results to its partners. The research center is now offering further development and industrialization of the vertical FeFET as a program to all its memory partners, which include the world's major companies producing memory ICs."FeFETs can be used as a technology to build memory very similar to Flash-memory, but with additional advantages for further scaling, simplified processing, and power consumption," added Van Houdt. "With our longstanding R&D and processing experience on advanced Flash, we are uniquely positioned to offer our partners a head start in this exciting opportunity. They can then decide how best to fit ferro-electric memories in their products and chips." Ref:KY32-K9T1G08U0M-YIBOKY32-CY7C1357S-100AXCKY32-AT49BV162AT(T)  

Apacer Technology has launched the DDR4 VLP Mini RDIMM memory module for networking, telecommunications and embedded systems, as it responds to key trends such as cloud computing, IoT and big data in the networking industry worldwide in recent years. Compliant with new generation ATCA (Advanced Telecommunications Computing Architecture) specifications for telecommunications and communication equipment, the DDR4 VLP Mini RDIMM memory module measures 0.738" high. It is suitable for space-constrained 1U rack systems, blade servers and embedded systems, effectively improving heat dissipation, and improving system stability and reliability.Networking and telecommunication specifications in the past were complicated and not standardised, causing many unnecessary problems in system design. ATCA is a new series of open architecture specifications developed for networking, telecommunications and industrial automation computer products. This series of specifications allows networking, communication and storage devices to be integrated on a single platform, greatly lessening the burden of monitoring and management. Adopting the common industry platform, Apacer’s new DDR4 VLP Mini RDIMM memory module fits into networking and communication equipment, such as router, gateway and switch, and embedded industrial automation equipment, reducing R&D costs and shortening time to market. Its expandability also provides convenience in the integration of the networking environment.JEDEC-compliant Apacer DDR4 VLP Mini RDIMM memory module measures only 80mm long, which is 60% the length of the standard 133mm RDIMM. Available in 4 and 8GB capacities, its 1.2V ultra-low operating voltage is up to 30% more power saving. The DDR4 also supports deep power-down mode, reducing close to 50% standby power consumption. Its power efficiency is particularly significant in satisfying the requirement for low power consumption in industrial embedded, networking and server systems. It is equipped with ECC function to ensure memory access reliability and data integrity, and has built-in thermal sensor that monitors temperature changes during memory module operation and optimises power use. Apacer DDR4 VLP Mini RDIMM memory module demonstrates high-speed transmission and low power consumption within space-constraint systems. Furthermore, its ATCA-compliance allows for system integration, providing the highest quality and stability. Ref:KY32-AT49BV162AT(T)KY32-K9T1G08U0M-YIBOKY32-CY7C131E-55NXI

New industrial-grade microSDHC/XC memory cards have been launched by Apacer Technology which are custom-built for video monitoring equipment to endure long hours of continuous data writing. Not only are Apacer microSDXC UHS-1(U3) memory cards available in capacities ranging from 4-128GB, their Ultra High Speed Class 3 specification also supports smooth Full-HD, 3D and 4K video recording, which is particularly significant in video monitoring applications that require continuous recording and sustain high wear rate.  Their durability, endurance and performance make them suitable for surveillance video recorders, dashcams for fleet vehicles and government use, and webcams.High-endurance memory cards, high-reliability assuranceUnlike those used for photographs and storing small files, Apacer memory cards are designed to endure extensive write cycles. Industrial-grade high-endurance microSDHC/XC memory cards are developed for security surveillance equipment that requires all-year-round uninterrupted data writing, ensuring high-quality images and data integrity required for long-lasting video recording. When using the 128GB ultra high capacity microSDXC memory card to record Full-HD in 20FPS, it can record for up to 20,000 hours; in loop recording, it can store 32 hours of video footage with automatic write-over. In an emergency when both quality and performance are required in the video surveillance system, Apacer microSD memory cards protect and store data securely, providing high endurance and high capacity.Improved speed, enhanced access performanceFeaturing Ultra High Speed Class 3 (U3) specification, Apacer microSD memory cards have maximum read/write speed of 75/65MB per second. The memory cards also support ECC (Error Correcting Code) to automatically check data and provide timely error correction, preventing data loss and damage, and increasing data accuracy and integrity. When teamed with 128GB (SDXC) large capacity, they become a suitable storage device for security surveillance systems.All Apacer microSDHC/SDXC memory cards are temperature-resistant, shockproof, waterproof, anti-static and x-ray-proof, allowing surveillance systems to operate reliably in a harsh environment. The memory cards also feature high quality MLC flash memory chip and customised firmware optimised management tools, such as write protect which prevents precious data from being written over or erased by mistake. Furthermore, the memory cards support ECC to reduce data error arising from constant overwrite, and wear-leveling and S.M.A.R.T. techniques which automatically monitor memory health status, improving product reliability and lifespan. Ref:KY32-K9T1G08U0M-YIBOKY32-CY7C1357S-100AXCKY32-70V639S10BC8

Microchip’s PIC18F ‘K42’ microcontrollers are available with up to 128kbyte (from 16kbyte) of flash memory in packages from 28-48 pins. Max clock speed is 64Mbit/s and there is up to 1kbyte data EEPROM and 8kbyte of SRAM.   The firm has gone big on its ‘core independent peripherals’ (CIP) to allow functions to be implemented in hardware, saving code, validation time, core overhead, and power consumption, said Microchip. Intended for automotive, industrial control, IoT, medical and white goods, they include peripherals for safety critical applications including cyclic redundancy check with memory scan, a windowed watchdog timer, a 24bit signal measurement timer and a hardware limit timer, as well as up to eight hardware PWMs, complementary waveform generation for power bridges, and multiple communications interfaces. Analogue peripherals including a zero crossing detector, constant current I/O (see below), a comparator, and a 12bit ADC with computation – the latter for automating capacitive voltage division (for touch sensing), averaging, filtering, over-sampling, and threshold comparison. Constant current I/O The constant current I/O feature allows the sink and source current of a pin to be set to 1, 2, 5 or 10mA. This has to be used with caution because the pin circuitry cannot dissipate much static power, so an “external resistor must be inserted in series with the load to dissipate most of the power,” said Microchip. It has an example, with a 5V rail and a load which needs 1mA and whose voltage drop can be between 1.0 and 1.5V. The external resistor and pin circuitry has to make up 3.5-4V difference, so the resistor  needs to be chosen to drop 3.5V at of 1 mA, said Microchip, then the pin can make up the 0-500mV variable difference. A ‘memory access partition’ supports data protection and bootloading, and the ‘device information area’ is a dedicated memory space for factory programmed device ID and peripheral calibration values. Building blocks ADC with computation zero crossing detector 10bit PMW complementary waveform generator numerically controlled oscillator data signal modulator hardware limit timer 24bit signal measurement timer configurable logic cell crc/scan module windowed watchdog timer peripheral pin select direct memory access temperature indicator data signal modulator 5bit DAC UART, SPI, and I2C Ref: KY32-PIC18F1220-E/ML KY0-PIC18F1220-E/SO KY0-PIC18F1220-I/ML