NXP USA Inc. SPC5673FF3MVR2

Description

This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications.
It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M devices.
The microcontroller’s e200z4 host processor core is built on the Power Architecture® technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration System.

Power Architecture core

– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
• Memory organization
– 2 MB on-chip flash memory with ECC and read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32 KB) and ECC
– 8 KB instruction cache (with line locking), configurable as 2- or 4-way
– 14 + 3 KB eTPU code and data RAM
– 4  4 crossbar switch (XBAR)
– 24-entry MMU
• Fail Safe Protection
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
• Interrupt
– Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)
– 64-channel eDMA
• Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC
• 1 eMIOS
– 24 unified channels
• 1 eTPU2 (second generation eTPU)
—32 standard channels
– 1 reaction module (6 channels with 3 outputs per channel)
• 2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers
– 6 command queues
– Trigger and DMA support
– 688 ns minimum conversion time
• On-chip CAN/SCI Bootstrap loader with Boot Assist Module (BAM)
• Nexus: Class 3+ for core; Class 1 for eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS)
– EVTO pin for communication with external tool
• Clock generation
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked loop)
• Up to 112 general purpose I/O lines
– Individually programmable as input, output or special function
– Programmable threshold (hysteresis)
• Power reduction modes: slow, stop, and standby
• Flexible supply scheme
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V