Texas Instruments TLK100PHP

[TI]

DESCRIPTION

The TLK3138 is an eight channel serial transceiver. It is compliant with the 10Gbps Ethernet XAUI specification. The TLK3138 provides 10 Gbps high-speed bi-directional point-to-point data transmission. The primary application of this device is in backplanes and front panel connections requiring dual/redundant 10Gbps connections over controlled impedance media of approximately 50Ω. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.
The TLK3138 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3138 provides two complete XGXS/PCS functions defined in Clause 47/48 of the IEEE P802.3ae 10Gbps Ethernet standard. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

FEATURES

• Eight Channel 3.125 Gbps Transceiver
• Contains Two Complete IEEE P802.3ae-2002 10 Gbps Ethernet XGXS(1) (XAUI) Compliant Cores
• XAUI (Serial side) Channel Redundancy Mode Support: Fast Switching from Primary to Secondary XAUI/Channel with Provisionable Error Character or Local Fault Code Insertion at Switch Time
• XGMII (Parallel side) Channel Redundancy Mode Support: Fast Switching from Primary to Secondary XGMII/Channel with Provisionable Error Character or Local Fault Code Insertion at Switch Time
• Serial Side Transmit Pre-emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
• Selectable Full Duplex Serial Side Retimer Mode
• Full Datapath Loopback Capability (Serial/Parallel Side)
• Support PRBS 27-1 and 223-1 Generate/Verify. Support Standard Defined CJPAT, CRPAT, High Frequency, Low Frequency, and Mixed Frequency Testing
• XGMII: HSTL Class 1 I/O with On-chip 50-Ω Termination on Inputs/Outputs (1.5-V Power Supply)
• XGMII: Support Receive (Output) Aligned/Centered Timing Modes, and Transmit (Input) Source Centered Mode
• Supports Jumbo Packet (9600 byte maximum) Operation
• Align Character Skew Support of 30 bit Times at Chip Pins
• Dual MDIO: IEEE 802.3ae Clause 45 Compliant Management Data Input / Output Interface (1.2-V and 2.5-V I/O)
• 1.2-V Core, 1.5-V HSTL I/O Supply, and 2.5-V LVCMOS and Bias Supply
• JTAG: IEEE 1149.1 Test Interface
• ±200 ppm Clock Tolerance in XAUI Transmit and Receive Datapaths
• Diagnostic LED Output Interface
• 130-nm CMOS Technology
• Package: PBGA 484, 23×23mm, 484 ball, 1mm Pitch
• 2.42 W Typical Power Dissipation (Dual XAUI Mode, Input HSTL Termination Disabled)
• Commercial Ambient Operating Temp (0°C to 70°C)
(1) XGMII Extender Sublayer

APPLICATIONS

• 10 Gigabit Ethernet Servers and Routers