Microchip Technology PIC18F96J65-I/PF

DEVICE OVERVIEW

This document contains device-specific information for the following devices:
• PIC18F66J60 • PIC18F87J60
• PIC18F66J65 • PIC18F96J60
• PIC18F67J60 • PIC18F96J65
• PIC18F86J60 • PIC18F97J60
• PIC18F86J65

Ethernet Features:

• IEEE 802.3™ Compatible Ethernet Controller
• Fully Compatible with 10/100/1000Base-T Networks
• Integrated MAC and 10Base-T PHY
• 8-Kbyte Transmit/Receive Packet Buffer SRAM
• Supports One 10Base-T Port
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous Packets
• Activity Outputs for 2 LED Indicators
• Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for various protocols
• MAC:
- Support for Unicast, Multicast and Broadcast packets
- Programmable Pattern Match of up to 64 bytes within packet at user-defined offset
- Programmable wake-up on multiple packet formats
• PHY:
- Wave shaping output filter

Flexible Oscillator Structure:

• Selectable System Clock derived from Single 25 MHz External Source:
- 2.778 to 41.667 MHz
• Internal 31 kHz Oscillator
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if oscillator stops
• Two-Speed Oscillator Start-up
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