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KSZ9031RNXCA: CAD Models, Datasheet, Features

  • Contents

Catalog

KSZ9031RNXCA Product Overview

KSZ9031RNXCA CAD Models

KSZ9031RNXCA Pin Configuration

KSZ9031RNXCA Block Diagram

KSZ9031RNXCA System Block Diagram

KSZ9031RNXCA Features

KSZ9031RNXCA Applications

KSZ9031RNXCA Datasheet

KSZ9031RNXCA Specifications

KSZ9031RNXCA Package

KSZ9031RNXCA Manufacturer

Using Warning

 

KSZ9031RNXCA Product Overview

A fully integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver for CAT-5 unshielded twisted pair (UTP) cable, the KSZ9031RNXCA transmits and receives data at these speeds.

 

The Reduced Gigabit Media Independent Interface (RGMII) on the KSZ9031RNXCA enables data transfer at 10/100/1000 Mbps directly connected to RGMII MACs in Gigabit Ethernet processors and switches.

 

By utilizing on-chip termination resistors for the four differential pairs and integrating an LDO controller to drive a cheap MOSFET to supply the 1.2V core, the KSZ9031RNX lowers board costs and streamlines board layout.

 

In order to make system setup and debugging easier during product rollout and production testing, the KSZ9031RNXCA provides diagnostic functions. Fault detection between the KSZ9031RNXCA I/Os and the board is made possible via parametric NAND tree support. Copper cable faults are found using the LinkMD® TDR-based cable diagnosis. Digital and analog data streams are checked by remote and local loopback functions.

 

AEC-Q100 automotive approved parts and a 48-pin, lead-free QFN packaging are both options for the standard KSZ9031RNXCA.

 

KSZ9031RNXCA CAD Models

 

 

Figure: PCB Symbol

 

 

 

Figure: Footprint

 

 

Figure: 3D Models

 

KSZ9031RNXCA Pin Configuration

 

 

Figure: Pin Configuration

Pin Number Pin Name Description
1 AVDDH 3.3V/2.5V (commercial temp only) analog VDD
2 TXRXP_A Media Dependent Interface[0], positive signal of differential pair
1000BASE-T mode:
TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for MDI X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXP_A is the positive transmit signal (TX+) for MDI configuration and the
positive receive signal (RX+) for MDI-X configuration, respectively.
3 TXRXM_A Media Dependent Interface[0], negative signal of differential pair
1000BASE-T mode:
TXRXM_A corresponds to BI_DA– for MDI configuration and BI_DB– for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXM_A is the negative transmit signal (TX–) for MDI configuration and the
negative receive signal (RX–) for MDI-X configuration, respectively.
4 AVDDL 1.2V analog VDD
5 TXRXP_B Media Dependent Interface[1], positive signal of differential pair
1000BASE-T mode:
TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for MDI X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXP_B is the positive receive signal (RX+) for MDI configuration and the
positive transmit signal (TX+) for MDI-X configuration, respectively.
6 TXRXM_B Media Dependent Interface[1], negative signal of differential pair
1000BASE-T mode:
TXRXM_B corresponds to BI_DB– for MDI configuration and BI_DA– for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXM_B is the negative receive signal (RX–) for MDI configuration and the
negative transmit signal (TX–) for MDI-X configuration, respectively.
7 TXRXP_C 1000BASE-T mode:
TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXP_C is not used.
8 TXRXM_C Media Dependent Interface[2], negative signal of differential pair
1000BASE-T mode:
TXRXM_C corresponds to BI_DC– for MDI configuration and BI_DD– for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXM_C is not used.
9 AVDDL 1.2V analog VDD
10 TXRXP_D Media Dependent Interface[3], positive signal of differential pair
1000BASE-T mode:
TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXP_D is not used.
11 TXRXM_D Media Dependent Interface[3], negative signal of differential pair
1000BASE-T mode:
TXRXM_D corresponds to BI_DD– for MDI configuration and BI_DC– for
MDI-X configuration, respectively.
10BASE-T/100BASE-TX mode:
TXRXM_D is not used.
12 AVDDH 3.3V/2.5V (commercial temp only) analog VDD
13 NC No connect. This pin is not bonded and can be connected to digital ground for
footprint compatibility with the KSZ9021RN Gigabit PHY.
14 DVDDL 1.2V digital VDD
15 LED2/PHYAD1 LED output: Programmable LED2 output
Config mode: The pull-up/pull-down value is latched as PHYAD[1] during
power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
The LED2 pin is programmed by the LED_MODE strapping option (Pin 41).
16 DVDDH 3.3V, 2.5V, or 1.8V digital VDD_I/O
17 LED1/PHYAD0/PME_N1 LED1 output: Programmable LED1 output
Config mode: The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of PHYAD[0]. See the Strap-In
Options - KSZ9031RNX section for details.
PME_N output: Programmable PME_N output (pin option 1). This pin function
requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range
from 1.0 kΩ to 4.7 kΩ. When asserted low, this pin signals that a WOL event
has occurred.
This pin is not an open-drain for all operating modes.
The LED1 pin is programmed by the LED_MODE strapping option (Pin 41).
18 DVDDL 1.2V digital VDD
19 TXD0 RGMII mode: RGMII TD0 (Transmit Data 0) input
20 TXD1 RGMII mode: RGMII TD1 (Transmit Data 1) input
21 TXD2 RGMII mode: RGMII TD2 (Transmit Data 2) input
22 TXD3 RGMII mode: RGMII TD3 (Transmit Data 3) input
23 DVDDL 1.2V digital VDD
24 GTX_CLK RGMII mode: RGMII TXC (Transmit Reference Clock) input
25 TX_EN RGMII mode: RGMII TX_CTL (Transmit Control) input
26 DVDDL 1.2V digital VDD
27 RXD3/MODE3 RGMII mode: RGMII RD3 (Receive Data 3) output
Config mode: The pull-up/pull-down value is latched as MODE3 during
power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
28 RXD2/MODE2 RGMII mode: RGMII RD2 (Receive Data 2) output
Config mode: The pull-up/pull-down value is latched as MODE2 during
power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
29 VSS Digital ground
30 DVDDL 1.2V digital VDD
31 RXD1/MODE1 RGMII mode: RGMII RD1 (Receive Data 1) output
Config mode: The pull-up/pull-down value is latched as MODE1 during
power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.
32 RXD0/MODE0 RGMII mode: RGMII RD0 (Receive Data 0) output
Config mode: The pull-up/pull-down value is latched as MODE0 during  power-up/reset.
33 RX_DV/CLK125_EN RGMII mode: RGMII RX_CTL (Receive Control) output
Config mode: Latched as CLK125_NDO Output Enable during power-up/reset.
34 DVDDH 3.3V, 2.5V, or 1.8V digital VDD_I/O
35 RX_CLK/PHYAD2 RGMII mode: RGMII RXC (Receive Reference Clock) output
Config mode: The pull-up/pull-down value is latched as PHYAD[2] during power-up/reset.
36 MDC Management data clock input
This pin is the input reference clock for MDIO (Pin 37).
37 MDIO Management data input/output
This pin is synchronous to MDC (Pin 36) and requires an external pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0 kΩ to 4.7 kΩ.
38 INT_N/PME_N2 Interrupt output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions and
reading the interrupt status. Register 1Fh, Bit [14] sets the interrupt output to
active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
For Interrupt (when active low) and PME functions, this pin requires an exter nal pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0 kΩ to
4.7 kΩ.
This pin is not an open-drain for all operating modes.
39 DVDDL 1.2V digital VDD
40 DVDDH 3.3V, 2.5V, or 1.8V digital VDD_I/O
41 CLK125_NDO/LED_MODE 125 MHz clock output
This pin provides a 125 MHz reference clock output option for use by the
MAC.
Config mode: The pull-up/pull-down value is latched as LED_MODE during
power-up/reset.
42 RESET_N Chip reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising edge)
of RESET_N.
43 LDO_O On-chip 1.2V LDO controller output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for
the chip’s core voltages. If the system provides 1.2V and this pin is not used,
it can be left floating.
44 AVDDL_PLL 1.2V analog VDD for PLL
45 XO 25 MHz crystal feedback
This pin is a no connect if an oscillator or external clock source is used.
46 XI Crystal/Oscillator/External Clock input 25 MHz ±50 ppm tolerance
47 NC No connect
This pin is not bonded and can be connected to AVDDH power for footprint
compatibility with the KSZ9021RN Gigabit PHY.
48 ISET Set the transmit output level
Connect a 12.1 kΩ 1% resistor to ground on this pin.
Paddle P_GND Exposed paddle on bottom of chip
Connect P_GND to ground.

KSZ9031RNXCA Block Diagram

 

 

Figure: Block Diagram

 

KSZ9031RNXCA System Block Diagram

 

 

Figure: System Block Diagram

 

KSZ9031RNXCA Features

  • Operating Voltages

- Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (External FET or Regulator)

- VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V

- Transceiver (AVDDH): 3.3V or 2.5V (Commercial Temp.)

  • AEC-Q100 Grade 3 (KSZ9031RNXUA/UB) andGrade 2 (KSZ9031RNXVA/VB) Qualified for Automotive Applications
  • 48-pin QFN (7 mm × 7 mm) Package
  • Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
  • Programmable LED Outputs for Link, Activity, and Speed
  • Baseline Wander Correction
  • LinkMD TDR-Based Cable Diagnostic to IdentifyFaulty Copper Cabling
  • Parametric NAND Tree Support to Detect FaultsBetween Chip I/Os and Board
  • Loopback Modes for Diagnostics
  • Automatic MDI/MDI-X Crossover to Detect andCorrect Pair Swap at all Speeds of Operation
  • Automatic Detection and Correction of PairSwaps, Pair Skew, and Pair Polarity
  • MDC/MDIO Management Interface for PHY Register Configuration
  • Interrupt Pin Option
  • Power-Down and Power-Saving Modes
  • Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications
  • RGMII Timing Supports On-Chip Delay Accordingto RGMII Version 2.0, with Programming Optionsfor External Delay and Making Adjustments and Corrections to TX and RX Timing Paths
  • RGMII with 3.3V/2.5V/1.8V Tolerant I/Os
  • Auto-Negotiation to Automatically Select theHighest Link-Up Speed (10/100/1000 Mbps) andDuplex (Half/Full)
  • On-Chip Termination Resistors for the Differential Pairs
  • On-Chip LDO Controller to Support Single 3.3VSupply Operation – Requires Only One ExternalFET to Generate 1.2V for the Core
  • Jumbo Frame Support up to 16 KB
  • 125 MHz Reference Clock Output
  • Energy Detect Power-Down Mode for ReducedPower Consumption When the Cable is Not Attached

 

KSZ9031RNXCA Applications

  • IPTV
  • IP Set-Top Box
  • Game Console
  • Triple-Play (Data, Voice, Video) Media Center
  • Industrial Control
  • Automotive In-Vehicle Networking
  • Laser/Network Printer
  • Network Attached Storage (NAS)
  • Network Server
  • Gigabit LAN on Motherboard (GLOM)
  • Broadband Gateway
  • Gigabit SOHO/SMB Router

 

KSZ9031RNXCA Datasheet

You can download the datasheet from the link given below:

 

KSZ9031RNXCA Datasheet

 

KSZ9031RNXCA Specifications

Type Description
Category Integrated Circuits (ICs)
Interface
Drivers, Receivers, Transceivers
Mfr Microchip Technology
Series -
Package Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Product Status Active
Type Transceiver
Protocol Ethernet
Number of Drivers/Receivers 4/4
Duplex Full
Data Rate -
Voltage - Supply 1.8V, 2.5V, 3.3V
Operating Temperature 0°C ~ 70°C
Mounting Type Surface Mount
Package / Case 48-VFQFN Exposed Pad
Supplier Device Package 48-QFN (7x7)
Base Product Number KSZ9031

 

KSZ9031RNXCA Package

 

 

Figure: Package

 

KSZ9031RNXCA Manufacturer

For thousands of different customer applications throughout the world, Microchip Technology Inc., a leading supplier of microcontroller and analog semiconductors, offers low-risk product development, lower total system costs, and quicker time to market. Microchip, with headquarters in Chandler, Arizona, provides excellent technical assistance, consistent delivery, and high-quality products.

 

Using Warning

Note: Please check their parameters and pin configuration before replacing them in your circuit.

KSZ9031RNXCA Documents & Media

Download datasheets and manufacturer documentation for Microchip Technology KSZ9031RNXCA.
PCN Assembly/Origin
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KSZ9031RNXCA PCB Symbol, Footprint & 3D Model

Microchip Technology KSZ9031RNXCA

Microchip Technology

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Karty

Karty is a seasoned writer with over 6 years of experience in the semiconductor electronics industry. She possesses a wealth of knowledge in the field, and her writing is characterized by a strong technical foundation and a keen eye for detail. Karty is also a creative thinker with a unique perspective, and her work often offers fresh insights into complex topics.

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