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CY7C68013A USB Microcontroller: Datasheet, Features and Block Diagram

  • Contents

Catalog

Functional Overview

CAD Models

Block Diagram

Features

Applications

Functions

Alternate Part Numbers

Datasheet

Product Attributes

Manufacturer

Using Warning

Functional Overview

USB Signaling Speed FX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:

■ Full speed, with a signaling bit rate of 12 Mbps

■ High speed, with a signaling bit rate of 480 Mbps FX2LP does not support the low speed signaling mode of 1.5 Mbps.

 

The 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.

 

CAD Models

Figure-CY7C68013A-Part-Symbol

 

Part Symbol

 

Figure-CY7C68013A-Footprint

 

Footprint

 

Block Diagram

Figure-CY7C68013A-Block-Diagram

Block Diagram

 

 

Features

Cypress Semiconductor Corporation’s (Cypress’s, now Infineon) EZ-USB FX2LP™ (CY7C68013A) is a low-power version of the EZ-USB FX2, which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very costeffective solution that provides superior time-to-market advantages with low power to enable bus powered applications.

 

The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 QFN. Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations.

 

With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.

 

The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56, 100 and 128 pin FX2.

 

Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.

  • Single-chip integrated USB 2.0 transceiver, SIE, and enhanced 8051 microprocessor
  • Fit, form and function compatible with the FX2 —Pin-compatible —Object-code-compatible —Functionally-compatible (FX2LP functionality is a superset of the FX2)
  • Draws no more than 85 mA in any mode making the FX2LP suitable for bus powered applications
  • Software: 8051 runs from internal RAM, which is: —Downloaded via USB —Loaded from EEPROM —External memory device (128-pin configuration only)
  • 16 KBytes of on-chip Code/Data RAM • Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints —Buffering options: double, triple, and quad
  • Additional programmable (BULK/INTERRUPT) 64-byte endpoint

 

Applications

  • Portable video recorder
  • MPEG/TV conversion
  • DSL modems
  • ATA interface
  • Memory card readers
  • Legacy conversion devices
  • Cameras
  • Scanners
  • Home PNA
  • Wireless LAN
  • MP3 players
  • Networking The “Reference Designs” section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit http://www.cypress.com for more information.

 

Functions

1.1.USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:

  • Full speed, with a signaling bit rate of 12 Mbps.
  • High speed, with a signaling bit rate of 480 Mbps. FX2LP does not support the low-speed signaling mode of 1.5 Mbps.

 

1.2. The 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.

 

1.3. 8051 Clock Frequency FX2LP has an on-chip oscillator circuit that uses an external 24-MHz (±100 ppm) crystal with the following characteristics:

  • Parallel resonant
  • Fundamental mode
  • 500-µW drive level
  • 12-pF (5% tolerance) load capacitors.

 

An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.

 

The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency—48, 24, or 12 MHz.

 

2. USARTS FX2LP contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multiplexed with port pins.

 

UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation.[1]

 

3. Special Function Registers

Certain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with “0” and “8” contain bitaddressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP. Because of the faster and more efficient SFR addressing, the FX2LP I/O ports are not addressable in external RAM space (using the MOVX instruction).

 

Alternate Part Numbers

This part may be known by these alternate part numbers:

CY7C68015A56LTXC

 

Datasheet

CY7C68013A-Datasheet

 

Product Attributes

Manufacturer Part Number: CY7C68013A-100AC
Part Life Cycle Code: Obsolete
Ihs Manufacturer: CYPRESS SEMICONDUCTOR CORP
Part Package Code: QFP
Package Description: LQFP, QFP100,.63X.87
Pin Count: 100
HTS Code: 8542.31.00.01
Manufacturer: Cypress Semiconductor
Risk Rank: 5.47
Address Bus Width: 16
Bit Size: 8
Bus Compatibility: I2C; I2S; UART
Clock Frequency-Max: 24 MHz
Data Transfer Rate-Max: 60 MBps
External Data Bus Width: 8
JESD-30 Code: S-PQFP-G100
JESD-609 Code: e0
Length: 20 mm
Moisture Sensitivity Level: 3
Number of I/O Lines: 40
Number of Terminals: 100
Operating Temperature-Max: 70 °C
Package Body Material: PLASTIC/EPOXY
Package Code: LQFP
Package Equivalence Code: QFP100,.63X.87
Package Shape: SQUARE
Package Style: FLATPACK, LOW PROFILE
Seated Height-Max: 1.6 mm
Speed: 48 MHz
Supply Voltage-Max: 3.6 V
Supply Voltage-Min: 3 V
Supply Voltage-Nom: 3.3 V
Surface Mount: YES
Technology: CMOS
Temperature Grade: COMMERCIAL
Terminal Finish: Tin/Lead (Sn/Pb)
Terminal Form: GULL WING
Terminal Pitch: 0.65 mm
Terminal Position: QUAD
Width: 14 mm

Manufacturer

Cypress Semiconductor Corporation is an American semiconductor design and manufacturing company, and is now a subsidiary of Infineon Technologies.It offered NOR flash memories, F-RAM and SRAM Traveo microcontrollers, the industry's only PSoC programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense capacitive touch-sensing controllers, Wireless BLE Bluetooth Low-Energy and USB connectivity solutions.

 

Using Warning

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

FAQ

 

What is the CY7C68013A?

CY7C68013A is is a highly integrated, low-power USB 2.0 microcontroller.

 

What does the 8051 microprocessor embedded in the FX2LP family contain?

256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs.

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