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DS90UB928Q in Practice: Solving EMC Failures and I2C Timing in Automotive SerDes

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Quick-Reference Card: DS90UB928Q at a Glance

Attribute Detail
Component Type FPD-Link III to OpenLDI (LVDS) Deserializer
Manufacturer Texas Instruments
Key Spec 5 MHz to 85 MHz Pixel Clock (Supports 720p HD)
Supply Voltage 3.3V (Core), 1.8V or 3.3V (I/O)
Package Options 48-WQFN (7mm x 7mm)
Lifecycle Status Active (AEC-Q100 Qualified)
Best For Automotive Infotainment and ADAS Display Bridging

DS90UB928Q IC package and automotive display application


1. What Is the DS90UB928Q? (Definition + Architecture)

The DS90UB928Q is an automotive-qualified FPD-Link III to FPD-Link (OpenLDI) deserializer from Texas Instruments that converts high-speed serialized data into uncompressed 720p digital video, audio, and bidirectional control signals over a single shielded twisted pair (STP) or coaxial cable.

1.1 Core Architecture & Design Philosophy

The DS90UB928Q is designed to sit at the "display end" of a high-speed serial link. Its primary job is to take the high-speed CML (Current Mode Logic) signal from an upstream serializer (like the DS90UB925Q or DS90UB927Q) and reconstruct the original parallel LVDS video stream.

The standout feature here isn't just the video; it’s the Bidirectional Control Channel (BCC). Unlike older SerDes generations that required a separate wire for I2C or touch-screen data, the 928Q embeds this data into the high-speed link. This reduces harness weight and complexity—a critical factor in modern automotive interior design.

1.2 Where It Fits in the Signal Chain

In a typical automotive signal chain, the DS90UB928Q acts as the bridge between the long-run cable (from the Head Unit) and the LCD panel. It receives the FPD-Link III signal, performs adaptive equalization to compensate for cable loss, and outputs OpenLDI (LVDS) directly to the display timing controller (TCON).


2. Electrical Characteristics: The Numbers That Matter

2.1 Power Supply & Consumption Profile

The device operates on a nominal 3.3V rail, but the I/O can be shifted to 1.8V to maintain compatibility with lower-voltage SoCs. * So What?: If you are using 1.8V logic, ensure your pull-up resistors on the I2C lines are tied to the correct VDDIO rail, not the main 3.3V supply, to prevent latch-up or ESD diode conduction.

2.2 Performance Specs

  • Pixel Clock (5–85 MHz): This range is wide enough to handle everything from low-res backup cameras to 720p60 infotainment screens.
  • Adaptive Equalizer: The chip automatically compensates for cable aging and temperature shifts.
  • So What?: This reduces the need for manual tuning during production, but it requires a clean PCB layout near the differential inputs to avoid confusing the internal adaptation logic.

2.3 Absolute Maximum Ratings — What Will Kill It

Parameter Max Rating
VCC (3.3V) to GND -0.3V to 4.0V
I/O Voltage (VDDIO) -0.3V to 4.0V
Junction Temperature +150°C
ESD HBM ±8kV

3. Pinout & Package Guide

3.1 Pin-by-Pin Functional Groups

Pin Group Pins Function
FPD-Link III In RIN+, RIN- High-speed differential input
OpenLDI Out DOUT[0:3]+/-, CLK+/- LVDS Video/Clock output to panel
Control SDA, SCL I2C Interface for local/remote config
Audio I2S_DA, I2S_WC, I2S_CLK Digital audio output for speakers
Config MODE, IDx Hardware straps for address and link mode

3.2 Package Variants & Soldering Notes

The 48-pin WQFN package features an exposed thermal pad (DAP). * Engineering Note: The thermal pad MUST be soldered to a large ground plane with multiple micro-vias. Without this, the chip will undergo thermal throttling or exhibit clock jitter under high-ambient automotive temperatures.


4. Known Issues, Errata & Real-World Pain Points

4.1 EMC/EMI Test Failures (Harmonics)

Problem: Many designs fail radiated emissions tests at the 4th and 6th harmonics of the pixel clock. Root Cause: Insufficient filtering on the internal Common Mode Filter (CMF) circuit. Recommended Fix: The datasheet may suggest a 0.1μF capacitor on the CMF pin. In practice, increasing this to 4.7μF significantly dampens these harmonics and helps pass CISPR-25 Class 5 requirements.

4.2 I2C Speed Configuration Discrepancies

Problem: Setting the I2C master for 100kbps often results in an actual throughput of ~80kbps. Root Cause: The internal oscillator frequency varies slightly, and the default register values for SCL high/low times are conservative. Recommended Fix: Do not rely on default auto-configuration. Manually calculate and write to registers 0x26 (SCL High Time) and 0x27 (SCL Low Time) based on your specific PCLK.

4.3 PCLK LOCK Instability

Problem: The "LOCK" pin toggles or fails to stay high when using specific long-length cables. Root Cause: Adaptive equalizer reaching its limit or signal integrity degradation at the 85MHz limit. Recommended Fix: Ensure the differential impedance is strictly 100Ω (STP) or 50Ω (Coax). Use the internal BIST (Built-In Self Test) mode to verify the link quality before troubleshooting the software stack.


5. Application Circuits & Integration Examples

5.1 Typical Application: Automotive Central Information Display

In this setup, the 928Q receives a 1-pair FPD-Link III signal from the dashboard's SoC. The 928Q then drives a 4-lane OpenLDI display. * Layout Tip: Keep the RIN+/RIN- traces as short as possible from the connector to the IC pins. Avoid stubs on these lines at all costs.

5.2 Interface Example: I2C Register Initialization

To initialize the link and enable the video output, use the following sequence via your local microcontroller or the remote Serializer:

// Pseudocode for DS90UB928Q Initialization
write_reg(0x01, 0x01);  // Digital Reset
delay(10ms);
write_reg(0x26, 0x30);  // Adjust I2C SCL High Time for 100kbps
write_reg(0x27, 0x30);  // Adjust I2C SCL Low Time
write_reg(0x34, 0x01);  // Enable Adaptive Equalizer
// Check for LOCK status on Pin 24 or Register 0x1C

6. Alternatives, Replacements & Cross-Reference

6.1 Pin-Compatible Drop-In Replacements

There are no direct pin-for-pin "drop-in" replacements from other manufacturers due to the proprietary nature of FPD-Link III. However, within the TI family:

Part Number Manufacturer Key Difference Compatible?
DS90UB948-Q1 TI Supports 2K resolution (Dual Link) ?? (Requires layout change)
DS90UB926-Q1 TI Older version, lower max clock ? (Different Pinout)

6.2 Upgrade Path

If your next-gen design requires 1080p or higher, move to the DS90UB948-Q1. It supports dual-lane FPD-Link III and offers higher bandwidth for larger displays.

6.3 Cost-Down Alternatives

For non-automotive applications, you may consider the Maxim (Analog Devices) GMSL2 series, though this requires changing both the Serializer and Deserializer, as the protocols are not interoperable.


7. Procurement & Supply Chain Intelligence

  • Lifecycle Status: Active. This part is widely used in automotive platforms with long lifecycles (10+ years).
  • Typical MOQ: 1,000 units (Tape & Reel).
  • BOM Risk Factors: As an automotive-qualified part, it is subject to strict allocation during semiconductor shortages. It is a single-source technology; if TI has a supply disruption, there is no direct equivalent that works with FPD-Link III serializers.
  • Authorized Distributors: Arrow, Avnet, Mouser, Digi-Key, and TI Direct.

8. Frequently Asked Questions

Q: What is the DS90UB928Q used for? A: It is primarily used to receive high-speed video data in automotive displays, such as infotainment screens, digital instrument clusters, and rear-seat entertainment systems.

Q: What are the best alternatives to the DS90UB928Q? A: Within the TI ecosystem, the DS90UB948 is the logical upgrade for higher resolution. Competitors include Maxim GMSL2 and Inova APIX3, though these require a complete system architecture shift.

Q: Does it support HDCP? A: The DS90UB928Q-Q1 supports HDCP content protection when paired with an HDCP-capable serializer. Verify the specific suffix of your part number for HDCP key inclusion.

Q: Can it work over Coax cables? A: Yes, it supports both Shielded Twisted Pair (STP) and Coaxial (Coax) cabling. The mode is typically selected via the MODE_SEL pin strapping.


9. Resources & Tools

  • Official Datasheet: Texas Instruments DS90UB928Q-Q1 Product Page
  • Evaluation Board: DS90UB928QEVM
  • Software: TI Analog LaunchPAD (ALP) for register configuration and link monitoring.
  • Reference Design: TIDA-00161 (Automotive Infotainment Display Reference Design).

DS90UB928QSQE/NOPB Documents & Media

Download datasheets and manufacturer documentation for Texas Instruments DS90UB928QSQE/NOPB.

DS90UB928QSQE/NOPB PCB Symbol, Footprint & 3D Model

Texas Instruments DS90UB928QSQE/NOPB

Texas Instruments

Serializers & Deserializers - Serdes FPD-Link III Deserializer

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