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Introduction

74LS138 is a 3-line to 8-line decoder / demultiplexer. The chip is designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high performance memory systems these decoders can be used to minimize the effects of system decoding. The three enable pins of chip (in which Two active-low and one active-high) reduce the need for external gates or inverters when expanding.

Catalog

Introduction

I Full Adder Circuit

II Responder Circuit

III Logic Function

IV Full Subtractor Circuit

V Three-input Majority Voting

FAQ

Ordering & Quantity

I Full Adder Circuit

The full adder has 3 input terminals: An, Bn, Cn-1; 2 output terminals: Sn, Cn. The 74LS138 3-line to 8-line decoder has 3 data input terminals: A, B, C; 3 enable terminals and 8 output terminals. Here, the 3 data input terminals of the 3-line to 8-line decoder can be regarded as the 3 input terminals of the full adder. That is, the inputs A, B, and C of the 3-line to 8-line decoder correspond to the inputs An, Bn, and Cn-1 of the full adder respectively. Set the 3 enable terminals of the 3-line to 8-line decoder to the effective level to maintain normal operation. The key point here is to deal with the relationship between the 8 output terminals of the 3-line to 8-line decoder and the 2 outputs of the full adder.

Use the output OUT (1, 2, 4, 7) of the 3-line to 8-line decoder as a 4-input or gate input, and the gate output as the sum of the adder. Use the output OUT ( 3, 5, 6, 7) of the 3-line to 8-line decoder as a 4-input or gate input, the gate output is used as the carry output of the adder. When the input of the adder is: a=1, b=0, ci=1, the input of the corresponding 3-line to 8-line decoder is A=1, B=0, C=1. The output of the decoder is out (5) = 1 and the rest is 0. According to the connection relationship designed above, S = 0, CO = 1, which satisfies the function of full adder.

Figure 1. Full Adder Circuit

II Responder Circuit

Figure 2. Responder Circuit

III Logic Function

F = ABC + A‘BC + AB’C

= 111 + 110 + 101

= Y7 + Y6 + Y5

According to the rule of 74LS138, A is the low bit (LSB) and D is the high bit (MSB). The 74LS138 decoding output is low level effective. With 74LS10 NAND gate, the actual logic is input low level effective or gate.

Figure 3. Circuit of Logic Function

IV Full Subtractor Circuit

Figure 4. Full Subtractor Circuit

V Three-input Majority Voting

The device consists of a 3-line to 8-line decoder (74LS138) and two 4-input NAND gates (74LS20). There are three buttons for user. Press the button to agree, not to press means to reject. When no one presses the button, or when only one person presses the button, for example, S1 is pressed, but S2 and S0 are not pressed. The red light is on, the green light is off, and the buzzer is silent, indicating veto. When two or more people press the button, for example, if S1 and S2 are pressed, the red light will be off, the green light will be on, and the buzzer will sound to indicate a pass. Use 74LS138 decoder and four-input NAND gate 74LS20 to realize this logic function.

Figure 5. Circuit of Three-input Majority Voting


FAQ

  • What type of applications is 74LS138 designed to be used?

High-performance memory-decoding or data-routing applications

  • How many pins does 74LS138 reduce the need for external gates or inverters when expanding?

Three enable pins

  • What is the difference between 74hc138 and 74LS138?

Both have the same function. 74HC138 is made of high-speed CMOS process, with low power consumption, high output, low level and wide range.

74LS138 adopts the early bipolar process, and its driving capability is relatively larger.

  • What is the functional difference between 74ls138 decoder and 74ls148?

74ls138 is a 3-8 wire decoder/multiplexer, 74ls148 is an 8-3 wire octal priority encoder.

One is decoding and the other is encoding. Opposite effect

  • What's the difference between 74LS138D and 74LS138N

Those two are the same chip, D is SOP package, N is DIP package.

  • What are the output characteristics of 74LS138 decoder

Under the premise that the enable terminals S1 (active high), S2 (active low), and S3 (active low) are valid at the same time, only one output terminal is low at a time (the rest are high);

If the enable terminal is invalid, the output is all high level.

  • What do the letters and numbers in 74ls138 stand for?

74ls138 is a 3-8-line decoder. The number 74 represents the 74 series of the 54/74 series, and the 74 series has an operating temperature of 0 degrees to 70 degrees. LS is a series, representing the low-power Schottky series. 138 is the variety code.

  • Whats the working principle of 74ls138?

74LS138 working principle

① When one strobe terminal (E1) is high level, and the other two strobe terminals (E2) and (E3) are low level, at the output terminals corresponding to Y0 to Y7, the binary code of address terminals (A0, A1, A2)  can be decoded at low level. For example: when A2A1A0=110, the Y6 output terminal outputs a low-level signal.

②Using E1, E2 and E3, it can be cascaded to expand into a 24-line decoder; if an external inverter is connected, it can also be cascaded to expand into a 32-line decoder.

③If one of the strobe terminals is used as a data input terminal, 74LS138 can also be used as a data distributor.

④It can be used in 8086 decoding circuit to expand memory.

 

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