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Product Overview

The 74HC86 is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

 

This blog will introduce 74HC86 systematically from its features, pinout to its specifications, applications, also including 74HC86 datasheet and so much more.

 

Catalog

Product Overview

74HC86 Features

74HC86 Pinout

Ordering Information

Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics

74HC86 Circuit Diagram

74HC86 Package

74HC86 Manufacturer

74HC86 Datasheet

Using Warnings

74HC86 FAQ

 

74HC86 Features

  • Output Drive Capability: 10 LSTTL  Loads
  • Outputs Directly Interface to CMOSNMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 A
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with JEDEC Standard No. 7A Requirements
  • ESD Performance: HBM  2000 V; Machine Model  200 V
  • Chip Complexity: 56 FETs or 14 Equivalent Gates
  • These are Pb−Free Devices

 

74HC86 Pinout

The following figure is the diagram of 74HC86 pinout.

 

74HC86 Pinout

74HC86 Pinout

 

Logic Diagram

Logic Diagram

 

Function Table

Function Table

 

Ordering Information

Device

Package

Shipping

74HC86DR2G

SOIC−14

(Pb−Free)

 

2500 / Tape & Reel

74HC86DTR2G

TSSOP−14*

 

Maximum Ratings

Symbol

Parameter

Value

Unit

VCC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

Vin

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

Vout

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

Iin

DC Input Current, per Pin

±20

mA

Iout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, SOIC Package†

TSSOP Package†

500

450

mW

Tstg

Storage Temperature

– 65 to + 150

°C

TL

Lead Temperature, 1 mm from Case for 10 Seconds

(SOIC or TSSOP Package)

 

260

°C

 

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings  only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

†Derating — SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: − 6.1 mW/°C from 65° to 125°C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

 

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must  always  be tied to an appropriate logic voltage level   (e.g.,  either  GND  or  VCC).

Unused outputs must be left open.

 

Symbol

Parameter

Min

Max

Unit

VCC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

0

VCC

V

TA

Operating Temperature, All Package Types

– 55

+ 125

°C

tr, tf

Input Rise and Fall Time (Figure 1)

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

0

0

1000

500

ns

0

400

 

 

DC Electrical Characteristics 

 

Symbol

 

 

Parameter

 

 

Test Conditions

 

 

VCC (V)

Guaranteed Limit

 

 

Unit

 

 

 

 

– 55 to 25°C

 

85°C

 

125°C

 

VIH

Minimum High−Level Input Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| ≤ 20 µA

2.0

3.0

4.5

1.5

2.1

3.15

1.5

2.1

3.15

1.5

2.1

3.15

V

 

 

 

6.0

4.2

4.2

4.2

 

VIL

Maximum Low−Level Input Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| ≤ 20 µA

2.0

3.0

4.5

0.5

0.9

1.35

0.5

0.9

1.35

0.5

0.9

1.35

V

 

 

 

6.0

1.8

1.8

1.8

 

VOH

Minimum High−Level Output Voltage

Vin = VIH or VIL

|Iout| ≤ 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

 

 

Vin = VIH or VIL |Iout| ≤ 2.4 mA

3.0

2.48

2.34

2.20

 

 

 

|Iout| ≤ 4.0 mA

4.5

3.98

3.84

3.70

 

 

 

|Iout| ≤ 5.2 mA

6.0

5.48

5.34

5.20

 

VOL

Maximum Low−Level Output Voltage

Vin = VIH or VIL

|Iout| ≤ 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

 

 

Vin = VIH or VIL |Iout| ≤ 2.4 mA

3.0

0.26

0.33

0.40

 

 

 

|Iout| ≤ 4.0 mA

4.5

0.26

0.33

0.40

 

 

 

|Iout| ≤ 5.2 mA

6.0

0.26

0.33

0.40

 

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

µA

ICC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

2.0

20

40

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS  Data Book (DL129/D).

 

AC Electrical Characteristics (CL = 50 pF, Input t, = tf = 6 ns)

 

Symbol

 

 

Parameter

 

VCC (V)

Guaranteed Limit

 

 

Unit

 

 

 

– 55 to 25°C

 

85°C

 

125°C

 

tPLH, tPHL

Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2)

2.0

100

125

150

ns

 

 

3.0

4.5

80

20

90

25

110

31

 

 

 

6.0

17

21

26

 

tTLH, tTHL

Maximum Output Transition Time, Any Output (Figures 1 and 2)

2.0

75

95

110

ns

 

 

3.0

4.5

30

15

40

19

55

22

 

 

 

6.0

13

16

19

 

Cin

Maximum Input Capacitance

10

10

10

pF

 

NOTES:

1.For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

2.Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

 

CPD

 

Power Dissipation Capacitance (Per Gate)*

Typical @ 25°C, VCC = 5.0 V

 

pF

33

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f +  ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

 

74HC86 Circuit Diagram

The following is the circuit diagram of Switching Waveforms.

 

Switching Waveforms

Switching Waveforms

 

Test Circuit

Test Circuit

 

Expanded Logic Diagram

Expanded Logic Diagram

 

74HC86 Package

The following diagram shows the 74HC86 package.

 

74HC86 Package

74HC86 Package

 

DIM

MILLIMETERS

INCHES

 

MIN

MAX

MIN

MAX

A

8.55

8.75

0.337

0.344

B

3.80

4.00

0.150

0.157

C

1.35

1.75

0.054

0.068

D

0.35

0.49

0.014

0.019

F

0.40

1.25

0.016

0.049

G

1.27 BSC

0.050 BSC

J

0.19

0.25

0.008

0.009

K

0.10

0.25

0.004

0.009

M

0 °

7 °

0 °

7 °

P

5.80

6.20

0.228

0.244

R

0.25

0.50

0.010

0.019

 

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

 

Soldering Footprint

Soldering Footprint

 

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 

74HC86 Manufacturer

ON Semiconductor is a Fortune 500 company driving energy efficient innovations, empowering customers to reduce global energy use. The company is a leading supplier of semiconductor-based solutions, offering a comprehensive portfolio of energy efficient power and signal management, logic, standard and custom devices. The company’s products help engineers solve their unique design challenges in automotive, communications, computing, consumer, industrial, medical and military/aerospace applications.

 

74HC86 Datasheet

You can download 74HC86 datasheet from the link given below:

74HC86 Datasheet

 

Using Warnings

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

74HC86 FAQ

What is NOR gate IC?

A NOR gate (“not OR gate”) is a logic gate that produces a high output (1) only if all its inputs are false, and low output (0) otherwise. Hence the NOR gate is the inverse of an OR gate, and its circuit is produced by connecting an OR gate to a NOT gate.

 

Why XOR gate is called exclusive?

An XOR gate is normally two inputs logic gate where the output is only logical 1 when only one input is logical 1. When both inputs are equal, either are 1 or both are 0, the output will be logical 0. This gate is called XOR or exclusive OR gate because its output is only 1 when its input is exclusively 1.

 

What is Quad input?

A quad gate is an IC (integrated circuit or chip) containing four logic gates. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltages.

PCB Symbol, Footprint & 3D Model

 

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