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74HC138 Decoder: Datasheet, Pinout, Schematic [FAQ]

  • Contents

Product Overview

The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high.

 

There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E1 and E2 asserted low and E3 asserted high.

 

This blog will introduce 74HC138 systematically from its features, pinout to its specifications, applications, also including 74HC138 datasheet and so much more.

 

Catalog

Product Overview

74HC138 Features

74HC138 Pinout

74HC138 Applications

74HC138 Circuit Schematic

74HC138 Logic Diagram

74HC138 Block Diagram

74HC138 Package

74HC138 Specification

74HC138 Manufacturer

74HC138 Datasheet

Using Warnings

74HC138 FAQ

 

74HC138 Features

  • Wide supply voltage range from 2.0 to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Demultiplexing capability
  • Multiple input enable for easy expansion
  • Ideal for memory chip select decoding
  • Active LOW mutually exclusive outputs
  • Input levels:

 For 74HC138: CMOS level

For 74HCT138: TTL level

  • Complies with JEDEC standards:

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

  • ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

 

 

74HC138 Pinout

The following figure is the diagram of 74HC138 pinout.

 

74HC138 Pinout

74HC138 Pinout

 

74HC138 Applications

  • Memory chip select decoding
  • Demultiplexing
  • Single line peripheral control
  • Allow simple serial bit streams from a microcontroller to control asmany peripheral lines as needed

 

74HC138 Circuit Schematic

VOL and VOH are typical voltage output levels that occur with the output load.

 

Waveforms and test circuit

Waveforms and test circuit

 

74HC138 Logic Diagram

The following figure shows the logic diagram of 74HC138.

 

74HC138 Logic Diagram

74HC138 Logic Diagram

 

74HC138 Block Diagram

The following figure shows the block diagram of 74HC138.

 

74HC138 Block Diagram

74HC138 Block Diagram

 

74HC138 Package

The following diagram shows the 74HC138 package.

 

74HC138 Package

74HC138 Package

 

74HC138 Specification

Brand Name: NXP Semiconductor
Length: 5 mm
Load Capacitance (CL): 50 pF
Operating Temperature-Max: 125 °C
Operating Temperature-Min:  -40 °C
Peak Reflow Temperature (Cel): 260
Power Supplies: 2/6 V
Prop. Delay@Nom-Sup: 45 ns
Propagation Delay (tpd): 225 ns
Supply Voltage-Max (Vsup): 6 V
Supply Voltage-Min (Vsup): 2 V
Supply Voltage-Nom (Vsup): 5 V
Subcategory: Decoder/Drivers

 

74HC138 Manufacturer

NXP Semiconductors N.V. enables secure connections for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile and communication infrastructure markets.

 

74HC138 Datasheet

You can download 74HC138 datasheet from the link given below:

74HC138 Datasheet

 

Using Warnings

Note: Please check their parameters and pin configuration before replacing them in your circuit.

 

74HC138 FAQ

What is a 74HC138?

The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3.

 

What is a 3 to 8 decoder?

A 3 to 8 decoder has three inputs (A,B,C) and eight outputs (DO to D7). Based on the 3 inputs one of the eight outputs is selected. The truth table for 3 to 8 decoder is shown in table (1).

 

What are the advantages of 3 to 8 line decoder in computer interfacing?

3 to 8 line Decoder has a memory of 8 stages. It is convenient to use an AND gate as the basic decoding element for the output because it produces a “HIGH” or logic “1” output only when all of its inputs are logic “1”. You can clearly see the logic diagram is developed using the AND gates and the NOT gates.

 

When a decoder can be used as a demultiplexer?

A decoder with an enable input can function as a Demultiplexer. A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. Selection of a specific output line is controlled by the bit values of n selection lines.

 

What does a decoder do in a circuit?

A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders because they are simpler to design.

74HC138D,653 Documents & Media

Download datasheets and manufacturer documentation for Nexperia USA Inc. 74HC138D,653.

74HC138D,653 PCB Symbol, Footprint & 3D Model

Nexperia USA Inc. 74HC138D,653

Nexperia USA Inc.

NEXPERIA - 74HC138D,653 - 74HC CMOS SMD 74HC138,SOIC16

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