Three-state Buffer Basic and Verilog HDL Simulation

3373

Author: Kynix

Published: 2022-01-13 | Last Updated: 2022-01-13

Contents

Introduction

In the computer field, a buffer refers to a buffer register, which is divided into two types: input buffer and output buffer. The function of the former is to temporarily store the data sent by the peripheral so that the processor can take it away; the latter is to temporarily store the data sent by the processor to the peripheral. With the numerical control buffer, the high-speed CPU and the slow-speed peripherals can coordinate and buffer to realize the synchronization of data transmission. Since the buffer is connected to the data bus, it must have a three-state output function.

Catalog

Introduction

Ⅰ Three-State Buffer Meaning

Ⅱ Buffers in the Java Language

2.1 Buffer

2.2 Data Transmission

2.3 Mark and Reset

2.4 Invariants

2.5 Clear Reverse Rewind

Ⅳ Verilog HDL Model and Simulation of Tri-state Buffer

4.1 Tri-state Buffer IC

4.2 Application Example of 74LS541 as Input Port

4.3 Multiplexer (MUX)

Ⅴ FAQ

Ⅰ Three-State Buffer Meaning

Three-state buffer (tri-state buffer), also known as three-state driver, its three-state output is controlled by the enable output terminal. When the enable output is valid, the device realizes normal logic state output (logic 0, logic 1); when the enable input is invalid, the output is in a high-impedance state, which is equivalent to disconnecting from the connected circuit.

Figure 1. Tristate Buffers

A buffer is one of the digital components, it does not perform any operation on the input value, and its output value is the same as the input value. It plays an important role in the design of the computer. There are two types of buffers. In addition to tri-state buffers, there are also conventional buffers (regular buffers).
Conventional buffers always output the value directly, which is used to output current to higher-level circuitry. The tri-state buffer has an optional card input, denoted by E, in addition to the functions of a conventional buffer. E=0 and E=1 have different output values.

Tristate Buffer Symbols

Figure 2. Tristate Buffer Symbols

When E=1, it is gated, and its input is directly sent to the output.
If E=0, the buffer is blocked. No matter what value is input, the output is always high impedance. The high-impedance state can drop the current low enough that the buffer-like output is not connected to anything.
In the design of the CPU, the DC load capacity of the general output line can drive a TTL load, and in the connection, an address line or data line of the CPU may be connected to multiple memory chips, but the memory chips are all MOS circuits. It is a capacitive load, and the DC load is much smaller than the TTL load. Therefore, in a small system, the CPU can be directly connected to the memory, but a buffer needs to be added in a large system.
In order to reduce the number of information transmission lines, the information transmission lines in most computers are in the form of buses, that is, all the same type of information to be transmitted goes through the same group of transmission lines, and the information is transmitted in time-sharing. There are generally three groups of buses in the computer, namely the data bus, the address bus and the control bus. In order to prevent information from interfering with each other, it is required that any register or memory hung on the bus, etc., its transmission end can not only show two information states of 0 and 1, but also should be able to show a third state-high impedance state. That is, it seems that their outputs are disconnected at this time, which has no effect on the bus state, and the bus can be occupied by other devices at this time. The above functions can be realized. In addition to the input and output terminals, it also has a control terminal, please see the figure below.

Three-state Output Buffer Register

Figure 3. Three-state Output Buffer Register

When E=1, the output=input, the bus is driven by the device at this time, and the data on the bus is determined by the input data.
When E=0, the output terminal is in a high-impedance state, and the device has no effect on the bus. When the output terminal of the register is connected to the three-state gate, and then the output terminal of the three-state gate is connected with the bus, the stage-rush register of the three-state output is formed. Since the one-way tri-state gate is used here, the data can only be output from the register to the data bus. If you want to achieve bidirectional transmission, you will use a bidirectional tri-state gate.

Three-state Gate

Figure 4. Three-state Gate

Ⅱ Buffers in the Java Language

2.1 Buffer

Directly known subclasses of java.nio.Buffer: ByteBuffer, CharBuffer, DoubleBuffer, FloatBuffer, IntBuffer, LongBuffer, ShortBuffer public abstract classBufferextendsObject. A container for data of a specific basic type.
A buffer is a linear finite sequence of elements of a particular primitive type. In addition to content, the basic properties of a buffer include capacity, limitation, and location.
1) The capacity of a buffer is the number of elements it contains. The capacity of the buffer cannot be negative and cannot be changed.
2) The limit of the buffer is the index of the first element that should not be read or written. A buffer's limit cannot be negative and cannot be larger than its capacity.
3) The position of the buffer is the index of the next element to be read or written. The buffer's position cannot be negative and cannot be larger than its limit. This class has a subclass for each non-boolean primitive type.

2.2 Data Transmission

Each subclass of this class defines two get and put operations:
A relative operation reads or writes one or more elements, starting at the current position and incrementing the position by the number of elements transferred. If the requested transfer exceeds the limit, a relative get operation will throw a BufferUnderflowException, and a relative put operation will throw a BufferOverflowException. In both cases, no data is transferred.
Absolute operations take explicit element indices, which do not affect position. Absolute get and put operations will throw IndexOutOfBoundsException if the index parameter exceeds the limit. Of course, I/O operations through the appropriate channel (usually related to the current position) can also transfer data to and from the buffer.

2.3 Mark and Reset

The mark is an index to which the buffer's position is reset when the reset method is called. It is not always necessary to define a marker, but when defining a marker, you cannot define it as a negative number, and you cannot make it larger than the position. If a marker is defined, it will be discarded when the position or limit is adjusted to a value less than the marker. Calling the reset method will cause an InvalidMarkException to be thrown if the mark is not defined.

2.4 Invariants

Mark, position, limit, and capacity values obey the following invariants:
0<=mark<=position<=limit<=capacity, newly created buffers always have a 0 position and an undefined mark. The initial limit can be 0 or some other value, depending on the buffer type and how it is built. In general, the initial contents of the buffer are undefined.

2.5 Clear Reverse Rewind

In addition to methods for accessing position, limitation, capacity values, and methods for marking and resetting, this class defines the following operations that can be performed on buffers.
clear() prepares the buffer for a series of new channel reads or relative put operations. It sets the limit to the capacity size and the position to 0.
flip() prepares the buffer for a series of new channel write or relative get operations. It sets the limit to the current position, then the position to 0.
rewind() prepares the buffer for rereading already contained data. It leaves the limit unchanged, setting the position to 0.

2.6 Read-Only Buffer

Every buffer is readable, but not every buffer is writable. The mutate method of each buffer class is designated as an optional operation and will throw a ReadOnlyBufferException when called on a read-only buffer. A read-only buffer does not allow changes to its contents, but its tag, position, and limit values are mutable. Its isReadOnly method can be called to determine whether the buffer is read-only.

2.7 Thread Safety

It is not safe for multiple current threads to use the buffer. If it is used by more than one thread, access to that buffer should be controlled through appropriate synchronization.

2.8 Call Chain

Specifies that methods in this class return the buffer on which they were called (otherwise they would return no value). This operation allows method calls to be formed into a chain, like a sequence of statements
b.flip(); b.position(23); b.limit(42); can be replaced by the following short statement b.flip().position(23).limit(42);

Ⅲ EDA Code

library ieee;
use IEEE.STD_LOGIC_1164.all;
ENTITY BUF3S IS
PORT (INPUT:IN STD_LOGIC;ENABLE:IN STD_LOGIC;OUTPUT:OUT STD_LOGIC);
END BUF3S;
ARCHITECTURE BHV OF BUF3S IS
BEGIN
PROCESS(ENABLE,INPUT)
BEGIN
IF ENABLE='1'
THEN OUTPUT<=INPUT;
ELSE OUTPUT<='Z';
END IF;
END PROCESS;
END BHV;

Ⅳ Verilog HDL Model and Simulation of Tri-state Buffer

Verilog HDL Model and Simulation of Tristate Buffer

Figure 5. Verilog HDL Model and Simulation of Tristate Buffer

4.1 Tri-state Buffer IC

Tristate buffers are often used for multiple data sources to share a (group) common line (bus).

For multiple data sources

Figure 6. For Multiple Data Sources

When all enable terminals of the decoder are valid, the combination of SS2~SS0 makes only one of /SELP~/SELW valid at the same time, so that one of the 8 data sources P~W drives SDATA. When the enable terminal is invalid, then none of the three-state gates are enabled, and the outputs are all high impedance.
The MSI device 74LS541 contains 8 independent tri-state gates and shares two enable inputs. The logic diagram and logic symbols are as follows:

74LS541 Logic Diagram and Logic Symbol

Figure 7. 74LS541 Logic Diagram and Logic Symbol

4.2 Application Example of 74LS541 as Input Port

Application Example of 74LS541 as Input Port

Figure 8. Application Example of 74LS541 as Input Port

The MSI device 74LS245 is an 8-bit tri-state bus transceiver with an enable output G and a direction selection input DIR to determine the transmission direction: when DIR=1, data is transmitted from A to B; when DIR=0, data is transmitted from B passed to A. The logic diagram and logic symbols are as follows:

74LS245 Logic Diagram and Logic Symbol

Figure 9. 74LS245 Logic Diagram and Logic Symbol

Bus

Figure 10. Bus

Verilog HDL Model of 8-bit Tri-state Bus Transceiver

Figure 11. Verilog HDL Model of 8-bit Tri-state Bus Transceiver

4.3 Multiplexer (MUX)

Multiplexers are also called data selectors, and are often abbreviated as MUX. It is a combinational logic circuit with multiple inputs and single outputs, denoted as n/1 or n-1.
Logic function: Since the enable terminal EN is valid., when selecting the control variable, select one of the multiple input data to the output terminal.

MUX

Figure 12. MUX

Each value group of the n selection control variables corresponds to select one of the m=2n input data and then send it to the output terminal.
Design of Commonly Used Multiplexers
🔺8 to 1 Multiplexer

8 to 1 Multiplexer Function Description

Figure 13. 8 to 1 Multiplexer Function Description

8 to 1 Logic Circuit Diagram

Figure 14. 8 to 1 Logic Circuit Diagram

Circuit package, Logic symbol

Circuit Package

Figure 15. Circuit Package

Logic Symbol

Figure 16. Logic Symbol

1 Out of 8 Verilog HDL Models

1 Out of 8 Verilog HDL Model

Figure 17. 1 Out of 8 Verilog HDL Model

8 Out of 1 Functional Simulation

Figure 18. 8 Out of 1 Functional Simulation

🔺8 Out of 1 Multiplexer with Tri--state Output

Function Description

Figure 19. Function Description

8 to 1 Logic Circuit Diagramof Three-state Output

Figure 20. 8 to 1 Logic Circuit Diagramof Three-state Output

Circuit Package, Logical Symbol

74LS251 Circuit Package and Logical Symbol

Figure 21. 74LS251 Circuit Package and Logical Symbol

1 Out of 8 Verilog HDL Model for Tri-state Output

Figure 22. Verilog HDL Model

Ⅴ FAQ

1. What is a buffer software?
A reserved segment of memory within a program that is used to hold the data being processed. Buffers are set up in every program to hold data coming in and going out. In a video streaming application, the program uses buffers to store an advance supply of video data to compensate for momentary delays.

2. Is buffer safe to use?
Buffer is a reliable, fast way to manage multiple social media accounts, from a user-friendly dashboard.

3. Why do we need buffering in OS?
Computers have many different devices that operate at varying speeds, and a buffer is needed to act as a temporary placeholder for everything interacting. This is done to keep everything running efficiently and without issues between all the devices, programs, and processes running at that time.

4. Is a buffer hardware or software?
A buffer is a data area shared by hardware devices or program processes that operate at different speeds or with different sets of priorities. The buffer allows each device or process to operate without being held up by the other. This term is used both in programming and in hardware.

5. What is tri-state buffer?
A tri-state buffer is a logic inverter or a non-inverting buffer with a tri-state output stage. ... When the enable line is not activated the buffer output stage has a high output impedance (i.e., the Z state, as described above in section 10.15) and transmission of data is prevented.

6. What is the difference between buffer and tri-state buffer?
A tri-state buffer is similar to a buffer, but it adds an additional "enable" input that controls whether the primary input is passed to its output or not. If the "enable" inputs signal is true, the tri-state buffer behaves like a normal buffer.

7. What is meant by tri-state buffer how it helps in reading and writing data from a register?
Definition: A three-state bus buffer is an integrated circuit that connects multiple data sources to a single bus. The open drivers can be selected to be either a logical high, a logical low, or high impedance which allows other buffers to drive the bus.

8. What is tri-state TTL?
Tri-state gates have additional circuitry via which the gate outputs can be enabled or disabled. This is very useful in digital systems where devices communicate via common wires called busses. Only one device can talk at a time; the others are disabled.

9. Which of the following is also known as tri-state?
Explanation: The progression in the parallel ports provides a third register or an individual control bit which can make the pin in a high impedance state. An output port which can do this is also known as tri-state, that is, logic high, logic low and a high impedance state.

10. What is tri-state in microprocessor?
Tristate means three states viz. Logic 0, Logic 1 and high impedance states. In high impedance state, the pin neither connected to supply nor to ground. Hence impedance at this pin is very high with respect to suppy as well as ground. Some pins of 8085 have three states.

11. How many buffer may active at any given time?
At any one time, one buffer is actively being displayed by the monitor, while the other, background buffer is being drawn.

12. What is tri-state circuit?
Tristate means a digital circuit output that can have 3 states: 0, 1 and High-Z or high impedance which is the circuit equivalent of “disconnected”. There are times when you want to have multiple digital circuits connected on a bus but not interfering with each other.

Previous Article >> Next Article >>

Kynix

Kynix was founded in 2008, specializing in the electronic components distribution business. We adhere to honesty and ethics as our business philosophy and have gradually established an excellent reputation and credibility in our international business. With the accurate quotation, excellent credit, reasonable price, reliable quality, fast delivery, and authentic service, we have won the praise of the majority of customers.

Join our mailing list!

Be the first to know about new products, special offers, and more.

Phone

Three-state Buffer Basic and Verilog HDL Simulation

Introduction

Catalog

Ⅰ Three-State Buffer Meaning