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Types of Flash Memory Comparison: NAND vs NOR

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Introduction

FLASH is a type of non-volatile memory that retains data even when power is disconnected. Unlike RAM, which can rewrite data at the byte level, flash memory operates differently. A flash memory chip consists of an array of data storage cells organized into blocks, with each block containing multiple pages (typically 64 to 256 pages in modern devices, though older devices used 32 pages). A page is usually 2KB, 4KB, 8KB, or 16KB in modern NAND flash, though the original specification was 512 bytes plus spare area, as flash was initially developed as a disk replacement technology.

What Is Flash Memory?


Ⅰ Types of Flash Memory

Flash memory is widely used as a storage medium in digital cameras, smartphones, tablets, USB drives, SSDs, and various consumer electronics. Flash memory cards come in various form factors depending on manufacturers and applications, including USB flash drives, CompactFlash (CF card), MultiMediaCard (MMC card), Secure Digital (SD card, microSD), Memory Stick, and XD-Picture Card (XD card). Note that SmartMedia (SM card) and Microdrive have been discontinued. While these flash cards have different physical formats and specifications, their underlying technical principles remain similar.
Flash memory includes two main architectural types: NOR Flash and NAND Flash. NOR Flash is a random access device with dedicated address and data lines (similar to SRAM), allowing byte-level read and write operations and direct access to any memory location, making it an excellent ROM alternative, such as in computer BIOS chips. NAND Flash, however, lacks dedicated address lines and cannot be directly addressed. It is controlled by sending commands and addresses through an I/O interface, meaning NAND Flash can only be accessed in pages, making it more suitable for sequential data storage.

Types of Flash Memory

Ⅱ NAND Flash Memory

NAND Flash is extensively used in high-capacity storage devices such as memory cards, USB drives, SSDs, eMMC, and UFS storage. NAND Flash cells are categorized by the number of bits stored per cell: SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell). SLC stores 1 bit per cell, MLC stores 2 bits, TLC stores 3 bits, and QLC stores 4 bits per cell.
As more bits are stored in a single cell, the read/write performance decreases, endurance diminishes, but cost per gigabyte is reduced, making higher-density options more economical for consumer applications.

Items

SLC

MLC

TLC

QLC

Bits Per Cell

1

2

3

4

P/E Cycles

50,000-100,000

3,000-10,000

1,000-3,000

100-1,000

Read Time (μs)

25

50

75

100

Program Time (μs)

200-300

600-900

900-1350

1350-2000

Erase Time (ms)

1.5-2

3

4.5

6-8


SLC is primarily used in enterprise, industrial, and military applications due to its high-speed writing, low error rate, and exceptional durability.
MLC is targeted at consumer and prosumer applications, offering twice the capacity of SLC at lower cost. It's suitable for USB drives, smartphones, digital cameras, and consumer-grade SSDs.
TLC has become the mainstream choice for consumer SSDs and SD cards due to its balance of cost, capacity, and acceptable performance for everyday use.
QLC, introduced more recently, offers even higher density and lower cost per gigabyte, making it increasingly popular in budget SSDs and high-capacity storage solutions, though with reduced endurance.
As a practical solid-state storage medium, NAND Flash has unique physical characteristics requiring specialized management. Designers face several key challenges:
1) Erase-before-write requirement: Data cannot be overwritten directly; blocks must be erased before new data can be written
2) Wear mechanism: Limited program/erase (P/E) cycles impose durability constraints
3) Read/write interference: Operations can cause data errors in adjacent cells
4) Data retention: Charge leakage over time can cause data loss
5) Bad block management: Both factory defects and runtime failures must be managed


Key technologies addressing these challenges include:
1) Cell type selection: Choosing appropriate NAND type (SLC/MLC/TLC/QLC) based on application requirements
2) Wear leveling algorithms: Distributing write operations evenly across all blocks to maximize lifespan
3) Bad block management: Identifying and mapping out defective blocks to ensure data integrity
4) Error Correction Code (ECC): Detecting and correcting bit errors using advanced algorithms like BCH or LDPC
5) Write amplification mitigation: Minimizing unnecessary write operations to extend device life
6) Garbage collection: Consolidating valid data and reclaiming space from partially used blocks
Data is stored as electrical charge in Flash memory cells. The amount of stored charge depends on the voltage applied to the Control Gate, which controls whether charge is injected or removed from the floating gate.
1) For programming (writing) NAND Flash, voltage is applied to the Control Gate to inject electrons into the floating gate. When charge exceeds the threshold voltage (Vth), the cell represents a logical 0.
2) For erasing NAND Flash, electrons are removed from the floating gate. When charge falls below the threshold voltage (Vth), the cell represents a logical 1.

 

Ⅲ NOR Flash Memory

NOR Flash, similar to conventional memory, supports random access, enabling XIP (eXecute In Place) functionality. This allows code execution directly from the flash without copying to RAM, making it ideal for boot code, BIOS/UEFI firmware, and embedded system applications requiring immediate code execution.
NOR Flash is categorized into two types based on host interface: Parallel NOR Flash and Serial NOR Flash.

Parallel NOR Flash & Serial NOR Flash

Parallel NOR Flash connects directly to the host controller with its contents mapped into the CPU address space, eliminating the need to copy to RAM. Early BIOS implementations used the FWH (Firmware Hub) interface, a parallel connection that has been largely obsoleted due to pin count and speed limitations.
Serial NOR Flash is more cost-effective than Parallel NOR Flash and typically connects to the host processor or Platform Controller Hub (PCH) via SPI (Serial Peripheral Interface), Quad-SPI (QSPI), or Octal-SPI interfaces. Modern implementations support higher speeds through multi-lane configurations.
Today, virtually all UEFI/BIOS firmware, embedded systems, IoT devices, and many consumer electronics use NOR Flash. Typical capacities range from 1MB to 256MB, with 16MB-128MB being common for modern UEFI implementations. While more expensive per gigabyte than NAND, NOR Flash offers superior reliability and random access performance.
NOR Flash has slower erase speeds and lower erase cycle counts compared to NAND, but these limitations rarely impact BIOS/firmware performance or cause device failures due to the infrequent update nature of firmware.

 

Ⅳ NAND Flash vs NOR Flash

Compared with NOR flash memory, NAND flash memory requires fewer transistors per cell to store the same amount of data, resulting in smaller die size and higher storage density. This architectural difference makes NAND significantly more cost-effective for high-capacity storage applications.
In terms of read speed, NOR flash memory offers faster random access than NAND flash memory, with typical access times of 50-100ns compared to NAND's page-based access. However, NAND flash memory significantly outperforms NOR in sequential write and erase operations. NAND's block-based erase operation is simpler and faster, erasing entire blocks (typically 128KB-4MB) at once.
NOR flash memory requires all bits to be set to 1 during erase operations before programming. While NOR flash memory provides faster random access and simpler byte-level operations, its lower storage density and higher cost make it more suitable for code storage and execution. NAND flash memory provides extremely high cell density (modern single chips can exceed 1TB capacity), making it ideal for mass data storage with fast write and erase speeds. Additionally, NAND flash operates on page-based read/write units (typically 4KB-16KB) and block-based erase units, making it functionally similar to traditional disk drives.
NAND Flash is more susceptible to bit errors than NOR Flash, necessitating robust Error Detection and Correction (EDC/ECC) algorithms. Modern NAND implementations use advanced ECC schemes like BCH (Bose-Chaudhuri-Hocquenghem) or LDPC (Low-Density Parity-Check) codes. Additionally, NAND Flash develops bad blocks over its lifetime. File systems like FAT on SD cards experience frequent rewrites of the file allocation table, and the P/E cycle count per block is critical to NAND Flash longevity. Balancing erase cycles across all blocks and managing bad blocks requires specialized firmware-level functionality including bad block management, wear leveling, ECC, and garbage collection. This management layer is called the FTL (Flash Translation Layer). Based on FTL implementation location, Flash Memory is categorized as Raw Flash or Managed Flash.

Raw Flash & Managed Flash

Raw Flash requires the host system to implement FTL functionality, giving designers complete control but requiring significant software development. Managed Flash (such as eMMC, UFS, SD cards) includes an integrated controller that handles FTL operations transparently, simplifying host system design at the cost of reduced low-level control.

Ⅴ Universal Flash Storage Versions Comparison

Storage performance significantly impacts device responsiveness and user experience. Universal Flash Storage (UFS) has become the dominant standard for high-performance mobile and embedded storage, replacing the older eMMC standard. UFS provides a standardized flash storage specification optimized for smartphones, tablets, automotive systems, and other performance-critical applications. Version numbers indicate generational improvements, with higher versions offering substantially better performance, features, and efficiency.
✔️Version Comparison (Main Parameters)

UFS Version

1.0

1.1

2.0

2.1

3.0

3.1

4.0

Introduced

2011-02-24

2012-06-25

2013-09-18

2016-04-04

2018-01-30

2020-01-30

2023-09-14

Bandwidth per lane

300 MB/s

600 MB/s

1450 MB/s (HS-G3)
2900 MB/s (HS-G4)

5800 MB/s (HS-G5)

Max. number of lanes

1

2

Max. total bandwidth

300 MB/s

1200 MB/s

2900 MB/s (HS-G3)
5800 MB/s (HS-G4)

11600 MB/s (HS-G5)

M-PHY version

1.0

3.0

4.1

5.0

UniPro version

1.4

1.6

1.8

2.0


✔️UFS 2.1 vs UFS 2.2
The primary enhancement in UFS 2.2 over UFS 2.1 is the Write Booster feature, which significantly improves write performance. Write Booster uses SLC (Single-Level Cell) cache to accelerate write operations, providing faster application launches, improved browser cache loading, reduced video encoding times, and enhanced overall system responsiveness. This feature is particularly beneficial for burst write scenarios common in mobile devices.
As eMMC has been phased out from mainstream consumer devices and NAND flash prices have decreased, UFS adoption has accelerated. UFS 2.2 briefly served as a transitional standard before UFS 3.x became mainstream in flagship devices.

✔️UFS 3.0 vs UFS 3.1
UFS 3.1 introduces three significant enhancements over UFS 3.0:
1) Write Booster (Enhanced)
Write Booster in UFS 3.1 is an enhanced version that increases device write speed substantially. This feature can boost write speeds up to 700 MB/s, compared to UFS 3.0's typical sequential write performance of around 500 MB/s. The mechanism works similarly to SLC caching in SSDs: a portion of TLC/QLC storage is dynamically configured to operate in SLC mode, providing faster write performance. Data is initially written to this high-performance buffer, then migrated to standard storage during idle periods, freeing the cache for subsequent operations.
2) Deep Sleep Mode
Deep Sleep enables the flash memory to enter an ultra-low-power state during extended idle periods, significantly reducing standby power consumption. This feature helps extend battery life during device standby and contributes to overall device thermal management. Deep Sleep can reduce idle power consumption by up to 40% compared to standard sleep modes.
3) Host Performance Booster (HPB)
HPB addresses long-term performance degradation by improving random read performance. As devices are used over time, file system fragmentation and the need to frequently reload the Logical-to-Physical (L2P) mapping table can cause performance degradation. HPB leverages the host device's RAM to cache portions of the L2P mapping table, reducing latency for random read operations. This is particularly effective at maintaining consistent performance after extended use, preventing the "slowdown over time" phenomenon common in storage devices. HPB can improve random read IOPS by up to 70% in fragmented scenarios.

✔️UFS 4.0 - The Latest Generation
Released in September 2023, UFS 4.0 represents the latest advancement in mobile storage technology. Key improvements include:
Doubled bandwidth: Up to 11.6 GB/s (5800 MB/s per lane with dual-lane configuration) using HS-G5 gear
Improved power efficiency: Lower power consumption per bit transferred compared to UFS 3.1
Enhanced thermal management: Better heat dissipation characteristics for sustained performance
Advanced features: Builds upon Write Booster, Deep Sleep, and HPB with further optimizations
UFS 4.0 is designed for next-generation flagship smartphones, tablets, and high-performance mobile devices requiring extreme storage bandwidth for 8K video recording, advanced computational photography, and AI workloads.

 

Frequently Asked Questions about Flash Memory

1. What are the different types of flash memory?
Flash memory comes in two fundamental architectural types: NOR and NAND. NOR flash offers random access and execute-in-place capabilities, making it ideal for code storage. NAND flash provides higher density and faster write speeds, making it suitable for data storage. Within NAND flash, there are further subdivisions based on bits per cell: SLC (1 bit), MLC (2 bits), TLC (3 bits), and QLC (4 bits), each offering different trade-offs between performance, endurance, and cost.

 

2. What are the characteristics of flash memory?
Flash memory has several distinctive characteristics: it is significantly less expensive than EEPROM and doesn't require batteries for data retention unlike SRAM. It is non-volatile, meaning data persists without power. Flash offers fast read access times (microseconds), high resistance to physical shock compared to hard disk drives, low power consumption, and silent operation. However, it has limitations including finite write/erase cycles, block-level erase requirements, and potential for bit errors requiring ECC.

 

3. What is the purpose of flash memory?
Flash memory serves as a non-volatile storage solution widely used in embedded systems, consumer electronics, and enterprise storage. It retains data without power, can be electrically erased and reprogrammed, and offers advantages over traditional magnetic storage including faster access times, lower power consumption, better durability, and compact form factors. Flash memory evolved from EEPROM technology and has become the dominant storage technology for mobile devices, SSDs, USB drives, memory cards, and embedded systems.

 

4. What is the difference between NAND flash and NOR flash?
NOR flash provides faster random read access and supports execute-in-place (XIP), allowing direct code execution without copying to RAM, making it ideal for firmware and boot code. However, it's more expensive and has slower erase/write operations. NAND flash offers higher storage density, lower cost per gigabyte, and much faster sequential write and erase speeds, making it ideal for mass storage applications. NAND is accessed serially through a shared I/O interface, while NOR has parallel address and data buses allowing random access. NAND requires more complex error correction due to higher bit error rates.

 

5. What is the difference between UFS and eMMC?
UFS (Universal Flash Storage) is the successor to eMMC (embedded MultiMediaCard) and offers several significant advantages: UFS supports full-duplex operation allowing simultaneous read and write operations, while eMMC is half-duplex. UFS uses a faster serial interface with higher bandwidth (up to 11.6 GB/s in UFS 4.0 vs. 400 MB/s in eMMC 5.1). UFS also features command queuing for better multitasking performance, lower latency, and improved power efficiency. These advantages make UFS the preferred choice for modern flagship smartphones and high-performance mobile devices.

 

6. How does wear leveling work in flash memory?
Wear leveling is a technique used to extend flash memory lifespan by distributing write and erase cycles evenly across all memory blocks. Since flash memory has a limited number of program/erase cycles per block, repeatedly writing to the same blocks would cause premature failure. Wear leveling algorithms track the erase count of each block and preferentially use blocks with lower erase counts for new writes. This ensures all blocks wear out at approximately the same rate, maximizing the overall device lifespan. Modern flash controllers implement sophisticated wear leveling algorithms as part of the Flash Translation Layer (FTL).

 

7. What is 3D NAND technology?
3D NAND (also called V-NAND) is a flash memory architecture that stacks memory cells vertically in multiple layers, rather than arranging them in a single planar layer. This technology allows for higher storage densities without requiring smaller manufacturing process nodes. Modern 3D NAND implementations can have over 200 layers, significantly increasing capacity while improving performance and endurance compared to planar NAND. 3D NAND also offers better power efficiency and can achieve higher performance due to reduced cell-to-cell interference. This technology has become the standard for modern SSDs and high-capacity storage devices.

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