ON Semiconductor SCANPSC110FSC

General Description

The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

Features

■ True IEEE1149.1 hierarchical and multidrop addressable capability
■ The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses
■ 3 IEEE 1149.1-compatible configurable local scan ports
■ Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three
■ 32-bit TCK counter
■ 16-bit LFSR Signature Compactor
■ L4
■ local TAPs can be 3-stated via the OE input to allow an alternate test master to take control of the local TAPs