Xilinx XC1718DPC

The General Purpose Timer Units

The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Each block has alternate input/output functions and specific interrupts associated with it.
Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. These registers are listed in Section 14.1.6.

• fGPT/4 maximum resolution

• 3 independent timers/counters
• Timers/counters can be concatenated
• 4 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
– Incremental Interface Mode
• Reload and Capture functionality
• Separate interrupt lines

Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended functionality. These registers are listed in Section 14.2.7. The core timer T6 may be concatenated with timers of the CAPCOM units (T0, T1, T7, and T8).

The following list summarizes the features which are supported:

• fGPT/2 maximum resolution

• 2 independent timers/counters
• Timers/counters can be concatenated
• 3 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
• Extended capture/reload functions via 16-bit capture/reload register CAPREL
• Separate interrupt lines