Description
The EF-DI-ERNIC-SITE is a programmable system-on-chip (SoC) platform and IP core that integrates high-density FPGA logic with dual-core processing units. It implements hardware-based RDMA over Converged Ethernet (RoCE v2) to support hardware acceleration and embedded Linux environments. The architecture provides a 100Gb/s data path with verified 40G throughput, achieving end-to-end round-trip times below 3μs and a 2.3μs P99 latency at 250MHz. It supports up to 254 persistent RDMA connections and achieves timing closure with 0.8ns slack at 200MHz. The system power budget ranges from 50W to 100W for high-speed configurations. Target applications include high-frequency trading, distributed storage, industrial motor control, medical, and aerospace sectors.
Features
- Integrates a dual-core processor system designed for hardware-accelerated embedded Linux environments.
- Implements hardware RoCE v2 via dedicated IP to provide lower latency than software-based RDMA solutions.
- Delivers sub-3μs end-to-end round-trip times (RTT) over 40G communication interfaces.
- Supports a maximum of 254 persistent RDMA connections for high-frequency trading and distributed storage clusters.
- Operates at clock frequencies up to 250MHz with a 2.3μs P99 latency on high-performance architectures.
- Provides a 100Gb/s data path with a verified 40G throughput capacity.
- Requires a system power budget of 50W to 100W for combined FPGA and PHY configurations in high-speed applications.
- Achieves timing closure with 0.8ns slack at 200MHz through optimized placement and routing.
Applications
- Communication Interfaces
- High-Speed Data Links
Faqs
Q:What is the current lifecycle status and application range for the Zynq platform?
A:The Zynq platform remains active in new designs for medical devices, industrial motor drives, and aerospace prototypes.
Q:What is the compatibility of the ERNIC IP core with newer FPGA families?
A:ERNIC is a 2019 IP core for 7-series and UltraScale FPGAs; there is no official documentation regarding support or porting to newer architectures.
Q:What design optimizations are required for high Queue Pair counts in Zynq UltraScale+ implementations?
A:Implementing 254 Queue Pairs may require specific placement and routing optimizations, such as Performance_refinePlacement, to achieve timing closure.
Q:What are the performance limitations of the 100Gb/s data path on UltraScale+ architectures?
A:Documentation indicates that 100Gb/s throughput may be restricted or theoretical on UltraScale+ devices compared to standard UltraScale architectures.
Q:Are there alternative solutions for implementing RoCE v2 without the ERNIC IP license?
A:No compliant, hardware-accelerated alternatives exist for implementing RoCE v2 on Zynq UltraScale+ platforms without the dedicated ERNIC IP license.
Q:How does the hardware evaluation license impact the design flow?
A:Evaluation licenses for the ERNIC IP typically expire during the design implementation phase rather than interrupting active data transfers.
Q:What's the real-world throughput I can expect from this RDMA NIC in a Zynq-7000 vs Ultrascale?
A:You’re asking for throughput numbers on an RDMA NIC across Zynq-7000 vs Ultrascale, but the doc doesn’t give you a single number. Not one. No Mbps, no Gbps, no latency figures. Nothing.
Q:Anyone used ERNIC IP in a Zynq UltraScale+ design? How bad is the timing closure beyond 127 QPs without Performance_refinePlacement?
A:I’ve used ERNIC in a Zynq UltraScale+ design—255 QPs, no tricks, just pure silicon pain.
Real talk: if you try to push past 127 QPs without `Performance_refinePlacement`, you’re asking for a timing c...
Q:Anyone used the ERNIC IP on Zynq UltraScale+? How's the latency in real apps?
A:I’ve used ERNIC on a Zynq UltraScale+ in a low-latency trading rig—real talk, it’s not magic, but it’s close when done right.
The docs say “low latency” and “hardware offloaded”—yeah, that’s true.
Q:Does ERNIC actually handle 100Gb/s on UltraScale+ devices, or is that just theoretical?
A:The 100Gb/s claim is technically true—but only if you’re not using UltraScale+ devices.
I’ve used this IP in a few designs, and here’s the catch: the doc literally says in Note 3: “For UltraScale dev...