TE Connectivity 640136-6

DESCRIPTION

The IDT79R4640 is a low-cost member of the Integrated Device Technology, Inc. ORION family, targeted to a variety of performance-hungry embedded applications. The R4640 continues the ORION tradition of high-performance through high-speed pipelines, high-bandwidth caches and bus interface, 64-bit architecture, and careful attention to efficient control. The cost of this performance is reduced by removing functional units frequently not required for many embedded applications.

FEATURES

• High-performance embedded 64-bit microprocessor
- 64-bit integer operations
- 64-bit registers
- Based on the MIPS RISC Architecture
- 80MHz, 100MHz, 133 MHz and 150MHz operation frequency
- 32-bit bus interface brings 64-bit power to 32-bit system cost
• High-performance DSP capability
- 75 Million Integer Mul-Accumulate operations/sec @150MHz
- 50 MFlops floating-point operations @150MHz
• High-performance microprocessor
- 75 M Mul-Add/second @150MHz
- 50 MFlops @150MHz
- >340,000 dhrystone (2.1)/sec capability @133MHz (197 dhrystone MIPS)
• High level of integration
- 64-bit, 150 MHz integer CPU
- 50MFlops single-precision floating-point unit
- 8KB instruction cache; 8KB data cache
- Integer multiply unit with 75M Mul-Add/sec
• Upwardly software compatible with IDT RISController Family
• Easily upgradable to 64-bit system
• Low-power operation
- Active power management powers-down inactive units
- Standby mode
• Large, efficient on-chip caches
- Separate 8KB Instruction and 8KB Data caches
- Over 1800MB/sec bandwidth from internal caches
- 2-set associative
- Write-back and write-through support
- Cache locking to facilitate deterministic response
- High performance write protocols for graphics and data communications
• Bus compatible with ORION family
- System interfaces to 67 MHz, provides bandwidth up to 266 MB/sec
- Direct interface to 32-bit wide systems
- Synchronized to external reference clock for multimaster operation
• Improved real-time support
- Fast interrupt decode
- Optional cache locking