Intel EN82527

[INNOVASIC]

General Description

CAN protocol uses a multi-master CSMA/CR (Carrier Sense, Multiple Access with Collision
Resolution) bus to transfer message objects between network nodes.
The IA82527 support CAN Specification 2.0 Part A and B, standard and extended message
frames, and has the capability to transmit, receive, and perform message filtering on standard and
extended message frames.
The IA82527 can store 15 message objects of 8-byte data length. Each message object can be
configured as either transmit or receive except for message object 15, which is receive-only.
Message object 15 also provides a special acceptance mask designed to filter message identifiers
that are received.
The IA82527 also provides a programmable acceptance mask that allows users to globally mask
any identifier bits of the incoming message. This global mask can be used for both standard and
extended message frames.
The IA82527 is capable of operating at 5.0 or 3.3 volts. This datasheet discusses both modes of
operation. Where applicable, characteristics specific to either 3.3 or 5.0 volt operation are
identified separately throughout this datasheet.
The IA82527 is manufactured in a reliable 5-volt process technology and is available in 44-lead
PLCC or PQFP RoHS packages for the automotive temperature range (-40°C to 125°C).

Features

The primary features of the IA82527 are as follows:
• CAN Protocol Support
– Specification 2.0, Part A and Part B
– Standard ID Data and Remote Frames
– Extended ID Data and Remote Frames
• CAN Bus Interface
– Configurable Input Comparator
– Configurable Output Driver
– Programmable Bit Rate
• Global Mask, Programmable
– Standard Message Identifier
– Extended Message Identifier
• Message Objects
– 14 Transmit/Receive Buffers
– 1 Double Buffered Receive Buffer with Programmable Mask
• Flexible Status Interface
• CPU Interface Options
– 16-Bit Multiplexed Intel Architecture
– 8-Bit Multiplexed Intel Architecture
– 8-Bit Multiplexed Non-Intel Architecture
– 8-Bit Non-Multiplexed Non-Intel Architecture
– Serial (SPI)
• I/O Ports (2)
– 8-Bit
– Bidirectional
• Flexible Interrupt Structure
• Programmable Clock Output