ADSP-2186MKSTZ-300
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Kynix Part #: KY32-ADSP-2186MKSTZ-300
Manufacturer Part#:

ADSP-2186MKSTZ-300

Product Category: Embedded - DSP (Digital Signal Processors)
Manufacturer: Analog Devices Inc.
Description: IC DSP CONTROLLER 16BIT 100LQFP
  datasheetADSP-2186MKSTZ-300 Datasheet
Package: 100-LQFP
Quantity: 2843 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: Analog Devices Inc.
Product Category: Embedded - DSP (Digital Signal Processors)
Series: ADSP-21xx
Type: Fixed Point
Packaging: Tray Alternate Packaging
Package-Case: 100-LQFP
Operating-Temperature: 0°C ~ 70°C (TA)
Mounting-Type: Surface Mount
Interface: Host Interface, Serial Port
Supplier-Device-Package: 100-LQFP (14x14)
Clock-Rate: 75MHz
Non-Volatile-Memory: External
On-Chip-RAM: 40kB
Voltage-I-O: 3.30V
Voltage-Core: 2.50V
Features, Applications

Features

Qualified for Automotive Applications. See Automotive Products on Page 64 Code compatible with all other members of the SHARC family The ADSP-2148x processors are available with unique audiocentric peripherals such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more. For complete ordering information see Ordering Guide on Page 65.

Note: This datasheet is preliminary. This document contains material that is subject to change without notice. High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory--5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM 400 MHz operating frequency

Instruction Cache 5 Stage Sequencer Core Timer Block 0 RAM/ROM Block 1 RAM/ROM Block 2 RAM Block 3 RAM

PERIPHERAL BUS SPEP BUS CORE FLAGS/ PWM3-1 PCG C-D TIMER 1-0 TWI SPI/B UART S/PDIF PCG Tx/Rx A-D ASRC PDAP/ SPORT IDP 3-0 7-0 WDT MLB CORE PWM FLAGS 3-0 AMI

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.3113 c2010 Analog Devices, Inc. All rights reserved.

Summary............................................................... 1 Table Of Contents.................................................... 2 Revision History...................................................... 2 General Description................................................. 3 Family Core Architecture........................................ 4 Family Peripheral Architecture................................ 6 I/O Processor Features......................................... 11 System Design.................................................... 12 Development Tools............................................. 12 Additional Information........................................ 13 Pin Function Descriptions....................................... 14 Specifications........................................................ 18 Operating Conditions.......................................... 18 Electrical Characteristics....................................... 19 Package Information........................................... 20 ESD Sensitivity................................................... 20 Maximum Power Dissipation................................ 20 Absolute Maximum Ratings.................................. 20 Timing Specifications.......................................... 20 Output Drive Currents......................................... 56 Test Conditions.................................................. 56 Capacitive Loading.............................................. 56 Thermal Characteristics....................................... 57 100-LQFP_EP Lead Assignment................................ 59 176-Lead LQFP_EP Lead Assignment......................... 61 Outline Dimensions............................................... 63 Surface-Mount Design......................................... 64 Automotive Products.............................................. 64 Ordering Guide..................................................... 65

The ADSP-2148x SHARCR processors are members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The processors are source code compatible with the ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (singleinstruction, single-data) mode. These new processors are 32bit/40-bit floating point processors optimized for high performance audio applications with its large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Table 1 shows performance benchmarks for the ADSP-2148x processors. Table 2 shows the features of the individual product offerings. Table 2. ADSP-2148x Family Features

Feature Maximum Instruction Rate RAM ROM Audio Decoders in ROM1 Pulse-Width Modulation DTCP Hardware Accelerator2 External Port Interface (SDRAM, AMI) Serial Ports Direct DMA from SPORTs to External Port (External Memory) FIR, IIR, FFT Accelerator MLB Interface IDP/PDAP UART DAI (SRU)/DPI (SRU2) S/PDIF Transceiver SPI TWI SRC Performance Thermal Diode VISA Support Package3

Benchmark Algorithm 1024 Point Complex FFT (Radix 4, With Reversal) FIR Filter (per Tap)1 IIR Filter (per Biquad)1 Matrix Multiply (Pipelined) Divide (y/×) Inverse Square Root

Yes Automotive Models Only Yes 1 Yes -140 dB Yes 176-Lead LQFP EPAD 100-Lead LQFP EPAD -128 dB

Audio decoding algorithms include Dolby AC-3 DTS 5.1, and Nueral Surround Decoder, MPEG-2 and AAC. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 These products contain the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. 3 The 100-lead packages of the ADSP-21483/21486/21488/ADSP-21489 processors do not contain an external port. And the ADSP-21486 processor in the 176-lead package does not contain a SDRAM controller.


Descriptions

DSP Fixed-Point 16bit 75MHz 75MIPS 100-Pin LQFP Tray
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Search Part number : "ADSP-" Included word is 15
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