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CY62128DV30L-55ZI


CY62128DV30L-55ZI
Images are for reference only See Product Specifications
Kynix Part #:KY32-CY62128DV30L-55ZI
Manufacturer Part #:CY62128DV30L-55ZI
Product Category: IC Chips
Manufacturer:Cypress Semiconductor
Description:
Package: TSOP
Quantity: 873 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Lead Time: 3(168 Hours)
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Specifications
Attribute Attribute Value
Manufacturer: Cypress Semiconductor
Product Category: IC Chips
Features, Applications

Features, Applications


Features

Very high speed: 55 ns Wide voltage range: to 3.6V Pin compatible with CY62128V Ultra-low active power Typical active current: 0.5 mA MHz Typical active current: f = fMAX Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected Packages offered a 32-lead SOIC, a 32-lead TSOP, a 32-lead Short TSOP, and a 32-lead Reverse TSOP is ideal for providing More Battery Life (MoBL?) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O<subscrip> Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE<c>(CE1 LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and


The is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This


Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.


(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature................................. to +150°C Ambient Temperature with Power Applied............................................. to +125°C Supply Voltage to Ground Potential..........................................-0.3V to VCCMAX 0.3V DC Voltage Applied to Outputs in High-Z -0.3V to VCC + 0.3V


DC Input -0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... 200 mA


Power Dissipation Operating, Icc (mA) VCC Range (V) Product CY62128DV30L CY62128DV30LL Min. 2.2 Typ. 3.0 Max. 3.6 Speed (ns) = 1 MHz Typ.[5] 0.5 Max. f = fMAX Typ.[5] Max. 10 Standby, ISB2 (μA) Typ.[5] 1.5 Max. 5 4


CY62128DV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current - CMOS Inputs Test Conditions 2.2 < VCC < 3.6 GND VI < VCC GND VO < VCC, Output Disabled f = fMAX = 1 MHz Vcc = 3.6V, IOUT = 0mA, CMOS level IOH -0.1 mA IOH -1.0 mA IOL 0.1 mA IOL 2.1 mA Min. VCC + 0.3 VCC V Typ.[5] Max. Unit V


CE1 > VCC 0.2V, L VIN > VCC - 0.2V, VIN f = fMAX (Address and Data Only), = 0 (OE, WE,) CE1 > VCC < 0.2V, VIN > VCC 0.2V or VIN L LL


Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions = 1 MHz VCC = VCC(typ) Max. 8 Unit pF


Notes: 3. VIL(min.) = -2.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.75V for pulse durations less than 20 ns. 4. Full device operation requires linear ramp of Vcc from 0V to Vcc(min) and Vcc must be stable at Vcc(min) for s. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), 25°C. 6. Tested initially and after any design or proces changes that may affect these parameters.



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CY62128DV30L-55ZI Related Product Picture
  • CY62128ELL-45SXIT
  • CY62128L-70ZC
  • CY62128VLL-55ZI
  • CY62136EV30L-45ZSXI
  • CY62136VLL-70ZI
  • CY62137CVSL-70BAIT
  • CY62137VLL-70ZE
  • CY62146DV30LL-55BVXIT
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  • CY62147EV30LL-45BVXI
  • CY62148BLL-70SXI
  • CY62148ELL-45ZSXA
  • CY62148LL-70ZC
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