A Load Insensitive High-Power Balanced Power Amplifier



Warm hints: The word in this article is about 3000 words and  reading time is about 15 minutes.

Summary

A high-output-power balanced power amplifier is designed with power-combining architecture for satellite communication terminals. The power-combining architecture introduces a ±45° phase shift in the output matching network of two amplifiers, which makes the balanced power amplifier more tolerant to load mismatch and less sensitive to load variation. This balanced power amplifier is implemented with InGaP/GaAs HBT process. Under the band of 1.5 GHz to 1.7 GHz and the supply voltage of 5 V, the measured results show that 32 dB of the gain, 38 dBm of the saturated output power and 43% of power added efficiency (PAE) are achieved, and a good radio frequency performance can be maintained under load mismatch conditions.

CoreHigh-Power Balanced Power AmplifierPurposeDesigned for satellite communication terminals
English namePower amplifierCategoryPower semiconductor device
FunctionIncreasing the power of a signalFeature More tolerant to load mismatch and less sensitive to load variation



Catalogs

CatalogsⅠ. Introduction of Power Amplifier1.3 High power balanced power amplifier2.2 Circuit Analysis
1.1 The background of power amplifierⅡ. Design and Analysis of balanced Power AmplifierⅢ. Test result 
1.2 The wide application of power amplifier in power combination scheme2.1 Integral circuit designⅣ. Conclusion



Introduction

Ⅰ. Introduction of Power Amplifier

1.1 The background of power amplifier

In recent years, with the development of economy, satellite communication and navigation systems are widely used in electronics and automobile industry,and the demand for power amplifiers of handheld terminal transmitters is increasing.These power amplifiers require greater power output and better stability to meet the performance requirements of satellite communications and navigation systems. Therefore, it is of great significance to study the practical and reliable high power integrated power amplifier used in the handheld terminal of satellite communication and navigation system.

The traditional single-terminal multi-stage integrated power amplifier is not only low in output power, due to the influence of its own semiconductor physical characteristics and the limitations of processing technology, heat dissipation, impedance matching, etc, but the output power will also decrease rapidly with the increase of frequency.

In order to improve the output power, the power combination technology is a practical and easy method to implement. At the same time, the balanced power amplifier is widely used in the power synthesis scheme because of its insensitive load and wider bandwidth than the single-ended power amplifier. 

1.2 The wide application of power amplifier in power combination scheme

In reference [1], a high linearity and high efficiency power amplifier is realized by balanced synthesis method. The power amplifier has the advantages of flat gain characteristics and more stability than the corresponding single-ended amplifier in a wide band.However, the introduction of orthogonal 3dB couplers at the input and output ends makes the power amplifier require more discrete devices, which is not conducive to miniaturization and integration.

In reference [2], a novel balanced synthesis architecture was used to design a load insensitive power amplifier.This kind of power amplifier adds ±45 °phase shift network to the upper input and lower output terminals, and finally combines the two power channels through the Wilkinson synthesizer at the output end. This design not only achieves high efficiency and linearity, but also has good stability when the load changes. It is widely used in 3G WCDMA mobile phone terminals. However, the introduction of Wilkinson synthesizer also brings many disadvantages, such as large insertion loss, increasing integration cost and complexity.

In reference [3], on the basis of reference [2], the ±45°phase shift network in the output end of the power amplifier is improved and optimized, the Wilkinson synthesizer is removed either, which makes the power amplifier insensitive to the load change while achieving high efficiency and high linearity.This design reduces the integrated devices, reduces the cost, and is widely used in modern 3G smart phone terminals.

1.3 High power balanced power amplifier

Based on the comprehensive consideration of output power and stability, a high power balanced power amplifier based on InGaP/GaAs HBT process, operating in the 1.5-1.7 GHz band, is designed in this article. The test results show that the balanced power amplifier has high output power and power addition efficiency (PAE), and the circuit can still maintain good RF performance when the load mismatches.

This video demonstrates the architecture and design considerations for high-power microwave amplifiers. 

The PCBs show an implementation instance of each amplifier type capable of delivering 100W of RF power. 

The datasheet of various components as well as an overall system structure are also presented.



Detail

Ⅱ. Design and Analysis of balanced Power Amplifier

2.1 Integral circuit design

Due to the superior linearity and high efficiency of HBT process in RF IC design, a balanced power amplifier working in 1.5-1.7 GHz band is designed by using InGaP/GaAs HBT process in this article. The overall circuit structure is shown in figure 1.

Figure 1 A balanced power amplifier circuit

The balanced power amplifier circuit includes the same upper and lower branch amplifiers, and the input and output matching circuits of ±45°phase-shifting networks.

In order to obtain a higher gain, the upper and lower branches are designed using a three-stage power amplifier structure, in which the first stage works in a class A to obtain a high linearity; in order to take into account the linearity and efficiency of the overall power amplifier, the second and third stages work in Class AB.

In order to achieve a good compromise between efficiency and linearity, the biasing circuit adopts self-adaptive linearizing bias.By adding one inductor and one capacitance to the input matching circuit of the upper and lower branches, the balanced power amplifier generates ±45°phase shift to the input signal, thus realizing that the upper and lower channels of the amplifier work in an orthogonal state.

A LC resonant network with a resonant frequency of 2Ω0 is added to the output matching, where Ω0 is the fundamental frequency, which is equivalent to getting a load of second harmonic short circuit at the same time, thus realizing the suppression of the second harmonic.

The structure is similar to that of F power amplifier, and is beneficial to obtain higher efficiency. The main characteristic of the circuit in this article is that the output matching circuit of the upper and lower branches added a ±45°phase shift network, the upper branch adds a -45°phase shift network with a low pass filter structure, and the lower branch adds a +45°phase shift network with a high pass filter structure. The balanced power amplifier designed by this synthetic structure has the advantages of small space usage, simple structure and easy implementation. At the same time, it can make the balanced power amplifier more tolerant to load mismatch and insensitive to the change of load.

2.2 Circuit Analysis

When the balanced power amplifier is in operation, the input signal is coupled to the A node through the blocking capacitor, and two signals are separated from the A node into the upper and lower branches respectively, because the three-stage amplifier in the upper and lower branches is exactly the same, they sharing an equal input impedance, so the power of the two signals separated at the A node is equal.

The separated signals are transmitted to the input end of the amplifier through the opposite 45°phase change of the upper and lower branches respectively, and then the orthogonal signals are amplified by the three-stage amplifier of the upper and lower branches.

The orthogonal signal of the upper and lower branches undergoes an opposite phase shift of 45° in the output matching network, so the same signal with the same phase and the same amplitude is realized at point B, and the output power of point B is the sum of those of the two amplifiers, finally the balanced power amplifier can obtain higher output power.

The balanced power amplifier is equivalent to the three-port network shown in figure 2.

Because the upper and lower branch of amplifiers are exactly the same,it can be considered that the amplifiers of the upper and lower branches have the same output reflection coefficient ΓPA. After passing through ±45°phase shift network, we can obtain ΓPAе −j2ΔΦ and ΓPAе +j2ΔΦ respectively. Therefore, the equivalent output impedance of the upper and lower branches viewed from the ab surface to the left in figure 2 is respectively as follows:


The equivalent output impedance ZL of the network viewed from the terminal to the left can be obtained in parallel by ZL1 and ZL2:

The output reflection coefficient of node B is:

By substituting formula (1)-(3) into equation (4) and simplifying, the output reflection coefficient of the balanced power amplifier is as follows:

When ΔΦ=45°, you have:

It is shown that the output reflection coefficient and VSWR of the balanced power amplifier are twice as much as that of the single branch power amplifier. Therefore, when the load mismatch occurs, the load mismatch tolerance of the balanced power amplifier is higher than that of the single-branch power amplifier after the ±45°phase shift output matching network is introduced.

Figure 2 Circuit equivalent diagram

In order to analyze the performance of the balanced power amplifier in the case of load mismatch, the equivalent circuit of figure 2 is simulated and analyzed. When the load mismatch (such as VSWR=3:1), the load impedance (normalized) of the upper and lower branch amplifiers varies with the phase ψ of the reflection coefficient Γ, as shown in figure 3.

By comparing the load impedance of the upper and lower branches, it can be seen that they have a phase difference of 180°. Because of the change of the load impedance of the upper and lower branches, the corresponding current is changed, and the phase difference of 180°occurs between the two.

The collector of the two third-stage amplifiers of the balanced power amplifier is single power supply, so the current of the upper and lower branches compensates each other, resulting in little change in the total current, as shown in Figure 4.

Therefore, when the load mismatch of the balanced power amplifier occurs, the change of working current is relatively small, that is, not sensitive to the change of load. The load insensitive effect of using this balancing architecture is similar to that of classical balanced power amplifier which is realized by using orthogonal 3 dB coupler.

Figure 3 Changes in the load of the structure (normalized) when VSWR=3:1

In the case of terminal mismatch (VSWR=3:1), the single end circuit architecture and the present balanced architecture are compared as shown in Fig. 5 with the same output power of 38 dBm.

It can be seen from figure 5 that the output power of the single-ended circuit architecture fluctuates greatly with of the phase ψ of the reflection coefficient Γ, while the output power of the balanced architecture in this article is relatively flat. At the same time, compared with the circuit architecture without phase shift, the in-phase circuit architecture has more advantages than the single-ended circuit architecture, but the output power of the balanced architecture is the flattest and can work stably.

Figure 4 Changes of current of the structure (normalized) when VSWR=3:1

Figure 5 Comparison with the output power (normalized) changes in three kinds of circuits when VSWR=3:1



Analysis

Ⅲ. Test result 

In this article, the balanced power amplifier is fabricated by InGaP/GaAs HBT technology. The three-stage amplifier and bias circuit with upper and lower branches are realized in the chip with an DIE area of 0.9 mm×0.8 mm. The choke inductor, input matching and output matching circuit are realized out of the chip. Considering the heat dissipation of the power amplifier, the whole thing is integrated on the Fr4 substrate with an area of 8 mm×8 mm. Figure 6 is the physical diagram of the circuit.The working voltage of the balanced power amplifier is 5 V and the total static current is about 310 mA. Using Agilent's network analyzer E5071C to measure the small signal S parameters S21, S11, S22 of the balanced power amplifier, as shown in figure 7:

  • S21 > 31 dB

(in the band of 1.5 GHz-1.7 GHz with a variation of less than 1 dB)

  • S11 < -12 dB

  • S22 < -10 dB

The test results show that the design has good small signal performance. Using Agilent's signal generator N5182A and spectrometer N9030A to build the test platform, inputting continuous wave (CW) and the performance of the balanced power amplifier is measured at 1.5,1.616 and 1.7 GHz, as shown in figure 8.

It can be seen from the diagram that the gain of the balanced power amplifier in the frequency band is about 32 dB, the in-band gain flatness is ±0.3 dB, the saturation power is more than 38 dBm/6.3 WN, and the power additional efficiency is greater than 43 dB.

At the same time, according to the gain curve of each frequency point, the balanced power amplifier has good AM-AM characteristic and 1dB compression point is about 37 dBm. The third order intermodulation distortion (IMD3) and the fifth order intermodulation distortion (IMD5) of the balanced power amplifier are measured by using a two-tone signal with a deviation of 2 MHz, as shown in figure 9. The results show that the balanced power amplifier has good linearity.

In general, the balanced power amplifier not only has high gain, high output power and high efficiency, but also has good linearity. 

Figure 6 Chip physical diagram

Figure 7 S parameter test results

Figure 8 Test performance in frequency band when CW signal is input

In order to verify the tolerance of the balanced power amplifier to the load mismatch and the load insensitivity, and the balanced power amplifier can still work properly when VSWR=20:1, a microwave manual tuner is connected to the output of the power amplifier.

And when the working frequency is 1.616 GHz, the input power Pin=10 dBm and voltage standing-wave ratio VSWR=3:1, the output power of the balanced power amplifier changes with the reflection coefficient phase, as shown in Figure 10.

The figure shows that the output power is about 35.7 dBm, with a range of ±0.7 dBm. Therefore, the performance of the balanced power amplifier is stable when the load is mismatched to a certain extent.

Figure 9 Test performance of IMD3 and IMD5

Figure 10 Changes of output power when VSWR=3:1

Ⅳ. Conclusion

In this article, a high power balanced power amplifier is designed by using the balance architecture, the chip area is 8 mm×8 mm by using InGaP/GaAs HBT process and the total static current is about 310 mA at a operating voltage of 5V. When the CW signal is input, the gain can be up to 32 dBm in the band of 1.5-1.7 GHz, the saturation output power Psat is 38 dBm, and the additional power efficiency is 43%. Beyond that, it can still work stably when the load mismatches. This balanced power amplifier is practical, reliable and safe, and can be used in handheld terminal of the satellite communication and navigation system.



Reference

1. BERRETTA G, CRISTAUDO D, SCACCIANOCE S. A balanced CDMA2000 SiGe HBT load insensitive power amplifier[C]//2006 IEEE Radio and Wireless Conference.California: IEEE Press, 2006: 523-526.


2. ZHANG G, CHANG S, WANG A. WCDMA PCS handset front end module[C]//2006 IEEE MTT-S International Microwave Symposium Digest. California: IEEE Press,2006: 304-307.


3. ZHANG G, CHANG S, CHEN S, et al. Dual mode efficiency enhanced linear power amplifiers using a new balanced structure[C]//2009 IEEE Radio Frequency Integrated Circuits Symposium. Massachusetts: IEEE Press,2009: 245-248.



Book Suggestion

Designing Audio Power Amplifiers 1st Edition

This comprehensive book on audio power amplifier design will appeal to members of the professional audio engineering community as well as the hobbyist. Designing Audio Power Amplifiers begins with power amplifier design basics that a novice can understand and moves all the way through to in-depth design techniques for the very sophisticated audiophile and professional audio power amplifier designer. This is the single best source of knowledge for anyone who wants to design an audio power amplifier, whether for fun or profit.

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RF Power Amplifiers for Wireless Communications, Second Edition

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Distortion in Rf Power Amplifiers (Artech House Microwave Library)Feb 1, 2003

A treatment of distortion in RF power amplifiers. It seeks to offer guidance on designing easily linearizable systems that have low memory effects. The reader is offered a detailed understanding of how the matching impedances of a power amplifier and other RF circuits can be tuned to minimize overall distortion. It also demonstrates how to build models that can be used for distortion simulations.

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