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Kynix Part #: KY32-CY24233ZCT
Manufacturer Part#:


Product Category: IC Chips
Manufacturer: CYPRESS
  datasheetCY24233ZCT Datasheet
Package: TSOP
Quantity: 2788 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: CYPRESS
Product Category: IC Chips
Features, Applications

Two reference outputs (27.00 MHz) Two 33.8688-MHz outputs Two 512fs outputs (22.5792 MHz or 24.576 MHz) 27.00-MHz clock or crystal input or 3.0V operation (2.5V functional) High-drive outputs 16-pin TSSOP package

The is a clock generator solution that supports DVD digital disk players. It produces a complete set of clocks needed to support the entire system. All output clocks are synthesized from a single 27.00-MHz fundamental cut crystal or input reference clock. The output clocks are precisely synthesized to meet the systems low PPM error requirements.

Pin Number Pin Name 33-1Out 33-2Out FSEL I/O Pin Description 3.3V fixed-frequency 27.00-MHz clock outputs. See Table 1 on page 1 for frequency selection for test mode functionality. or 3.0V fixed frequency clock outputs. See Table 1 on page 1 for frequency selection. 3.3V fixed frequency 33.8688-MHz clock outputs. See Table 1 on page 1 for frequency selection for test mode functionality. Frequency selection input. This pin controls the frequency that is present on two 512 output clock pins. On-chip reference oscillator pin. Drives an external crystal. When an externally generated reference signal is used at XTI, this pin remains unconnected. Bypass with a proper capacitance to ground to match the external crystal's load capacitance. On-chip reference oscillator input pin. Requires either an external crystal (nominally 27 MHz) or externally generated reference signal. Bypass with a proper capacitance to ground to match the external crystal's load capacitance.

Internal pull up. If this input pin is asserted low, it will set this device into a test mode. See Table 1 on page 1.

Table 2. Maximum Lumped Capacitative Output Loads Clock 33-1Out,33-2Out, 512-1Out,512-2Out Max Load 25 15 Units pF

The FSEL input is used to select the frequency of the clocks on the 512-1Out and 512-2Out pins. The device contains internal clock edge synchronization to insure that when the state of this pin is changed while the clocks are running no short (runt) or long (stretched) clocks will occur in the output streams. This is to say that the transitions will be made at a naturally occurring clock edge of the former clocks period and the cycle immediately after the change will of a full newly selected clocks period and duty cycle.

Finish Cycle Start at Full Cycle Wait

Notes: 1. Part may be operated with Pins 3,4,13,15 soldered to pads on PCB with no PCB trace connected to these pads, i.e., floating. 2. Table Nomenclature: All pin numbers with an asterisks immediately after them indicates that they have an internal pull-up resistor to ensure that they will be sensed as a logic HIGH even if no external circuitry is attached to them. I = Input pins, O = Output pins and PWR = Power connection pins.

Maximum Input Voltage Relative to VSS:............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature:................................. to +150°C Operating Temperature:................................ to +85°C Maximum ESD protection............................................... 2KV Maximum Power Supply:................................................5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).

Operating Voltage:...................................................2.5-3.6V DC Parameters (VDD +75°C or VDD to +85°C) Parameter VIL VIH IIL Description Input Low Voltage

Input High Voltage Input Low Current For internal Pull-up resistors[3,5] IIL measured at VIN = GND, IIH measured at VIN = VDD

Input High Current Input Hysteriss[3] Test 1, FSEL=1[6] Test 1, FSEL=1 IOL 4.0 mA IOH 4.0 mA

Dynamic Supply Current Dynamic Supply Current Output Low Voltage Output High Voltage Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance

Parameter TR TF TPU Tj2 Tj3 TXS Rise Time Fall Time Power up to Stable Output Clock Duty Cycle (all output clocks) Clock Jitter (33-1Out,33-2Out) Clock Jitter (512-1Out,512-2Out) Clock Jitter (27-1Out,27-2Out) Crystal Oscillator Start-up Time Description

Conditions All clocks at rated load All Output Clocks All clocks at rated load[9] Cycle to cycle jitter (Peak-Peak, 10,000 cycles ) All clocks at rated load[9]

Parameter TR TF TPU Rise Time Fall Time Power-up to Stable Output Description Conditions All clocks at rated load All output clocks

Notes: 3. Multiple Supplies:The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Applicable to input signal: FSEL and Test pins. 5. Although internal pull-up resistors have a typical value of 400K, this value may vary between 200K and 800K. 6. All outputs loaded as perTable 2 on page 2. 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 8. Measured between 0.2* VDD and 0.8*VDDV. 9. Triggering is done at 1.5V.

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