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Kynix Part #: KY32-ADSP-2188MKST-300
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Product Category: IC Chips
Manufacturer: ADI
  datasheetADSP-2188MKST-300 Datasheet
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Quantity: 500 PCS
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Manufacturer: ADI
Product Category: IC Chips
Features, Applications

Features Performance

13.3 ns Instruction Cycle Time 2.75 V (Internal), 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode.

System Interface Flexible I/O Structure Allows 3.3 V Operation; All Inputs Tolerate 3.6 V Regardless of Mode 16-Bit Internal DMA Port for High-Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits "Glueless" System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-PortTM Emulator Interface Supports Debugging in Final Systems

Integration ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions 256K Bytes of On-Chip RAM, Configured as 48K Words Program Memory RAM 56K Words Data Memory RAM Dual-Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA


Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: Fax: 781/326-8703 c Analog Devices, Inc., 2000

FEATURES. 1 FUNCTIONAL BLOCK DIAGRAM. 1 GENERAL DESCRIPTION. 3 DEVELOPMENT SYSTEM. 3 Additional Information. 3 ARCHITECTURE OVERVIEW. 4 Serial Ports. 5 PIN DESCRIPTIONS. 5 Common-Mode Pins. 6 Memory Interface Pins. 7 Full Memory Mode Pins (Mode 0). 7 Host Mode Pins (Mode 1). 7 Terminating Unused Pins. 8 Pin Terminations. 8 Interrupts. 9 LOW POWER OPERATION. 9 Power-Down. 9 Idle. 9 Slow Idle. 9 SYSTEM INTERFACE. 10 Clock Signals. 10 RESET. 11 Power Supplies. 11 MODES OF OPERATION. 11 Setting Memory Mode. 11 Passive Configuration. 11 Active Configuration. 11 IACK Configuration. 12 MEMORY ARCHITECTURE. 12 Program Memory. 12 Data Memory. 13 Memory Mapped Registers (New to the ADSP-2188M). 13 I/O Space (Full Memory Mode). 14 Composite Memory Select (CMS). 14 Byte Memory Select (BMS). 14 Byte Memory. 14 Byte Memory DMA (BDMA, Full Memory Mode). 14 Internal Memory DMA Port (IDMA Port; Host Memory Mode). 15 Bootstrap Loading (Booting). 16 IDMA Port Booting. 16 Bus Request and Bus Grant. 16 Flag I/O Pins. 16 Instruction Set Description. 17 DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM. 17 Target Board Connector for EZ-ICE Probe. 18 Target Memory Interface. 18 PM, DM, BM, IOM, AND CM. 18 Target System Interface Signals. 18

RECOMMENDED OPERATING CONDITIONS. ELECTRICAL CHARACTERISTICS. ABSOLUTE MAXIMUM RATINGS. TIMING SPECIFICATIONS. GENERAL NOTES. TIMING NOTES. MEMORY TIMING SPECIFICATIONS. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS. ENVIRONMENTAL CONDITIONS. POWER DISSIPATION. Output Drive Currents. Capacitive Loading. TEST CONDITIONS. Output Disable Time. Output Enable Time. Clock Signals and Reset. Interrupts and Flags. Bus Request-Bus Grant. Memory Read. Memory Write. Serial Ports. IDMA Address Latch. IDMA Write, Short Write Cycle. IDMA Write, Long Write Cycle. IDMA Read, Long Read Cycle. IDMA Read, Short Read Cycle. IDMA Read, Short Read Cycle in Short Read Only Mode. 100-LEAD LQFP PIN CONFIGURATION. LQFP Package Pinout. 144-Ball Mini-BGA Package Pinout. Mini-BGA Package Pinout. OUTLINE DIMENSIONS 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100). OUTLINE DIMENSIONS 144-Ball Mini-BGA (CA-144). ORDERING GUIDE.

Table I. Interrupt Priority and Interrupt Vector Addresses. 9 Table II. Modes of Operation. 11 Table III. PMOVLAY Bits. 12 Table IV. DMOVLAY Bits. 13 Table V. Wait States. 14 Table VI. Data Formats. 14

The is a single-chip microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The ADSP-2188M combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2188M integrates 256K bytes of on-chip memory configured as 48K words (24-bit) of program RAM, and 56K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2188M is available a 100-lead LQFP package and 144 Ball Mini-BGA. In addition, the ADSP-2188M supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test-- new ALU constants, new multiplication instruction squared), biased rounding, result-free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2188M operates with 13.3 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2188M's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2188M can: Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer

The EZ-KIT Lite is a hardware/software kit offering a complete evaluation environment for the ADSP-218x family: an ADSP2189M-based evaluation board with PC monitor software plus assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: 75 MHz ADSP-2189M Full 16-Bit Stereo Audio I/O with AD73322 Codec RS-232 Interface EZ-ICE Connector for Emulator Control DSP Demo Programs Evaluation Suite of VisualDSP

The ADSP-218x EZ-ICER Emulator aids in the hardware debugging an ADSP-2188M system. The ADSP-2188M integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2188M device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: In-target operation to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging

This takes place while the processor continues to:

See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE-Compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector.

The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2188M. The System Builder provides a high-level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display different portions of the hardware environment.

This data sheet provides a general overview of ADSP-2188M functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User's Manual. For more information about the development tools, refer to the ADSP-2100 Family Development Tools data sheet.

EZ-ICE is a registered trademark of Analog Devices, Inc.

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