CY25560SCT
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CY25560SCT

Product Category: IC Chips
Manufacturer: CYPRESS
Description:
  datasheetCY25560SCT Datasheet
Package: SOP8
Quantity: 523 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: CYPRESS
Product Category: IC Chips
Features, Applications

Features

to 100-MHz operating frequency range Wide (9) range of spread selections Accepts clock and crystal inputs Low power dissipation: mW @ Fin = 25 MHz mW @ Fin = 65 MHz mW @ Fin = 100 MHz Frequency spread disable function Center spread modulation Low cycle-to cycle jitter 8-pin SOIC package


Applications

Desktop, notebook, and tablet PCs VGA controllers LCD panels and monitors Printers and multifunction devices (MFP)


Peak electromagnetic interference (EMI) reduction to 16 dB Fast time to market Cost reduction


Pin Number Pin Name Xin/CLK VDD GND SSCLK SSCC S1 Type Positive power supply. Power supply ground. Modulated clock output which is the same frequency as the input clock or the crystal frequency. Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled when input is HIGH and disabled when input is LOW. This pin is pulled high internally. Tri-level logic input control pin used to select input frequency range and spread percent. Refer to tri-level logic on page 3 for programming details. Pin 6 has internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1. Tri-level logic input control pin used to select input frequency range and spread percent. Refer to tri-level logic on page 3 for programming details. Pin 7 has internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1. Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock is used to drive XIN/CLK input (pin-1). Pin Description Clock or crystal connection input. Refer to Table 1 for input frequency range selection.


The CYPRESS is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing EMI found in today's high-speed digital electronic systems. The CY25560 uses a CYPRESS proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies of Clock (SSCLK) is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance. The is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L) and Middle (M) logic levels to select Table 1. Frequency and Spread% Selection (Center Spread)


Select the Frequency and Center Spread % desired and then set S0 as indicated.

one of the nine available Spread % ranges. Refer to Table 1 for programming details. The CY25560 is optimized for SVGA (40-MHz) and XVGA (65-MHz) Controller clocks and also suitable for the applications where the frequency range to 100 MHz. A wide range of digitally selectable spread percentages is made possible by using three-level (High, Low, and Middle) logic at the S0 and S1 digital control inputs. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread Spectrum Clock Control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. The CY25560 is available in an eight-pin SOIC package with to 70°C operating temperature range.


Select the Frequency and Center Spread % desired and then set S0 as indicated.

With binary logic, four states can be programmed with two control lines whereas three-level logic can program nine logic states using two control lines. Three-level logic in the CY25560 is implemented by defining a third logic state in addition to the standard logic "1" and "0." Pins 6 and 7 of the CY25560 recognize a logic state by the voltage applied to the respective pin. These states are defined as "0" (Low), "M" (Middle), and "1" (One). Each of these states have a defined voltage range that is interpreted by the a "0", "M" or "1" logic state. Refer to Table 3 for voltage ranges for each logic state. The CY25560 has two equal value resistor dividers connected internally to Pins 6 and 7 that produce the default "M" (Middle) state if these pins are left unconnected (NC). Pins 6 and/or 7 can be tied directly to ground or VDD to program a Logic or "1" state, respectively.


The is a PLL-type clock generator using a proprietary Cypress design. By precisely controlling the bandwidth of the output clock, the CY25560 becomes a Low-EMI clock generator. The theory and detailed operation of the CY25560 will be discussed in the following sections. EMI All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50%. Because of this 50/50-duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, etc. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for EMI. Conventional methods of reducing EMI have been to use shielding, filtering, multilayer PCBs, etc. The CY25560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q. SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. The CY25560 takes a narrow band digital reference clock in the range of 25-100 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 65-MHz clock with a 50% duty cycle. From a 65-MHz clock we know the following: Document 38-07425 Rev.


If this clock is applied to the Xin/CLK pin of CY25560, the output clock at pin 4 (SSCLK) will be sweeping back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition from to F2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 2 shows the modulation profile a 65 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 2 also shows a scan of the same SSCG clock using a spectrum analyzer. In this scan you can see a 6.48-dB reduction in the peak RF energy when using the SSCG clock. Modulation Rate Spectrum Spread Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmod. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. The CY25560 has a fixed divider count of 1166. Page of 7

Search Part number : "CY255" Included word is 14
Part Number Manufacturer Package Quantity Description
CY25561SXC-TBB CYPRESS SOP-8 1207
CY25562SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 94 IC CLOCK GEN 3.3V SS 8-SOIC
CY25568SXCT Cypress Semiconductor Corp 16-SOIC (0.154", 3.90mm Width) 3054 IC CLOCK GEN 3.3V SS 16SOIC
CY25560SC CY SOP-8 611
CY25560SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 3900 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560-SXC CYTRESS SOP8 161
CY25560SXCT Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 27776 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560SXC-T CYPREE 8-SOIC (0.154", 3.90mm Width) 1150 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560-SXI CY SOP8 3692
CY25560SXIT Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 9060 IC CLOCK GEN 3.3V SS 8-SOIC
CY25561-SC CY SOP8 96500
CY25561SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 88 IC CLOCK GEN 3.3V SS 8-SOIC
CY25561-SC CYPRESS 96500
CY25561SXCT Cypress Semiconductor Corp SOP-8 2464 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560SCT RELATED PRODUCT PICTURE
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  • CY25561SXC-TBB
  • CY25562SXC
  • CY25568SXCT
  • CY25560SC
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  • CY25560-SXC
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  • CY25560SXC-T
  • CY25560-SXI
  • CY25560SXIT
  • CY25561-SC
  • CY25561SXC
  • CY25561-SC
  • CY25561SXCT
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